1 //===- SPURegisterInfo.cpp - Cell SPU Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "SPURegisterInfo.h"
17 #include "SPURegisterNames.h"
18 #include "SPUInstrBuilder.h"
19 #include "SPUSubtarget.h"
20 #include "SPUMachineFunction.h"
21 #include "SPUFrameInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGNodes.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/ADT/BitVector.h"
41 #include "llvm/ADT/STLExtras.h"
47 /// getRegisterNumbering - Given the enum value for some register, e.g.
48 /// PPC::F14, return the number that it corresponds to (e.g. 14).
49 unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
52 case SPU::R0: return 0;
53 case SPU::R1: return 1;
54 case SPU::R2: return 2;
55 case SPU::R3: return 3;
56 case SPU::R4: return 4;
57 case SPU::R5: return 5;
58 case SPU::R6: return 6;
59 case SPU::R7: return 7;
60 case SPU::R8: return 8;
61 case SPU::R9: return 9;
62 case SPU::R10: return 10;
63 case SPU::R11: return 11;
64 case SPU::R12: return 12;
65 case SPU::R13: return 13;
66 case SPU::R14: return 14;
67 case SPU::R15: return 15;
68 case SPU::R16: return 16;
69 case SPU::R17: return 17;
70 case SPU::R18: return 18;
71 case SPU::R19: return 19;
72 case SPU::R20: return 20;
73 case SPU::R21: return 21;
74 case SPU::R22: return 22;
75 case SPU::R23: return 23;
76 case SPU::R24: return 24;
77 case SPU::R25: return 25;
78 case SPU::R26: return 26;
79 case SPU::R27: return 27;
80 case SPU::R28: return 28;
81 case SPU::R29: return 29;
82 case SPU::R30: return 30;
83 case SPU::R31: return 31;
84 case SPU::R32: return 32;
85 case SPU::R33: return 33;
86 case SPU::R34: return 34;
87 case SPU::R35: return 35;
88 case SPU::R36: return 36;
89 case SPU::R37: return 37;
90 case SPU::R38: return 38;
91 case SPU::R39: return 39;
92 case SPU::R40: return 40;
93 case SPU::R41: return 41;
94 case SPU::R42: return 42;
95 case SPU::R43: return 43;
96 case SPU::R44: return 44;
97 case SPU::R45: return 45;
98 case SPU::R46: return 46;
99 case SPU::R47: return 47;
100 case SPU::R48: return 48;
101 case SPU::R49: return 49;
102 case SPU::R50: return 50;
103 case SPU::R51: return 51;
104 case SPU::R52: return 52;
105 case SPU::R53: return 53;
106 case SPU::R54: return 54;
107 case SPU::R55: return 55;
108 case SPU::R56: return 56;
109 case SPU::R57: return 57;
110 case SPU::R58: return 58;
111 case SPU::R59: return 59;
112 case SPU::R60: return 60;
113 case SPU::R61: return 61;
114 case SPU::R62: return 62;
115 case SPU::R63: return 63;
116 case SPU::R64: return 64;
117 case SPU::R65: return 65;
118 case SPU::R66: return 66;
119 case SPU::R67: return 67;
120 case SPU::R68: return 68;
121 case SPU::R69: return 69;
122 case SPU::R70: return 70;
123 case SPU::R71: return 71;
124 case SPU::R72: return 72;
125 case SPU::R73: return 73;
126 case SPU::R74: return 74;
127 case SPU::R75: return 75;
128 case SPU::R76: return 76;
129 case SPU::R77: return 77;
130 case SPU::R78: return 78;
131 case SPU::R79: return 79;
132 case SPU::R80: return 80;
133 case SPU::R81: return 81;
134 case SPU::R82: return 82;
135 case SPU::R83: return 83;
136 case SPU::R84: return 84;
137 case SPU::R85: return 85;
138 case SPU::R86: return 86;
139 case SPU::R87: return 87;
140 case SPU::R88: return 88;
141 case SPU::R89: return 89;
142 case SPU::R90: return 90;
143 case SPU::R91: return 91;
144 case SPU::R92: return 92;
145 case SPU::R93: return 93;
146 case SPU::R94: return 94;
147 case SPU::R95: return 95;
148 case SPU::R96: return 96;
149 case SPU::R97: return 97;
150 case SPU::R98: return 98;
151 case SPU::R99: return 99;
152 case SPU::R100: return 100;
153 case SPU::R101: return 101;
154 case SPU::R102: return 102;
155 case SPU::R103: return 103;
156 case SPU::R104: return 104;
157 case SPU::R105: return 105;
158 case SPU::R106: return 106;
159 case SPU::R107: return 107;
160 case SPU::R108: return 108;
161 case SPU::R109: return 109;
162 case SPU::R110: return 110;
163 case SPU::R111: return 111;
164 case SPU::R112: return 112;
165 case SPU::R113: return 113;
166 case SPU::R114: return 114;
167 case SPU::R115: return 115;
168 case SPU::R116: return 116;
169 case SPU::R117: return 117;
170 case SPU::R118: return 118;
171 case SPU::R119: return 119;
172 case SPU::R120: return 120;
173 case SPU::R121: return 121;
174 case SPU::R122: return 122;
175 case SPU::R123: return 123;
176 case SPU::R124: return 124;
177 case SPU::R125: return 125;
178 case SPU::R126: return 126;
179 case SPU::R127: return 127;
181 std::cerr << "Unhandled reg in SPURegisterInfo::getRegisterNumbering!\n";
186 SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
187 const TargetInstrInfo &tii) :
188 SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
189 Subtarget(subtarget),
194 void SPURegisterInfo::reMaterialize(MachineBasicBlock &MBB,
195 MachineBasicBlock::iterator I,
197 const MachineInstr *Orig) const {
198 MachineInstr *MI = Orig->clone();
199 MI->getOperand(0).setReg(DestReg);
203 // SPU's 128-bit registers used for argument passing:
204 static const unsigned SPU_ArgRegs[] = {
205 SPU::R3, SPU::R4, SPU::R5, SPU::R6, SPU::R7, SPU::R8, SPU::R9,
206 SPU::R10, SPU::R11, SPU::R12, SPU::R13, SPU::R14, SPU::R15, SPU::R16,
207 SPU::R17, SPU::R18, SPU::R19, SPU::R20, SPU::R21, SPU::R22, SPU::R23,
208 SPU::R24, SPU::R25, SPU::R26, SPU::R27, SPU::R28, SPU::R29, SPU::R30,
209 SPU::R31, SPU::R32, SPU::R33, SPU::R34, SPU::R35, SPU::R36, SPU::R37,
210 SPU::R38, SPU::R39, SPU::R40, SPU::R41, SPU::R42, SPU::R43, SPU::R44,
211 SPU::R45, SPU::R46, SPU::R47, SPU::R48, SPU::R49, SPU::R50, SPU::R51,
212 SPU::R52, SPU::R53, SPU::R54, SPU::R55, SPU::R56, SPU::R57, SPU::R58,
213 SPU::R59, SPU::R60, SPU::R61, SPU::R62, SPU::R63, SPU::R64, SPU::R65,
214 SPU::R66, SPU::R67, SPU::R68, SPU::R69, SPU::R70, SPU::R71, SPU::R72,
215 SPU::R73, SPU::R74, SPU::R75, SPU::R76, SPU::R77, SPU::R78, SPU::R79
219 SPURegisterInfo::getArgRegs()
225 SPURegisterInfo::getNumArgRegs()
227 return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]);
231 SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
233 // Cell ABI calling convention
234 static const unsigned SPU_CalleeSaveRegs[] = {
235 SPU::R80, SPU::R81, SPU::R82, SPU::R83,
236 SPU::R84, SPU::R85, SPU::R86, SPU::R87,
237 SPU::R88, SPU::R89, SPU::R90, SPU::R91,
238 SPU::R92, SPU::R93, SPU::R94, SPU::R95,
239 SPU::R96, SPU::R97, SPU::R98, SPU::R99,
240 SPU::R100, SPU::R101, SPU::R102, SPU::R103,
241 SPU::R104, SPU::R105, SPU::R106, SPU::R107,
242 SPU::R108, SPU::R109, SPU::R110, SPU::R111,
243 SPU::R112, SPU::R113, SPU::R114, SPU::R115,
244 SPU::R116, SPU::R117, SPU::R118, SPU::R119,
245 SPU::R120, SPU::R121, SPU::R122, SPU::R123,
246 SPU::R124, SPU::R125, SPU::R126, SPU::R127,
247 SPU::R2, /* environment pointer */
248 SPU::R1, /* stack pointer */
249 SPU::R0, /* link register */
253 return SPU_CalleeSaveRegs;
256 const TargetRegisterClass* const*
257 SPURegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
259 // Cell ABI Calling Convention
260 static const TargetRegisterClass * const SPU_CalleeSaveRegClasses[] = {
261 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
262 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
263 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
264 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
265 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
266 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
267 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
268 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
269 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
270 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
271 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
272 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
273 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
274 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
275 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
276 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
277 &SPU::GPRCRegClass, /* environment pointer */
278 &SPU::GPRCRegClass, /* stack pointer */
279 &SPU::GPRCRegClass, /* link register */
283 return SPU_CalleeSaveRegClasses;
287 R0 (link register), R1 (stack pointer) and R2 (environment pointer -- this is
288 generally unused) are the Cell's reserved registers
290 BitVector SPURegisterInfo::getReservedRegs(const MachineFunction &MF) const {
291 BitVector Reserved(getNumRegs());
292 Reserved.set(SPU::R0); // LR
293 Reserved.set(SPU::R1); // SP
294 Reserved.set(SPU::R2); // environment pointer
298 //===----------------------------------------------------------------------===//
299 // Stack Frame Processing methods
300 //===----------------------------------------------------------------------===//
302 // needsFP - Return true if the specified function should have a dedicated frame
303 // pointer register. This is true if the function has variable sized allocas or
304 // if frame pointer elimination is disabled.
306 static bool needsFP(const MachineFunction &MF) {
307 const MachineFrameInfo *MFI = MF.getFrameInfo();
308 return NoFramePointerElim || MFI->hasVarSizedObjects();
311 //--------------------------------------------------------------------------
312 // hasFP - Return true if the specified function actually has a dedicated frame
313 // pointer register. This is true if the function needs a frame pointer and has
314 // a non-zero stack size.
316 SPURegisterInfo::hasFP(const MachineFunction &MF) const {
317 const MachineFrameInfo *MFI = MF.getFrameInfo();
318 return MFI->getStackSize() && needsFP(MF);
321 //--------------------------------------------------------------------------
323 SPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
324 MachineBasicBlock &MBB,
325 MachineBasicBlock::iterator I)
328 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
333 SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
334 RegScavenger *RS) const
337 MachineInstr &MI = *II;
338 MachineBasicBlock &MBB = *MI.getParent();
339 MachineFunction &MF = *MBB.getParent();
340 MachineFrameInfo *MFI = MF.getFrameInfo();
342 while (!MI.getOperand(i).isFrameIndex()) {
344 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
347 MachineOperand &SPOp = MI.getOperand(i);
348 int FrameIndex = SPOp.getIndex();
350 // Now add the frame object offset to the offset from r1.
351 int Offset = MFI->getObjectOffset(FrameIndex);
353 // Most instructions, except for generated FrameIndex additions using AIr32,
354 // have the immediate in operand 1. AIr32, in this case, has the immediate
356 unsigned OpNo = (MI.getOpcode() != SPU::AIr32 ? 1 : 2);
357 MachineOperand &MO = MI.getOperand(OpNo);
359 // Offset is biased by $lr's slot at the bottom.
360 Offset += MO.getImm() + MFI->getStackSize() + SPUFrameInfo::minStackSize();
361 assert((Offset & 0xf) == 0
362 && "16-byte alignment violated in eliminateFrameIndex");
364 // Replace the FrameIndex with base register with $sp (aka $r1)
365 SPOp.ChangeToRegister(SPU::R1, false);
366 if (Offset > SPUFrameInfo::maxFrameOffset()
367 || Offset < SPUFrameInfo::minFrameOffset()) {
368 cerr << "Large stack adjustment ("
370 << ") in SPURegisterInfo::eliminateFrameIndex.";
372 MO.ChangeToImmediate(Offset);
376 /// determineFrameLayout - Determine the size of the frame and maximum call
379 SPURegisterInfo::determineFrameLayout(MachineFunction &MF) const
381 MachineFrameInfo *MFI = MF.getFrameInfo();
383 // Get the number of bytes to allocate from the FrameInfo
384 unsigned FrameSize = MFI->getStackSize();
386 // Get the alignments provided by the target, and the maximum alignment
387 // (if any) of the fixed frame objects.
388 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
389 unsigned Align = std::max(TargetAlign, MFI->getMaxAlignment());
390 assert(isPowerOf2_32(Align) && "Alignment is not power of 2");
391 unsigned AlignMask = Align - 1;
393 // Get the maximum call frame size of all the calls.
394 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
396 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
397 // that allocations will be aligned.
398 if (MFI->hasVarSizedObjects())
399 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
401 // Update maximum call frame size.
402 MFI->setMaxCallFrameSize(maxCallFrameSize);
404 // Include call frame size in total.
405 FrameSize += maxCallFrameSize;
407 // Make sure the frame is aligned.
408 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
410 // Update frame info.
411 MFI->setStackSize(FrameSize);
414 void SPURegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
418 // Save and clear the LR state.
419 SPUFunctionInfo *FI = MF.getInfo<SPUFunctionInfo>();
420 FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
422 // Mark LR and SP unused, since the prolog spills them to stack and
423 // we don't want anyone else to spill them for us.
425 // Also, unless R2 is really used someday, don't spill it automatically.
426 MF.getRegInfo().setPhysRegUnused(SPU::R0);
427 MF.getRegInfo().setPhysRegUnused(SPU::R1);
428 MF.getRegInfo().setPhysRegUnused(SPU::R2);
431 void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
433 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
434 MachineBasicBlock::iterator MBBI = MBB.begin();
435 MachineFrameInfo *MFI = MF.getFrameInfo();
436 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
438 // Prepare for debug frame info.
439 bool hasDebugInfo = MMI && MMI->hasDebugInfo();
440 unsigned FrameLabelId = 0;
442 // Move MBBI back to the beginning of the function.
445 // Work out frame sizes.
446 determineFrameLayout(MF);
447 int FrameSize = MFI->getStackSize();
449 assert((FrameSize & 0xf) == 0
450 && "SPURegisterInfo::emitPrologue: FrameSize not aligned");
453 FrameSize = -(FrameSize + SPUFrameInfo::minStackSize());
455 // Mark effective beginning of when frame pointer becomes valid.
456 FrameLabelId = MMI->NextLabelID();
457 BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(FrameLabelId).addImm(0);
460 // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
462 BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
464 if (isS10Constant(FrameSize)) {
465 // Spill $sp to adjusted $sp
466 BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
468 // Adjust $sp by required amout
469 BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
471 } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
472 // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
473 // $r2 to adjust $sp:
474 BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2)
477 BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
479 BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1)
482 BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1)
485 BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2)
488 BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2)
492 cerr << "Unhandled frame size: " << FrameSize << "\n";
497 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
499 // Show update of SP.
500 MachineLocation SPDst(MachineLocation::VirtualFP);
501 MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize);
502 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
504 // Add callee saved registers to move list.
505 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
506 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
507 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
508 unsigned Reg = CSI[I].getReg();
509 if (Reg == SPU::R0) continue;
510 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
511 MachineLocation CSSrc(Reg);
512 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
515 // Mark effective beginning of when frame pointer is ready.
516 unsigned ReadyLabelId = MMI->NextLabelID();
517 BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(ReadyLabelId).addImm(0);
519 MachineLocation FPDst(SPU::R1);
520 MachineLocation FPSrc(MachineLocation::VirtualFP);
521 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
524 // This is a leaf function -- insert a branch hint iff there are
525 // sufficient number instructions in the basic block. Note that
526 // this is just a best guess based on the basic block's size.
527 if (MBB.size() >= (unsigned) SPUFrameInfo::branchHintPenalty()) {
528 MachineBasicBlock::iterator MBBI = prior(MBB.end());
529 // Insert terminator label
530 unsigned BranchLabelId = MMI->NextLabelID();
531 BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(BranchLabelId).addImm(0);
537 SPURegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
539 MachineBasicBlock::iterator MBBI = prior(MBB.end());
540 const MachineFrameInfo *MFI = MF.getFrameInfo();
541 int FrameSize = MFI->getStackSize();
542 int LinkSlotOffset = SPUFrameInfo::stackSlotSize();
544 assert(MBBI->getOpcode() == SPU::RET &&
545 "Can only insert epilog into returning blocks");
546 assert((FrameSize & 0xf) == 0
547 && "SPURegisterInfo::emitEpilogue: FrameSize not aligned");
549 FrameSize = FrameSize + SPUFrameInfo::minStackSize();
550 if (isS10Constant(FrameSize + LinkSlotOffset)) {
551 // Reload $lr, adjust $sp by required amount
552 // Note: We do this to slightly improve dual issue -- not by much, but it
553 // is an opportunity for dual issue.
554 BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0)
555 .addImm(FrameSize + LinkSlotOffset)
557 BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1)
560 } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
561 // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
562 // $r2 to adjust $sp:
563 BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2)
566 BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
568 BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1)
571 BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0)
574 BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2).
577 BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2)
581 cerr << "Unhandled frame size: " << FrameSize << "\n";
588 SPURegisterInfo::getRARegister() const
594 SPURegisterInfo::getFrameRegister(MachineFunction &MF) const
600 SPURegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const
602 // Initial state of the frame pointer is R1.
603 MachineLocation Dst(MachineLocation::VirtualFP);
604 MachineLocation Src(SPU::R1, 0);
605 Moves.push_back(MachineMove(0, Dst, Src));
610 SPURegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
611 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
612 return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
615 #include "SPUGenRegisterInfo.inc"