1 //===- SPUOperands.td - Cell SPU Instruction Operands ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by a team from the Computer Systems Research
6 // Department at The Aerospace Corporation and is distributed under the
7 // University of Illinois Open Source License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
10 // Cell SPU Instruction Operands:
11 //===----------------------------------------------------------------------===//
13 def LO16 : SDNodeXForm<imm, [{
14 unsigned val = N->getValue();
15 // Transformation function: get the low 16 bits.
16 return getI32Imm(val & 0xffff);
19 def LO16_vec : SDNodeXForm<scalar_to_vector, [{
20 SDOperand OpVal(0, 0);
22 // Transformation function: get the low 16 bit immediate from a build_vector
24 assert(N->getOpcode() == ISD::BUILD_VECTOR
25 && "LO16_vec got something other than a BUILD_VECTOR");
27 // Get first constant operand...
28 for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
29 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
31 OpVal = N->getOperand(i);
34 assert(OpVal.Val != 0 && "LO16_vec did not locate a <defined> node");
35 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal);
36 return getI32Imm((unsigned)CN->getValue() & 0xffff);
39 // Transform an immediate, returning the high 16 bits shifted down:
40 def HI16 : SDNodeXForm<imm, [{
41 return getI32Imm((unsigned)N->getValue() >> 16);
44 // Transformation function: shift the high 16 bit immediate from a build_vector
45 // node into the low 16 bits, and return a 16-bit constant.
46 def HI16_vec : SDNodeXForm<scalar_to_vector, [{
47 SDOperand OpVal(0, 0);
49 assert(N->getOpcode() == ISD::BUILD_VECTOR
50 && "HI16_vec got something other than a BUILD_VECTOR");
52 // Get first constant operand...
53 for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
54 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
56 OpVal = N->getOperand(i);
59 assert(OpVal.Val != 0 && "HI16_vec did not locate a <defined> node");
60 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal);
61 return getI32Imm((unsigned)CN->getValue() >> 16);
64 // simm7 predicate - True if the immediate fits in an 7-bit signed
66 def simm7: PatLeaf<(imm), [{
67 int sextVal = ((((int) N->getValue()) << 25) >> 25);
68 return (sextVal >= -64 && sextVal <= 63);
71 // uimm7 predicate - True if the immediate fits in an 7-bit unsigned
73 def uimm7: PatLeaf<(imm), [{
74 return (N->getValue() <= 0x7f);
77 // immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
79 def immSExt8 : PatLeaf<(imm), [{
80 int Value = (int) N->getValue();
81 int Value8 = (Value << 24) >> 24;
82 return (Value < 0xff && (Value8 >= -128 && Value8 < 127));
85 // immU8: immediate, unsigned 8-bit quantity
86 def immU8 : PatLeaf<(imm), [{
87 return (N->getValue() <= 0xff);
90 // i64ImmSExt10 predicate - True if the i64 immediate fits in a 10-bit sign
91 // extended field. Used by RI10Form instructions like 'ldq'.
92 def i64ImmSExt10 : PatLeaf<(imm), [{
93 return isI64IntS10Immediate(N);
96 // i32ImmSExt10 predicate - True if the i32 immediate fits in a 10-bit sign
97 // extended field. Used by RI10Form instructions like 'ldq'.
98 def i32ImmSExt10 : PatLeaf<(imm), [{
99 return isI32IntS10Immediate(N);
102 // i16ImmSExt10 predicate - True if the i32 immediate fits in a 10-bit sign
103 // extended field. Used by RI10Form instructions like 'ldq'.
104 def i16ImmSExt10 : PatLeaf<(imm), [{
105 return isI16IntS10Immediate(N);
108 def immSExt16 : PatLeaf<(imm), [{
109 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
112 return isIntS16Immediate(N, Ignored);
115 def immZExt16 : PatLeaf<(imm), [{
116 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
118 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
121 def immU16 : PatLeaf<(imm), [{
122 // immU16 predicate- True if the immediate fits into a 16-bit unsigned field.
123 return (uint64_t)N->getValue() == (N->getValue() & 0xffff);
126 def imm18 : PatLeaf<(imm), [{
127 // imm18 predicate: True if the immediate fits into an 18-bit unsigned field.
128 int Value = (int) N->getValue();
129 return ((Value & ((1 << 19) - 1)) == Value);
132 def hi16 : PatLeaf<(imm), [{
133 // hi16 predicate - returns true if the immediate has all zeros in the
134 // low order bits and is a 32-bit constant:
135 if (N->getValueType(0) == MVT::i32) {
136 uint32_t val = N->getValue();
137 return ((val & 0xffff0000) == val);
143 //===----------------------------------------------------------------------===//
144 // Floating point operands:
145 //===----------------------------------------------------------------------===//
147 // Transform a float, returning the high 16 bits shifted down, as if
148 // the float was really an unsigned integer:
149 def HI16_f32 : SDNodeXForm<fpimm, [{
150 const APFloat &apf = N->getValueAPF();
151 float fval = apf.convertToFloat();
152 unsigned val = *((unsigned *) &fval);
153 return getI32Imm(val >> 16);
156 // Transformation function on floats: get the low 16 bits as if the float was
157 // an unsigned integer.
158 def LO16_f32 : SDNodeXForm<fpimm, [{
159 const APFloat &apf = N->getValueAPF();
160 float fval = apf.convertToFloat();
161 unsigned val = *((unsigned *) &fval);
162 return getI32Imm(val & 0xffff);
165 def FPimm_sext16 : SDNodeXForm<fpimm, [{
166 const APFloat &apf = N->getValueAPF();
167 float fval = apf.convertToFloat();
168 unsigned val = *((unsigned *) &fval);
169 return getI32Imm((int) ((val << 16) >> 16));
172 def FPimm_u18 : SDNodeXForm<fpimm, [{
173 const APFloat &apf = N->getValueAPF();
174 float fval = apf.convertToFloat();
175 unsigned val = *((unsigned *) &fval);
176 return getI32Imm(val & ((1 << 19) - 1));
179 def fpimmSExt16 : PatLeaf<(fpimm), [{
181 return isFPS16Immediate(N, Ignored);
184 // Does the SFP constant only have upp 16 bits set?
185 def hi16_f32 : PatLeaf<(fpimm), [{
186 if (N->getValueType(0) == MVT::f32) {
187 const APFloat &apf = N->getValueAPF();
188 float fval = apf.convertToFloat();
189 uint32_t val = *((unsigned *) &fval);
190 return ((val & 0xffff0000) == val);
196 // Does the SFP constant fit into 18 bits?
197 def fpimm18 : PatLeaf<(fpimm), [{
198 if (N->getValueType(0) == MVT::f32) {
199 const APFloat &apf = N->getValueAPF();
200 float fval = apf.convertToFloat();
201 uint32_t Value = *((uint32_t *) &fval);
202 return ((Value & ((1 << 19) - 1)) == Value);
208 //===----------------------------------------------------------------------===//
210 //===----------------------------------------------------------------------===//
212 //===----------------------------------------------------------------------===//
213 // build_vector operands:
214 //===----------------------------------------------------------------------===//
216 // v16i8SExt8Imm_xform function: convert build_vector to 8-bit sign extended
217 // immediate constant load for v16i8 vectors. N.B.: The incoming constant has
218 // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
219 def v16i8SExt8Imm_xform: SDNodeXForm<build_vector, [{
220 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
223 // v16i8SExt8Imm: Predicate test for 8-bit sign extended immediate constant
224 // load, works in conjunction with its transform function. N.B.: This relies the
225 // incoming constant being a 16-bit quantity, where the upper and lower bytes
226 // are EXACTLY the same (e.g., 0x2a2a)
227 def v16i8SExt8Imm: PatLeaf<(build_vector), [{
228 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
229 }], v16i8SExt8Imm_xform>;
231 // v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
232 // immediate constant load for v16i8 vectors. N.B.: The incoming constant has
233 // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
234 def v16i8U8Imm_xform: SDNodeXForm<build_vector, [{
235 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
238 // v16i8U8Imm: Predicate test for unsigned 8-bit immediate constant
239 // load, works in conjunction with its transform function. N.B.: This relies the
240 // incoming constant being a 16-bit quantity, where the upper and lower bytes
241 // are EXACTLY the same (e.g., 0x2a2a)
242 def v16i8U8Imm: PatLeaf<(build_vector), [{
243 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
244 }], v16i8U8Imm_xform>;
246 // v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign extended
247 // immediate constant load for v8i16 vectors.
248 def v8i16SExt8Imm_xform: SDNodeXForm<build_vector, [{
249 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16);
252 // v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate constant
253 // load, works in conjunction with its transform function.
254 def v8i16SExt8Imm: PatLeaf<(build_vector), [{
255 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).Val != 0;
256 }], v8i16SExt8Imm_xform>;
258 // v8i16SExt10Imm_xform function: convert build_vector to 16-bit sign extended
259 // immediate constant load for v8i16 vectors.
260 def v8i16SExt10Imm_xform: SDNodeXForm<build_vector, [{
261 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
264 // v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate constant
265 // load, works in conjunction with its transform function.
266 def v8i16SExt10Imm: PatLeaf<(build_vector), [{
267 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
268 }], v8i16SExt10Imm_xform>;
270 // v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended
271 // immediate constant load for v8i16 vectors.
272 def v8i16SExt16Imm_xform: SDNodeXForm<build_vector, [{
273 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16);
276 // v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate constant
277 // load, works in conjunction with its transform function.
278 def v8i16SExt16Imm: PatLeaf<(build_vector), [{
279 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).Val != 0;
280 }], v8i16SExt16Imm_xform>;
282 // v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended
283 // immediate constant load for v4i32 vectors.
284 def v4i32SExt10Imm_xform: SDNodeXForm<build_vector, [{
285 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
288 // v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate constant
289 // load, works in conjunction with its transform function.
290 def v4i32SExt10Imm: PatLeaf<(build_vector), [{
291 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
292 }], v4i32SExt10Imm_xform>;
294 // v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended
295 // immediate constant load for v4i32 vectors.
296 def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{
297 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32);
300 // v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate constant
301 // load, works in conjunction with its transform function.
302 def v4i32SExt16Imm: PatLeaf<(build_vector), [{
303 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).Val != 0;
304 }], v4i32SExt16Imm_xform>;
306 // v4i32Uns18Imm_xform function: convert build_vector to 18-bit unsigned
307 // immediate constant load for v4i32 vectors.
308 def v4i32Uns18Imm_xform: SDNodeXForm<build_vector, [{
309 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32);
312 // v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
313 // works in conjunction with its transform function.
314 def v4i32Uns18Imm: PatLeaf<(build_vector), [{
315 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).Val != 0;
316 }], v4i32Uns18Imm_xform>;
318 // ILHUvec_get_imm xform function: convert build_vector to ILHUvec imm constant
320 def ILHUvec_get_imm: SDNodeXForm<build_vector, [{
321 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32);
324 /// immILHUvec: Predicate test for a ILHU constant vector.
325 def immILHUvec: PatLeaf<(build_vector), [{
326 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).Val != 0;
327 }], ILHUvec_get_imm>;
329 // Catch-all for any other i32 vector constants
330 def v4i32_get_imm: SDNodeXForm<build_vector, [{
331 return SPU::get_v4i32_imm(N, *CurDAG);
334 def v4i32Imm: PatLeaf<(build_vector), [{
335 return SPU::get_v4i32_imm(N, *CurDAG).Val != 0;
338 // v2i64SExt10Imm_xform function: convert build_vector to 10-bit sign extended
339 // immediate constant load for v2i64 vectors.
340 def v2i64SExt10Imm_xform: SDNodeXForm<build_vector, [{
341 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64);
344 // v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate constant
345 // load, works in conjunction with its transform function.
346 def v2i64SExt10Imm: PatLeaf<(build_vector), [{
347 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).Val != 0;
348 }], v2i64SExt10Imm_xform>;
350 // v2i64SExt16Imm_xform function: convert build_vector to 16-bit sign extended
351 // immediate constant load for v2i64 vectors.
352 def v2i64SExt16Imm_xform: SDNodeXForm<build_vector, [{
353 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64);
356 // v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate constant
357 // load, works in conjunction with its transform function.
358 def v2i64SExt16Imm: PatLeaf<(build_vector), [{
359 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).Val != 0;
360 }], v2i64SExt16Imm_xform>;
362 // v2i64Uns18Imm_xform function: convert build_vector to 18-bit unsigned
363 // immediate constant load for v2i64 vectors.
364 def v2i64Uns18Imm_xform: SDNodeXForm<build_vector, [{
365 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64);
368 // v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
369 // works in conjunction with its transform function.
370 def v2i64Uns18Imm: PatLeaf<(build_vector), [{
371 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).Val != 0;
372 }], v2i64Uns18Imm_xform>;
374 /// immILHUvec: Predicate test for a ILHU constant vector.
375 def immILHUvec_i64: PatLeaf<(build_vector), [{
376 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).Val != 0;
377 }], ILHUvec_get_imm>;
379 // Catch-all for any other i32 vector constants
380 def v2i64_get_imm: SDNodeXForm<build_vector, [{
381 return SPU::get_v2i64_imm(N, *CurDAG);
384 def v2i64Imm: PatLeaf<(build_vector), [{
385 return SPU::get_v2i64_imm(N, *CurDAG).Val != 0;
388 //===----------------------------------------------------------------------===//
389 // Operand Definitions.
391 def s7imm: Operand<i16> {
392 let PrintMethod = "printS7ImmOperand";
395 def u7imm: Operand<i16> {
396 let PrintMethod = "printU7ImmOperand";
399 def u7imm_i32: Operand<i32> {
400 let PrintMethod = "printU7ImmOperand";
403 // Halfword, signed 10-bit constant
404 def s10imm : Operand<i16> {
405 let PrintMethod = "printS10ImmOperand";
408 def s10imm_i32: Operand<i32> {
409 let PrintMethod = "printS10ImmOperand";
412 def s10imm_i64: Operand<i64> {
413 let PrintMethod = "printS10ImmOperand";
416 // Unsigned 10-bit integers:
417 def u10imm: Operand<i16> {
418 let PrintMethod = "printU10ImmOperand";
421 def u10imm_i32: Operand<i32> {
422 let PrintMethod = "printU10ImmOperand";
425 def s16imm : Operand<i16> {
426 let PrintMethod = "printS16ImmOperand";
429 def s16imm_i32: Operand<i32> {
430 let PrintMethod = "printS16ImmOperand";
433 def s16imm_i64: Operand<i64> {
434 let PrintMethod = "printS16ImmOperand";
437 def s16imm_f32: Operand<f32> {
438 let PrintMethod = "printS16ImmOperand";
441 def s16imm_f64: Operand<f64> {
442 let PrintMethod = "printS16ImmOperand";
445 def u16imm : Operand<i32> {
446 let PrintMethod = "printU16ImmOperand";
449 def f16imm : Operand<f32> {
450 let PrintMethod = "printU16ImmOperand";
453 def s18imm : Operand<i32> {
454 let PrintMethod = "printS18ImmOperand";
457 def u18imm : Operand<i32> {
458 let PrintMethod = "printU18ImmOperand";
461 def u18imm_i64 : Operand<i64> {
462 let PrintMethod = "printU18ImmOperand";
465 def f18imm : Operand<f32> {
466 let PrintMethod = "printU18ImmOperand";
469 def f18imm_f64 : Operand<f64> {
470 let PrintMethod = "printU18ImmOperand";
473 // Negated 7-bit halfword rotate immediate operands
474 def rothNeg7imm : Operand<i32> {
475 let PrintMethod = "printROTHNeg7Imm";
478 def rothNeg7imm_i16 : Operand<i16> {
479 let PrintMethod = "printROTHNeg7Imm";
482 // Negated 7-bit word rotate immediate operands
483 def rotNeg7imm : Operand<i32> {
484 let PrintMethod = "printROTNeg7Imm";
487 def rotNeg7imm_i16 : Operand<i16> {
488 let PrintMethod = "printROTNeg7Imm";
491 // Floating point immediate operands
492 def f32imm : Operand<f32>;
494 def target : Operand<OtherVT> {
495 let PrintMethod = "printBranchOperand";
498 // Absolute address call target
499 def calltarget : Operand<iPTR> {
500 let PrintMethod = "printCallOperand";
501 let MIOperandInfo = (ops u18imm:$calldest);
504 // Relative call target
505 def relcalltarget : Operand<iPTR> {
506 let PrintMethod = "printPCRelativeOperand";
507 let MIOperandInfo = (ops s16imm:$calldest);
511 def brtarget : Operand<OtherVT> {
512 let PrintMethod = "printPCRelativeOperand";
515 // Indirect call target
516 def indcalltarget : Operand<iPTR> {
517 let PrintMethod = "printCallOperand";
518 let MIOperandInfo = (ops ptr_rc:$calldest);
521 def symbolHi: Operand<i32> {
522 let PrintMethod = "printSymbolHi";
525 def symbolLo: Operand<i32> {
526 let PrintMethod = "printSymbolLo";
529 def symbolLSA: Operand<i32> {
530 let PrintMethod = "printSymbolLSA";
533 // memory s7imm(reg) operaand
534 def memri7 : Operand<iPTR> {
535 let PrintMethod = "printMemRegImmS7";
536 let MIOperandInfo = (ops s7imm:$imm, ptr_rc:$reg);
539 // memory s10imm(reg) operand
540 def memri10 : Operand<iPTR> {
541 let PrintMethod = "printMemRegImmS10";
542 let MIOperandInfo = (ops s10imm:$imm, ptr_rc:$reg);
545 // 256K local store address
546 // N.B.: The tblgen code generator expects to have two operands, an offset
547 // and a pointer. Of these, only the immediate is actually used.
548 def addr256k : Operand<iPTR> {
549 let PrintMethod = "printAddr256K";
550 let MIOperandInfo = (ops s16imm:$imm, ptr_rc:$reg);
553 // memory s18imm(reg) operand
554 def memri18 : Operand<iPTR> {
555 let PrintMethod = "printMemRegImmS18";
556 let MIOperandInfo = (ops s18imm:$imm, ptr_rc:$reg);
559 // memory register + register operand
560 def memrr : Operand<iPTR> {
561 let PrintMethod = "printMemRegReg";
562 let MIOperandInfo = (ops ptr_rc:$reg_a, ptr_rc:$reg_b);
565 // Define SPU-specific addressing modes: These come in three basic
568 // D-form : [r+I10] (10-bit signed offset + reg)
569 // X-form : [r+r] (reg+reg)
570 // A-form : abs (256K LSA offset)
571 // D-form(2): [r+I7] (7-bit signed offset + reg)
573 def dform_addr : ComplexPattern<iPTR, 2, "SelectDFormAddr", [], []>;
574 def xform_addr : ComplexPattern<iPTR, 2, "SelectXFormAddr", [], []>;
575 def aform_addr : ComplexPattern<iPTR, 2, "SelectAFormAddr", [], []>;
576 def dform2_addr : ComplexPattern<iPTR, 2, "SelectDForm2Addr", [], []>;