lib/Target/CellSPU/SPUInstrInfo.h

   1 //===- SPUInstrInfo.h - Cell SPU Instruction Information --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the CellSPU implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef SPU_INSTRUCTIONINFO_H
  15 #define SPU_INSTRUCTIONINFO_H
  16
  17 #include "SPU.h"
  18 #include "llvm/Target/TargetInstrInfo.h"
  19 #include "SPURegisterInfo.h"
  20
  21 namespace llvm {
  22   //! Cell SPU instruction information class
  23   class SPUInstrInfo : public TargetInstrInfoImpl {
  24     SPUTargetMachine &TM;
  25     const SPURegisterInfo RI;
  26   public:
  27     explicit SPUInstrInfo(SPUTargetMachine &tm);
  28
  29     /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  30     /// such, whenever a client has an instance of instruction info, it should
  31     /// always be able to get register info as well (through this method).
  32     ///
  33     virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }
  34
  35     ScheduleHazardRecognizer *
  36     CreateTargetHazardRecognizer(const TargetMachine *TM,
  37                                  const ScheduleDAG *DAG) const;
  38
  39     unsigned isLoadFromStackSlot(const MachineInstr *MI,
  40                                  int &FrameIndex) const;
  41     unsigned isStoreToStackSlot(const MachineInstr *MI,
  42                                 int &FrameIndex) const;
  43
  44     virtual void copyPhysReg(MachineBasicBlock &MBB,
  45                              MachineBasicBlock::iterator I, DebugLoc DL,
  46                              unsigned DestReg, unsigned SrcReg,
  47                              bool KillSrc) const;
  48
  49     //! Store a register to a stack slot, based on its register class.
  50     virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  51                                      MachineBasicBlock::iterator MBBI,
  52                                      unsigned SrcReg, bool isKill, int FrameIndex,
  53                                      const TargetRegisterClass *RC,
  54                                      const TargetRegisterInfo *TRI) const;
  55
  56     //! Load a register from a stack slot, based on its register class.
  57     virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  58                                       MachineBasicBlock::iterator MBBI,
  59                                       unsigned DestReg, int FrameIndex,
  60                                       const TargetRegisterClass *RC,
  61                                       const TargetRegisterInfo *TRI) const;
  62
  63     //! Reverses a branch's condition, returning false on success.
  64     virtual
  65     bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
  66
  67     virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  68                                MachineBasicBlock *&FBB,
  69                                SmallVectorImpl<MachineOperand> &Cond,
  70                                bool AllowModify) const;
  71
  72     virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
  73
  74     virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  75                                   MachineBasicBlock *FBB,
  76                                   const SmallVectorImpl<MachineOperand> &Cond,
  77                                   DebugLoc DL) const;
  78    };
  79 }
  80
  81 #endif