1 //===- SPUInstrInfo.h - Cell SPU Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the CellSPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef SPU_INSTRUCTIONINFO_H
15 #define SPU_INSTRUCTIONINFO_H
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "SPURegisterInfo.h"
22 //! Cell SPU instruction information class
23 class SPUInstrInfo : public TargetInstrInfoImpl {
25 const SPURegisterInfo RI;
27 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
29 const SmallVectorImpl<unsigned> &Ops,
30 int FrameIndex) const;
32 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
34 const SmallVectorImpl<unsigned> &Ops,
35 MachineInstr* LoadMI) const {
40 explicit SPUInstrInfo(SPUTargetMachine &tm);
42 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
43 /// such, whenever a client has an instance of instruction info, it should
44 /// always be able to get register info as well (through this method).
46 virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }
48 /// getPointerRegClass - Return the register class to use to hold pointers.
49 /// This is used for addressing modes.
50 virtual const TargetRegisterClass *getPointerRegClass() const;
52 // Return true if the instruction is a register to register move and
53 // leave the source and dest operands in the passed parameters.
55 virtual bool isMoveInstr(const MachineInstr& MI,
57 unsigned& destReg) const;
59 unsigned isLoadFromStackSlot(const MachineInstr *MI,
60 int &FrameIndex) const;
61 unsigned isStoreToStackSlot(const MachineInstr *MI,
62 int &FrameIndex) const;
64 virtual bool copyRegToReg(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator MI,
66 unsigned DestReg, unsigned SrcReg,
67 const TargetRegisterClass *DestRC,
68 const TargetRegisterClass *SrcRC) const;
70 //! Store a register to a stack slot, based on its register class.
71 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
72 MachineBasicBlock::iterator MBBI,
73 unsigned SrcReg, bool isKill, int FrameIndex,
74 const TargetRegisterClass *RC) const;
76 //! Store a register to an address, based on its register class
77 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
78 SmallVectorImpl<MachineOperand> &Addr,
79 const TargetRegisterClass *RC,
80 SmallVectorImpl<MachineInstr*> &NewMIs) const;
82 //! Load a register from a stack slot, based on its register class.
83 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MBBI,
85 unsigned DestReg, int FrameIndex,
86 const TargetRegisterClass *RC) const;
88 //! Loqad a register from an address, based on its register class
89 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
90 SmallVectorImpl<MachineOperand> &Addr,
91 const TargetRegisterClass *RC,
92 SmallVectorImpl<MachineInstr*> &NewMIs) const;
94 //! Return true if the specified load or store can be folded
96 bool canFoldMemoryOperand(const MachineInstr *MI,
97 const SmallVectorImpl<unsigned> &Ops) const;
99 //! Return true if the specified block does not fall through
100 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
102 //! Reverses a branch's condition, returning false on success.
104 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
106 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
107 MachineBasicBlock *&FBB,
108 SmallVectorImpl<MachineOperand> &Cond) const;
110 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
112 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
113 MachineBasicBlock *FBB,
114 const SmallVectorImpl<MachineOperand> &Cond) const;