1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUInstrInfo.h"
16 #include "SPUInstrBuilder.h"
17 #include "SPUTargetMachine.h"
18 #include "SPUGenInstrInfo.inc"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
25 : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
27 RI(*TM.getSubtargetImpl(), *this)
32 /// getPointerRegClass - Return the register class to use to hold pointers.
33 /// This is used for addressing modes.
34 const TargetRegisterClass *
35 SPUInstrInfo::getPointerRegClass() const
37 return &SPU::R32CRegClass;
41 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
43 unsigned& destReg) const {
44 // Primarily, ORI and OR are generated by copyRegToReg. But, there are other
45 // cases where we can safely say that what's being done is really a move
46 // (see how PowerPC does this -- it's the model for this code too.)
47 switch (MI.getOpcode()) {
62 assert(MI.getNumOperands() == 3 &&
63 MI.getOperand(0).isRegister() &&
64 MI.getOperand(1).isRegister() &&
65 MI.getOperand(2).isImmediate() &&
66 "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
67 if (MI.getOperand(2).getImm() == 0) {
68 sourceReg = MI.getOperand(1).getReg();
69 destReg = MI.getOperand(0).getReg();
74 assert(MI.getNumOperands() == 3 &&
75 "wrong number of operands to AIr32");
76 if (MI.getOperand(0).isRegister() &&
77 (MI.getOperand(1).isRegister() ||
78 MI.getOperand(1).isFrameIndex()) &&
79 (MI.getOperand(2).isImmediate() &&
80 MI.getOperand(2).getImm() == 0)) {
81 sourceReg = MI.getOperand(1).getReg();
82 destReg = MI.getOperand(0).getReg();
87 case SPU::ORv8i16_i16:
88 case SPU::ORv4i32_i32:
89 case SPU::ORv2i64_i64:
90 case SPU::ORv4f32_f32:
91 case SPU::ORv2f64_f64:
93 case SPU::ORi16_v8i16:
94 case SPU::ORi32_v4i32:
95 case SPU::ORi64_v2i64:
96 case SPU::ORf32_v4f32:
97 case SPU::ORf64_v2f64:
105 assert(MI.getNumOperands() == 3 &&
106 MI.getOperand(0).isRegister() &&
107 MI.getOperand(1).isRegister() &&
108 MI.getOperand(2).isRegister() &&
109 "invalid SPU OR(vec|r32|r64|gprc) instruction!");
110 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
111 sourceReg = MI.getOperand(1).getReg();
112 destReg = MI.getOperand(0).getReg();
122 SPUInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
123 switch (MI->getOpcode()) {
139 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
140 MI->getOperand(2).isFrameIndex()) {
141 FrameIndex = MI->getOperand(2).getIndex();
142 return MI->getOperand(0).getReg();
150 SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
151 switch (MI->getOpcode()) {
173 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
174 MI->getOperand(2).isFrameIndex()) {
175 FrameIndex = MI->getOperand(2).getIndex();
176 return MI->getOperand(0).getReg();
183 void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
184 MachineBasicBlock::iterator MI,
185 unsigned DestReg, unsigned SrcReg,
186 const TargetRegisterClass *DestRC,
187 const TargetRegisterClass *SrcRC) const
189 if (DestRC != SrcRC) {
190 cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
194 if (DestRC == SPU::R8CRegisterClass) {
195 BuildMI(MBB, MI, get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0);
196 } else if (DestRC == SPU::R16CRegisterClass) {
197 BuildMI(MBB, MI, get(SPU::ORHIr16), DestReg).addReg(SrcReg).addImm(0);
198 } else if (DestRC == SPU::R32CRegisterClass) {
199 BuildMI(MBB, MI, get(SPU::ORIr32), DestReg).addReg(SrcReg).addImm(0);
200 } else if (DestRC == SPU::R32FPRegisterClass) {
201 BuildMI(MBB, MI, get(SPU::ORf32), DestReg).addReg(SrcReg)
203 } else if (DestRC == SPU::R64CRegisterClass) {
204 BuildMI(MBB, MI, get(SPU::ORr64), DestReg).addReg(SrcReg)
206 } else if (DestRC == SPU::R64FPRegisterClass) {
207 BuildMI(MBB, MI, get(SPU::ORf64), DestReg).addReg(SrcReg)
209 } /* else if (DestRC == SPU::GPRCRegisterClass) {
210 BuildMI(MBB, MI, get(SPU::ORgprc), DestReg).addReg(SrcReg)
212 } */ else if (DestRC == SPU::VECREGRegisterClass) {
213 BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
216 std::cerr << "Attempt to copy unknown/unsupported register class!\n";
222 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
223 MachineBasicBlock::iterator MI,
224 unsigned SrcReg, bool isKill, int FrameIdx,
225 const TargetRegisterClass *RC) const
228 if (RC == SPU::GPRCRegisterClass) {
229 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
232 } else if (RC == SPU::R64CRegisterClass) {
233 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
236 } else if (RC == SPU::R64FPRegisterClass) {
237 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
240 } else if (RC == SPU::R32CRegisterClass) {
241 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
244 } else if (RC == SPU::R32FPRegisterClass) {
245 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
248 } else if (RC == SPU::R16CRegisterClass) {
249 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ?
253 assert(0 && "Unknown regclass!");
257 addFrameReference(BuildMI(MBB, MI, get(opc))
258 .addReg(SrcReg, false, false, isKill), FrameIdx);
261 void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
263 SmallVectorImpl<MachineOperand> &Addr,
264 const TargetRegisterClass *RC,
265 SmallVectorImpl<MachineInstr*> &NewMIs) const {
266 cerr << "storeRegToAddr() invoked!\n";
269 if (Addr[0].isFrameIndex()) {
270 /* do what storeRegToStackSlot does here */
273 if (RC == SPU::GPRCRegisterClass) {
274 /* Opc = PPC::STW; */
275 } else if (RC == SPU::R16CRegisterClass) {
276 /* Opc = PPC::STD; */
277 } else if (RC == SPU::R32CRegisterClass) {
278 /* Opc = PPC::STFD; */
279 } else if (RC == SPU::R32FPRegisterClass) {
280 /* Opc = PPC::STFD; */
281 } else if (RC == SPU::R64FPRegisterClass) {
282 /* Opc = PPC::STFS; */
283 } else if (RC == SPU::VECREGRegisterClass) {
284 /* Opc = PPC::STVX; */
286 assert(0 && "Unknown regclass!");
289 MachineInstrBuilder MIB = BuildMI(get(Opc))
290 .addReg(SrcReg, false, false, isKill);
291 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
292 MachineOperand &MO = Addr[i];
294 MIB.addReg(MO.getReg());
295 else if (MO.isImmediate())
296 MIB.addImm(MO.getImm());
298 MIB.addFrameIndex(MO.getIndex());
300 NewMIs.push_back(MIB);
305 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
306 MachineBasicBlock::iterator MI,
307 unsigned DestReg, int FrameIdx,
308 const TargetRegisterClass *RC) const
311 if (RC == SPU::GPRCRegisterClass) {
312 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
315 } else if (RC == SPU::R64CRegisterClass) {
316 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
319 } else if (RC == SPU::R64FPRegisterClass) {
320 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
323 } else if (RC == SPU::R32CRegisterClass) {
324 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
327 } else if (RC == SPU::R32FPRegisterClass) {
328 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
331 } else if (RC == SPU::R16CRegisterClass) {
332 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
336 assert(0 && "Unknown regclass in loadRegFromStackSlot!");
340 addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx);
344 \note We are really pessimistic here about what kind of a load we're doing.
346 void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
347 SmallVectorImpl<MachineOperand> &Addr,
348 const TargetRegisterClass *RC,
349 SmallVectorImpl<MachineInstr*> &NewMIs)
351 cerr << "loadRegToAddr() invoked!\n";
354 if (Addr[0].isFrameIndex()) {
355 /* do what loadRegFromStackSlot does here... */
358 if (RC == SPU::R8CRegisterClass) {
359 /* do brilliance here */
360 } else if (RC == SPU::R16CRegisterClass) {
361 /* Opc = PPC::LWZ; */
362 } else if (RC == SPU::R32CRegisterClass) {
364 } else if (RC == SPU::R32FPRegisterClass) {
365 /* Opc = PPC::LFD; */
366 } else if (RC == SPU::R64FPRegisterClass) {
367 /* Opc = PPC::LFS; */
368 } else if (RC == SPU::VECREGRegisterClass) {
369 /* Opc = PPC::LVX; */
370 } else if (RC == SPU::GPRCRegisterClass) {
371 /* Opc = something else! */
373 assert(0 && "Unknown regclass!");
376 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
377 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
378 MachineOperand &MO = Addr[i];
380 MIB.addReg(MO.getReg());
381 else if (MO.isImmediate())
382 MIB.addImm(MO.getImm());
384 MIB.addFrameIndex(MO.getIndex());
386 NewMIs.push_back(MIB);
390 /// foldMemoryOperand - SPU, like PPC, can only fold spills into
391 /// copy instructions, turning them into load/store instructions.
393 SPUInstrInfo::foldMemoryOperand(MachineFunction &MF,
395 SmallVectorImpl<unsigned> &Ops,
396 int FrameIndex) const
398 #if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN
399 if (Ops.size() != 1) return NULL;
401 unsigned OpNum = Ops[0];
402 unsigned Opc = MI->getOpcode();
403 MachineInstr *NewMI = 0;
405 if ((Opc == SPU::ORr32
406 || Opc == SPU::ORv4i32)
407 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
408 if (OpNum == 0) { // move -> store
409 unsigned InReg = MI->getOperand(1).getReg();
410 if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
411 NewMI = addFrameReference(BuildMI(TII.get(SPU::STQDr32)).addReg(InReg),
414 } else { // move -> load
415 unsigned OutReg = MI->getOperand(0).getReg();
416 Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) ? SPU::STQDr32 : SPU::STQXr32;
417 NewMI = addFrameReference(BuildMI(TII.get(Opc), OutReg), FrameIndex);
422 NewMI->copyKillDeadInfo(MI);