1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by a team from the Computer Systems Research
6 // Department at The Aerospace Corporation and is distributed under the
7 // University of Illinois Open Source License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
13 //===----------------------------------------------------------------------===//
15 #include "SPURegisterNames.h"
16 #include "SPUInstrInfo.h"
17 #include "SPUTargetMachine.h"
18 #include "SPUGenInstrInfo.inc"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
25 : TargetInstrInfo(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
27 RI(*TM.getSubtargetImpl(), *this)
32 /// getPointerRegClass - Return the register class to use to hold pointers.
33 /// This is used for addressing modes.
34 const TargetRegisterClass *
35 SPUInstrInfo::getPointerRegClass() const
37 return &SPU::R32CRegClass;
41 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
43 unsigned& destReg) const {
44 // Primarily, ORI and OR are generated by copyRegToReg. But, there are other
45 // cases where we can safely say that what's being done is really a move
46 // (see how PowerPC does this -- it's the model for this code too.)
47 switch (MI.getOpcode()) {
65 assert(MI.getNumOperands() == 3 &&
66 MI.getOperand(0).isRegister() &&
67 MI.getOperand(1).isRegister() &&
68 MI.getOperand(2).isImmediate() &&
69 "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
70 if (MI.getOperand(2).getImmedValue() == 0) {
71 sourceReg = MI.getOperand(1).getReg();
72 destReg = MI.getOperand(0).getReg();
77 assert(MI.getNumOperands() == 3 &&
78 "wrong number of operands to AIr32");
79 if (MI.getOperand(0).isRegister() &&
80 (MI.getOperand(1).isRegister() ||
81 MI.getOperand(1).isFrameIndex()) &&
82 (MI.getOperand(2).isImmediate() &&
83 MI.getOperand(2).getImmedValue() == 0)) {
84 sourceReg = MI.getOperand(1).getReg();
85 destReg = MI.getOperand(0).getReg();
92 // Special case because there's no third immediate operand to the
93 // instruction (the constant is embedded in the instruction)
94 assert(MI.getOperand(0).isRegister() &&
95 MI.getOperand(1).isRegister() &&
96 "ORIf32/f64: operands not registers");
97 sourceReg = MI.getOperand(1).getReg();
98 destReg = MI.getOperand(0).getReg();
101 // case SPU::ORv16i8_i8:
102 case SPU::ORv8i16_i16:
103 case SPU::ORv4i32_i32:
104 case SPU::ORv2i64_i64:
105 case SPU::ORv4f32_f32:
106 case SPU::ORv2f64_f64:
107 // case SPU::ORi8_v16i8:
108 case SPU::ORi16_v8i16:
109 case SPU::ORi32_v4i32:
110 case SPU::ORi64_v2i64:
111 case SPU::ORf32_v4f32:
112 case SPU::ORf64_v2f64:
119 assert(MI.getNumOperands() == 3 &&
120 MI.getOperand(0).isRegister() &&
121 MI.getOperand(1).isRegister() &&
122 MI.getOperand(2).isRegister() &&
123 "invalid SPU OR(vec|r32|r64|gprc) instruction!");
124 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
125 sourceReg = MI.getOperand(1).getReg();
126 destReg = MI.getOperand(0).getReg();
136 SPUInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
137 switch (MI->getOpcode()) {
153 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
154 MI->getOperand(2).isFrameIndex()) {
155 FrameIndex = MI->getOperand(2).getFrameIndex();
156 return MI->getOperand(0).getReg();
164 SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
165 switch (MI->getOpcode()) {
187 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
188 MI->getOperand(2).isFrameIndex()) {
189 FrameIndex = MI->getOperand(2).getFrameIndex();
190 return MI->getOperand(0).getReg();