1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUInstrInfo.h"
16 #include "SPUInstrBuilder.h"
17 #include "SPUTargetMachine.h"
18 #include "SPUGenInstrInfo.inc"
19 #include "SPUHazardRecognizers.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
28 //! Predicate for an unconditional branch instruction
29 inline bool isUncondBranch(const MachineInstr *I) {
30 unsigned opc = I->getOpcode();
32 return (opc == SPU::BR
37 //! Predicate for a conditional branch instruction
38 inline bool isCondBranch(const MachineInstr *I) {
39 unsigned opc = I->getOpcode();
41 return (opc == SPU::BRNZr32
42 || opc == SPU::BRNZv4i32
44 || opc == SPU::BRZv4i32
45 || opc == SPU::BRHNZr16
46 || opc == SPU::BRHNZv8i16
47 || opc == SPU::BRHZr16
48 || opc == SPU::BRHZv8i16);
52 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
53 : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
55 RI(*TM.getSubtargetImpl(), *this)
58 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
59 /// this target when scheduling the DAG.
60 ScheduleHazardRecognizer *SPUInstrInfo::CreateTargetHazardRecognizer(
61 const TargetMachine *TM,
62 const ScheduleDAG *DAG) const {
63 const TargetInstrInfo *TII = TM->getInstrInfo();
64 assert(TII && "No InstrInfo?");
65 return new SPUHazardRecognizer(*TII);
69 SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
70 int &FrameIndex) const {
71 switch (MI->getOpcode()) {
82 const MachineOperand MOp1 = MI->getOperand(1);
83 const MachineOperand MOp2 = MI->getOperand(2);
84 if (MOp1.isImm() && MOp2.isFI()) {
85 FrameIndex = MOp2.getIndex();
86 return MI->getOperand(0).getReg();
95 SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
96 int &FrameIndex) const {
97 switch (MI->getOpcode()) {
109 const MachineOperand MOp1 = MI->getOperand(1);
110 const MachineOperand MOp2 = MI->getOperand(2);
111 if (MOp1.isImm() && MOp2.isFI()) {
112 FrameIndex = MOp2.getIndex();
113 return MI->getOperand(0).getReg();
121 void SPUInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
122 MachineBasicBlock::iterator I, DebugLoc DL,
123 unsigned DestReg, unsigned SrcReg,
126 // We support cross register class moves for our aliases, such as R3 in any
127 // reg class to any other reg class containing R3. This is required because
128 // we instruction select bitconvert i64 -> f64 as a noop for example, so our
129 // types have no specific meaning.
131 BuildMI(MBB, I, DL, get(SPU::LRr128), DestReg)
132 .addReg(SrcReg, getKillRegState(KillSrc));
136 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
137 MachineBasicBlock::iterator MI,
138 unsigned SrcReg, bool isKill, int FrameIdx,
139 const TargetRegisterClass *RC,
140 const TargetRegisterInfo *TRI) const
143 bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
144 if (RC == SPU::GPRCRegisterClass) {
145 opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
146 } else if (RC == SPU::R64CRegisterClass) {
147 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
148 } else if (RC == SPU::R64FPRegisterClass) {
149 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
150 } else if (RC == SPU::R32CRegisterClass) {
151 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
152 } else if (RC == SPU::R32FPRegisterClass) {
153 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
154 } else if (RC == SPU::R16CRegisterClass) {
155 opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16);
156 } else if (RC == SPU::R8CRegisterClass) {
157 opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8);
158 } else if (RC == SPU::VECREGRegisterClass) {
159 opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
161 llvm_unreachable("Unknown regclass!");
165 if (MI != MBB.end()) DL = MI->getDebugLoc();
166 addFrameReference(BuildMI(MBB, MI, DL, get(opc))
167 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
171 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
172 MachineBasicBlock::iterator MI,
173 unsigned DestReg, int FrameIdx,
174 const TargetRegisterClass *RC,
175 const TargetRegisterInfo *TRI) const
178 bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
179 if (RC == SPU::GPRCRegisterClass) {
180 opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
181 } else if (RC == SPU::R64CRegisterClass) {
182 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
183 } else if (RC == SPU::R64FPRegisterClass) {
184 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
185 } else if (RC == SPU::R32CRegisterClass) {
186 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
187 } else if (RC == SPU::R32FPRegisterClass) {
188 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
189 } else if (RC == SPU::R16CRegisterClass) {
190 opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16);
191 } else if (RC == SPU::R8CRegisterClass) {
192 opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8);
193 } else if (RC == SPU::VECREGRegisterClass) {
194 opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
196 llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
200 if (MI != MBB.end()) DL = MI->getDebugLoc();
201 addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
206 \note This code was kiped from PPC. There may be more branch analysis for
207 CellSPU than what's currently done here.
210 SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
211 MachineBasicBlock *&FBB,
212 SmallVectorImpl<MachineOperand> &Cond,
213 bool AllowModify) const {
214 // If the block has no terminators, it just falls into the block after it.
215 MachineBasicBlock::iterator I = MBB.end();
216 if (I == MBB.begin())
219 while (I->isDebugValue()) {
220 if (I == MBB.begin())
224 if (!isUnpredicatedTerminator(I))
227 // Get the last instruction in the block.
228 MachineInstr *LastInst = I;
230 // If there is only one terminator instruction, process it.
231 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
232 if (isUncondBranch(LastInst)) {
233 // Check for jump tables
234 if (!LastInst->getOperand(0).isMBB())
236 TBB = LastInst->getOperand(0).getMBB();
238 } else if (isCondBranch(LastInst)) {
239 // Block ends with fall-through condbranch.
240 TBB = LastInst->getOperand(1).getMBB();
241 DEBUG(errs() << "Pushing LastInst: ");
242 DEBUG(LastInst->dump());
243 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
244 Cond.push_back(LastInst->getOperand(0));
247 // Otherwise, don't know what this is.
251 // Get the instruction before it if it's a terminator.
252 MachineInstr *SecondLastInst = I;
254 // If there are three terminators, we don't know what sort of block this is.
255 if (SecondLastInst && I != MBB.begin() &&
256 isUnpredicatedTerminator(--I))
259 // If the block ends with a conditional and unconditional branch, handle it.
260 if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
261 TBB = SecondLastInst->getOperand(1).getMBB();
262 DEBUG(errs() << "Pushing SecondLastInst: ");
263 DEBUG(SecondLastInst->dump());
264 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
265 Cond.push_back(SecondLastInst->getOperand(0));
266 FBB = LastInst->getOperand(0).getMBB();
270 // If the block ends with two unconditional branches, handle it. The second
271 // one is not executed, so remove it.
272 if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
273 TBB = SecondLastInst->getOperand(0).getMBB();
276 I->eraseFromParent();
280 // Otherwise, can't handle this.
285 SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
286 MachineBasicBlock::iterator I = MBB.end();
287 if (I == MBB.begin())
290 while (I->isDebugValue()) {
291 if (I == MBB.begin())
295 if (!isCondBranch(I) && !isUncondBranch(I))
298 // Remove the first branch.
299 DEBUG(errs() << "Removing branch: ");
301 I->eraseFromParent();
303 if (I == MBB.begin())
307 if (!(isCondBranch(I) || isUncondBranch(I)))
310 // Remove the second branch.
311 DEBUG(errs() << "Removing second branch: ");
313 I->eraseFromParent();
318 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
319 MachineBasicBlock *FBB,
320 const SmallVectorImpl<MachineOperand> &Cond,
322 // Shouldn't be a fall through.
323 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
324 assert((Cond.size() == 2 || Cond.size() == 0) &&
325 "SPU branch conditions have two components!");
330 // Unconditional branch
331 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(SPU::BR));
334 DEBUG(errs() << "Inserted one-way uncond branch: ");
335 DEBUG((*MIB).dump());
337 // Conditional branch
338 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
339 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
341 DEBUG(errs() << "Inserted one-way cond branch: ");
342 DEBUG((*MIB).dump());
346 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
347 MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR));
349 // Two-way Conditional Branch.
350 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
353 DEBUG(errs() << "Inserted conditional branch: ");
354 DEBUG((*MIB).dump());
355 DEBUG(errs() << "part 2: ");
356 DEBUG((*MIB2).dump());
361 //! Reverses a branch's condition, returning false on success.
363 SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
365 // Pretty brainless way of inverting the condition, but it works, considering
366 // there are only two conditions...
368 unsigned Opc; //! The incoming opcode
369 unsigned RevCondOpc; //! The reversed condition opcode
371 { SPU::BRNZr32, SPU::BRZr32 },
372 { SPU::BRNZv4i32, SPU::BRZv4i32 },
373 { SPU::BRZr32, SPU::BRNZr32 },
374 { SPU::BRZv4i32, SPU::BRNZv4i32 },
375 { SPU::BRHNZr16, SPU::BRHZr16 },
376 { SPU::BRHNZv8i16, SPU::BRHZv8i16 },
377 { SPU::BRHZr16, SPU::BRHNZr16 },
378 { SPU::BRHZv8i16, SPU::BRHNZv8i16 }
381 unsigned Opc = unsigned(Cond[0].getImm());
382 // Pretty dull mapping between the two conditions that SPU can generate:
383 for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
384 if (revconds[i].Opc == Opc) {
385 Cond[0].setImm(revconds[i].RevCondOpc);