1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUInstrInfo.h"
16 #include "SPUInstrBuilder.h"
17 #include "SPUTargetMachine.h"
18 #include "SPUGenInstrInfo.inc"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/raw_ostream.h"
27 //! Predicate for an unconditional branch instruction
28 inline bool isUncondBranch(const MachineInstr *I) {
29 unsigned opc = I->getOpcode();
31 return (opc == SPU::BR
36 //! Predicate for a conditional branch instruction
37 inline bool isCondBranch(const MachineInstr *I) {
38 unsigned opc = I->getOpcode();
40 return (opc == SPU::BRNZr32
41 || opc == SPU::BRNZv4i32
43 || opc == SPU::BRZv4i32
44 || opc == SPU::BRHNZr16
45 || opc == SPU::BRHNZv8i16
46 || opc == SPU::BRHZr16
47 || opc == SPU::BRHZv8i16);
51 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
52 : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
54 RI(*TM.getSubtargetImpl(), *this)
58 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
61 unsigned& SrcSR, unsigned& DstSR) const {
62 SrcSR = DstSR = 0; // No sub-registers.
64 switch (MI.getOpcode()) {
79 assert(MI.getNumOperands() == 3 &&
80 MI.getOperand(0).isReg() &&
81 MI.getOperand(1).isReg() &&
82 MI.getOperand(2).isImm() &&
83 "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
84 if (MI.getOperand(2).getImm() == 0) {
85 sourceReg = MI.getOperand(1).getReg();
86 destReg = MI.getOperand(0).getReg();
91 assert(MI.getNumOperands() == 3 &&
92 "wrong number of operands to AIr32");
93 if (MI.getOperand(0).isReg() &&
94 MI.getOperand(1).isReg() &&
95 (MI.getOperand(2).isImm() &&
96 MI.getOperand(2).getImm() == 0)) {
97 sourceReg = MI.getOperand(1).getReg();
98 destReg = MI.getOperand(0).getReg();
115 case SPU::ORv16i8_i8:
116 case SPU::ORv8i16_i16:
117 case SPU::ORv4i32_i32:
118 case SPU::ORv2i64_i64:
119 case SPU::ORv4f32_f32:
120 case SPU::ORv2f64_f64:
121 case SPU::ORi8_v16i8:
122 case SPU::ORi16_v8i16:
123 case SPU::ORi32_v4i32:
124 case SPU::ORi64_v2i64:
125 case SPU::ORf32_v4f32:
126 case SPU::ORf64_v2f64:
128 case SPU::ORi128_r64:
129 case SPU::ORi128_f64:
130 case SPU::ORi128_r32:
131 case SPU::ORi128_f32:
132 case SPU::ORi128_r16:
135 case SPU::ORi128_vec:
137 case SPU::ORr64_i128:
138 case SPU::ORf64_i128:
139 case SPU::ORr32_i128:
140 case SPU::ORf32_i128:
141 case SPU::ORr16_i128:
144 case SPU::ORvec_i128:
162 case SPU::ORr64_f64: {
163 assert(MI.getNumOperands() == 2 &&
164 MI.getOperand(0).isReg() &&
165 MI.getOperand(1).isReg() &&
166 "invalid SPU OR<type>_<vec> or LR instruction!");
167 sourceReg = MI.getOperand(1).getReg();
168 destReg = MI.getOperand(0).getReg();
183 assert(MI.getNumOperands() == 3 &&
184 MI.getOperand(0).isReg() &&
185 MI.getOperand(1).isReg() &&
186 MI.getOperand(2).isReg() &&
187 "invalid SPU OR(vec|r32|r64|gprc) instruction!");
188 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
189 sourceReg = MI.getOperand(1).getReg();
190 destReg = MI.getOperand(0).getReg();
200 SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
201 int &FrameIndex) const {
202 switch (MI->getOpcode()) {
213 const MachineOperand MOp1 = MI->getOperand(1);
214 const MachineOperand MOp2 = MI->getOperand(2);
215 if (MOp1.isImm() && MOp2.isFI()) {
216 FrameIndex = MOp2.getIndex();
217 return MI->getOperand(0).getReg();
226 SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
227 int &FrameIndex) const {
228 switch (MI->getOpcode()) {
240 const MachineOperand MOp1 = MI->getOperand(1);
241 const MachineOperand MOp2 = MI->getOperand(2);
242 if (MOp1.isImm() && MOp2.isFI()) {
243 FrameIndex = MOp2.getIndex();
244 return MI->getOperand(0).getReg();
252 bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
253 MachineBasicBlock::iterator MI,
254 unsigned DestReg, unsigned SrcReg,
255 const TargetRegisterClass *DestRC,
256 const TargetRegisterClass *SrcRC,
259 // We support cross register class moves for our aliases, such as R3 in any
260 // reg class to any other reg class containing R3. This is required because
261 // we instruction select bitconvert i64 -> f64 as a noop for example, so our
262 // types have no specific meaning.
264 if (DestRC == SPU::R8CRegisterClass) {
265 BuildMI(MBB, MI, DL, get(SPU::LRr8), DestReg).addReg(SrcReg);
266 } else if (DestRC == SPU::R16CRegisterClass) {
267 BuildMI(MBB, MI, DL, get(SPU::LRr16), DestReg).addReg(SrcReg);
268 } else if (DestRC == SPU::R32CRegisterClass) {
269 BuildMI(MBB, MI, DL, get(SPU::LRr32), DestReg).addReg(SrcReg);
270 } else if (DestRC == SPU::R32FPRegisterClass) {
271 BuildMI(MBB, MI, DL, get(SPU::LRf32), DestReg).addReg(SrcReg);
272 } else if (DestRC == SPU::R64CRegisterClass) {
273 BuildMI(MBB, MI, DL, get(SPU::LRr64), DestReg).addReg(SrcReg);
274 } else if (DestRC == SPU::R64FPRegisterClass) {
275 BuildMI(MBB, MI, DL, get(SPU::LRf64), DestReg).addReg(SrcReg);
276 } else if (DestRC == SPU::GPRCRegisterClass) {
277 BuildMI(MBB, MI, DL, get(SPU::LRr128), DestReg).addReg(SrcReg);
278 } else if (DestRC == SPU::VECREGRegisterClass) {
279 BuildMI(MBB, MI, DL, get(SPU::LRv16i8), DestReg).addReg(SrcReg);
281 // Attempt to copy unknown/unsupported register class!
289 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
290 MachineBasicBlock::iterator MI,
291 unsigned SrcReg, bool isKill, int FrameIdx,
292 const TargetRegisterClass *RC,
293 const TargetRegisterInfo *TRI) const
296 bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
297 if (RC == SPU::GPRCRegisterClass) {
298 opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
299 } else if (RC == SPU::R64CRegisterClass) {
300 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
301 } else if (RC == SPU::R64FPRegisterClass) {
302 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
303 } else if (RC == SPU::R32CRegisterClass) {
304 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
305 } else if (RC == SPU::R32FPRegisterClass) {
306 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
307 } else if (RC == SPU::R16CRegisterClass) {
308 opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16);
309 } else if (RC == SPU::R8CRegisterClass) {
310 opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8);
311 } else if (RC == SPU::VECREGRegisterClass) {
312 opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
314 llvm_unreachable("Unknown regclass!");
318 if (MI != MBB.end()) DL = MI->getDebugLoc();
319 addFrameReference(BuildMI(MBB, MI, DL, get(opc))
320 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
324 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
325 MachineBasicBlock::iterator MI,
326 unsigned DestReg, int FrameIdx,
327 const TargetRegisterClass *RC,
328 const TargetRegisterInfo *TRI) const
331 bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
332 if (RC == SPU::GPRCRegisterClass) {
333 opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
334 } else if (RC == SPU::R64CRegisterClass) {
335 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
336 } else if (RC == SPU::R64FPRegisterClass) {
337 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
338 } else if (RC == SPU::R32CRegisterClass) {
339 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
340 } else if (RC == SPU::R32FPRegisterClass) {
341 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
342 } else if (RC == SPU::R16CRegisterClass) {
343 opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16);
344 } else if (RC == SPU::R8CRegisterClass) {
345 opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8);
346 } else if (RC == SPU::VECREGRegisterClass) {
347 opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
349 llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
353 if (MI != MBB.end()) DL = MI->getDebugLoc();
354 addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
357 //! Return true if the specified load or store can be folded
359 SPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
360 const SmallVectorImpl<unsigned> &Ops) const {
361 if (Ops.size() != 1) return false;
363 // Make sure this is a reg-reg copy.
364 unsigned Opc = MI->getOpcode();
377 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
385 /// foldMemoryOperand - SPU, like PPC, can only fold spills into
386 /// copy instructions, turning them into load/store instructions.
388 SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
390 const SmallVectorImpl<unsigned> &Ops,
391 int FrameIndex) const
393 if (Ops.size() != 1) return 0;
395 unsigned OpNum = Ops[0];
396 unsigned Opc = MI->getOpcode();
397 MachineInstr *NewMI = 0;
410 if (OpNum == 0) { // move -> store
411 unsigned InReg = MI->getOperand(1).getReg();
412 bool isKill = MI->getOperand(1).isKill();
413 bool isUndef = MI->getOperand(1).isUndef();
414 if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
415 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(),
418 MIB.addReg(InReg, getKillRegState(isKill) | getUndefRegState(isUndef));
419 NewMI = addFrameReference(MIB, FrameIndex);
421 } else { // move -> load
422 unsigned OutReg = MI->getOperand(0).getReg();
423 bool isDead = MI->getOperand(0).isDead();
424 bool isUndef = MI->getOperand(0).isUndef();
425 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc));
427 MIB.addReg(OutReg, RegState::Define | getDeadRegState(isDead) |
428 getUndefRegState(isUndef));
429 Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
430 ? SPU::STQDr32 : SPU::STQXr32;
431 NewMI = addFrameReference(MIB, FrameIndex);
441 \note This code was kiped from PPC. There may be more branch analysis for
442 CellSPU than what's currently done here.
445 SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
446 MachineBasicBlock *&FBB,
447 SmallVectorImpl<MachineOperand> &Cond,
448 bool AllowModify) const {
449 // If the block has no terminators, it just falls into the block after it.
450 MachineBasicBlock::iterator I = MBB.end();
451 if (I == MBB.begin())
454 while (I->isDebugValue()) {
455 if (I == MBB.begin())
459 if (!isUnpredicatedTerminator(I))
462 // Get the last instruction in the block.
463 MachineInstr *LastInst = I;
465 // If there is only one terminator instruction, process it.
466 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
467 if (isUncondBranch(LastInst)) {
468 // Check for jump tables
469 if (!LastInst->getOperand(0).isMBB())
471 TBB = LastInst->getOperand(0).getMBB();
473 } else if (isCondBranch(LastInst)) {
474 // Block ends with fall-through condbranch.
475 TBB = LastInst->getOperand(1).getMBB();
476 DEBUG(errs() << "Pushing LastInst: ");
477 DEBUG(LastInst->dump());
478 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
479 Cond.push_back(LastInst->getOperand(0));
482 // Otherwise, don't know what this is.
486 // Get the instruction before it if it's a terminator.
487 MachineInstr *SecondLastInst = I;
489 // If there are three terminators, we don't know what sort of block this is.
490 if (SecondLastInst && I != MBB.begin() &&
491 isUnpredicatedTerminator(--I))
494 // If the block ends with a conditional and unconditional branch, handle it.
495 if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
496 TBB = SecondLastInst->getOperand(1).getMBB();
497 DEBUG(errs() << "Pushing SecondLastInst: ");
498 DEBUG(SecondLastInst->dump());
499 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
500 Cond.push_back(SecondLastInst->getOperand(0));
501 FBB = LastInst->getOperand(0).getMBB();
505 // If the block ends with two unconditional branches, handle it. The second
506 // one is not executed, so remove it.
507 if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
508 TBB = SecondLastInst->getOperand(0).getMBB();
511 I->eraseFromParent();
515 // Otherwise, can't handle this.
520 SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
521 MachineBasicBlock::iterator I = MBB.end();
522 if (I == MBB.begin())
525 while (I->isDebugValue()) {
526 if (I == MBB.begin())
530 if (!isCondBranch(I) && !isUncondBranch(I))
533 // Remove the first branch.
534 DEBUG(errs() << "Removing branch: ");
536 I->eraseFromParent();
538 if (I == MBB.begin())
542 if (!(isCondBranch(I) || isUncondBranch(I)))
545 // Remove the second branch.
546 DEBUG(errs() << "Removing second branch: ");
548 I->eraseFromParent();
553 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
554 MachineBasicBlock *FBB,
555 const SmallVectorImpl<MachineOperand> &Cond,
557 // Shouldn't be a fall through.
558 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
559 assert((Cond.size() == 2 || Cond.size() == 0) &&
560 "SPU branch conditions have two components!");
565 // Unconditional branch
566 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(SPU::BR));
569 DEBUG(errs() << "Inserted one-way uncond branch: ");
570 DEBUG((*MIB).dump());
572 // Conditional branch
573 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
574 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
576 DEBUG(errs() << "Inserted one-way cond branch: ");
577 DEBUG((*MIB).dump());
581 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
582 MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR));
584 // Two-way Conditional Branch.
585 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
588 DEBUG(errs() << "Inserted conditional branch: ");
589 DEBUG((*MIB).dump());
590 DEBUG(errs() << "part 2: ");
591 DEBUG((*MIB2).dump());
596 //! Reverses a branch's condition, returning false on success.
598 SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
600 // Pretty brainless way of inverting the condition, but it works, considering
601 // there are only two conditions...
603 unsigned Opc; //! The incoming opcode
604 unsigned RevCondOpc; //! The reversed condition opcode
606 { SPU::BRNZr32, SPU::BRZr32 },
607 { SPU::BRNZv4i32, SPU::BRZv4i32 },
608 { SPU::BRZr32, SPU::BRNZr32 },
609 { SPU::BRZv4i32, SPU::BRNZv4i32 },
610 { SPU::BRHNZr16, SPU::BRHZr16 },
611 { SPU::BRHNZv8i16, SPU::BRHZv8i16 },
612 { SPU::BRHZr16, SPU::BRHNZr16 },
613 { SPU::BRHZv8i16, SPU::BRHNZv8i16 }
616 unsigned Opc = unsigned(Cond[0].getImm());
617 // Pretty dull mapping between the two conditions that SPU can generate:
618 for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
619 if (revconds[i].Opc == Opc) {
620 Cond[0].setImm(revconds[i].RevCondOpc);