1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "SPURegisterNames.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Constants.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/Compiler.h"
38 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
40 isI64IntS10Immediate(ConstantSDNode *CN)
42 return isS10Constant(CN->getSExtValue());
45 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
47 isI32IntS10Immediate(ConstantSDNode *CN)
49 return isS10Constant(CN->getSExtValue());
53 //! SDNode predicate for sign-extended, 10-bit immediate values
55 isI32IntS10Immediate(SDNode *N)
57 return (N->getOpcode() == ISD::Constant
58 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
62 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
64 isI32IntU10Immediate(ConstantSDNode *CN)
66 return isU10Constant(CN->getSExtValue());
69 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
71 isI16IntS10Immediate(ConstantSDNode *CN)
73 return isS10Constant(CN->getSExtValue());
76 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
78 isI16IntS10Immediate(SDNode *N)
80 return (N->getOpcode() == ISD::Constant
81 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
84 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
86 isI16IntU10Immediate(ConstantSDNode *CN)
88 return isU10Constant((short) CN->getZExtValue());
91 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
93 isI16IntU10Immediate(SDNode *N)
95 return (N->getOpcode() == ISD::Constant
96 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
99 //! ConstantSDNode predicate for signed 16-bit values
101 \arg CN The constant SelectionDAG node holding the value
102 \arg Imm The returned 16-bit value, if returning true
104 This predicate tests the value in \a CN to see whether it can be
105 represented as a 16-bit, sign-extended quantity. Returns true if
109 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
111 MVT vt = CN->getValueType(0);
112 Imm = (short) CN->getZExtValue();
113 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
115 } else if (vt == MVT::i32) {
116 int32_t i_val = (int32_t) CN->getZExtValue();
117 short s_val = (short) i_val;
118 return i_val == s_val;
120 int64_t i_val = (int64_t) CN->getZExtValue();
121 short s_val = (short) i_val;
122 return i_val == s_val;
128 //! SDNode predicate for signed 16-bit values.
130 isIntS16Immediate(SDNode *N, short &Imm)
132 return (N->getOpcode() == ISD::Constant
133 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
136 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
138 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
140 MVT vt = FPN->getValueType(0);
141 if (vt == MVT::f32) {
142 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
143 int sval = (int) ((val << 16) >> 16);
152 isHighLow(const SDValue &Op)
154 return (Op.getOpcode() == SPUISD::IndirectAddr
155 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
156 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
157 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
158 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
161 //===------------------------------------------------------------------===//
162 //! MVT to "useful stuff" mapping structure:
164 struct valtype_map_s {
166 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
167 bool ldresult_imm; /// LDRESULT instruction requires immediate?
168 unsigned lrinst; /// LR instruction
171 const valtype_map_s valtype_map[] = {
172 { MVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
173 { MVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
174 { MVT::i32, SPU::ORIr32, true, SPU::LRr32 },
175 { MVT::i64, SPU::ORr64, false, SPU::LRr64 },
176 { MVT::f32, SPU::ORf32, false, SPU::LRf32 },
177 { MVT::f64, SPU::ORf64, false, SPU::LRf64 },
178 // vector types... (sigh!)
179 { MVT::v16i8, 0, false, SPU::LRv16i8 },
180 { MVT::v8i16, 0, false, SPU::LRv8i16 },
181 { MVT::v4i32, 0, false, SPU::LRv4i32 },
182 { MVT::v2i64, 0, false, SPU::LRv2i64 },
183 { MVT::v4f32, 0, false, SPU::LRv4f32 },
184 { MVT::v2f64, 0, false, SPU::LRv2f64 }
187 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
189 const valtype_map_s *getValueTypeMapEntry(MVT VT)
191 const valtype_map_s *retval = 0;
192 for (size_t i = 0; i < n_valtype_map; ++i) {
193 if (valtype_map[i].VT == VT) {
194 retval = valtype_map + i;
202 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
215 //===--------------------------------------------------------------------===//
216 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
217 /// instructions for SelectionDAG operations.
219 class SPUDAGToDAGISel :
220 public SelectionDAGISel
222 SPUTargetMachine &TM;
223 SPUTargetLowering &SPUtli;
224 unsigned GlobalBaseReg;
227 explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
228 SelectionDAGISel(*tm.getTargetLowering()),
230 SPUtli(*tm.getTargetLowering())
233 virtual bool runOnFunction(Function &Fn) {
234 // Make sure we re-emit a set of the global base reg if necessary
236 SelectionDAGISel::runOnFunction(Fn);
240 /// getI32Imm - Return a target constant with the specified value, of type
242 inline SDValue getI32Imm(uint32_t Imm) {
243 return CurDAG->getTargetConstant(Imm, MVT::i32);
246 /// getI64Imm - Return a target constant with the specified value, of type
248 inline SDValue getI64Imm(uint64_t Imm) {
249 return CurDAG->getTargetConstant(Imm, MVT::i64);
252 /// getSmallIPtrImm - Return a target constant of pointer type.
253 inline SDValue getSmallIPtrImm(unsigned Imm) {
254 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
257 /// Select - Convert the specified operand from a target-independent to a
258 /// target-specific node if it hasn't already been changed.
259 SDNode *Select(SDValue Op);
261 //! Returns true if the address N is an A-form (local store) address
262 bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
265 //! D-form address predicate
266 bool SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
269 /// Alternate D-form address using i7 offset predicate
270 bool SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
273 /// D-form address selection workhorse
274 bool DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Disp,
275 SDValue &Base, int minOffset, int maxOffset);
277 //! Address predicate if N can be expressed as an indexed [r+r] operation.
278 bool SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
281 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
282 /// inline asm expressions.
283 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
285 std::vector<SDValue> &OutOps) {
287 switch (ConstraintCode) {
288 default: return true;
290 if (!SelectDFormAddr(Op, Op, Op0, Op1)
291 && !SelectAFormAddr(Op, Op, Op0, Op1))
292 SelectXFormAddr(Op, Op, Op0, Op1);
294 case 'o': // offsetable
295 if (!SelectDFormAddr(Op, Op, Op0, Op1)
296 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
298 Op1 = getSmallIPtrImm(0);
301 case 'v': // not offsetable
303 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
305 SelectAddrIdxOnly(Op, Op, Op0, Op1);
310 OutOps.push_back(Op0);
311 OutOps.push_back(Op1);
315 /// InstructionSelect - This callback is invoked by
316 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
317 virtual void InstructionSelect();
319 virtual const char *getPassName() const {
320 return "Cell SPU DAG->DAG Pattern Instruction Selection";
323 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
324 /// this target when scheduling the DAG.
325 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
326 const TargetInstrInfo *II = TM.getInstrInfo();
327 assert(II && "No InstrInfo?");
328 return new SPUHazardRecognizer(*II);
331 // Include the pieces autogenerated from the target description.
332 #include "SPUGenDAGISel.inc"
337 /// InstructionSelect - This callback is invoked by
338 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
340 SPUDAGToDAGISel::InstructionSelect()
344 // Select target instructions for the DAG.
346 CurDAG->RemoveDeadNodes();
350 \arg Op The ISD instructio operand
351 \arg N The address to be tested
352 \arg Base The base address
353 \arg Index The base address index
356 SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
358 // These match the addr256k operand type:
359 MVT OffsVT = MVT::i16;
360 SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
362 switch (N.getOpcode()) {
364 case ISD::ConstantPool:
365 case ISD::GlobalAddress:
366 cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
370 case ISD::TargetConstant:
371 case ISD::TargetGlobalAddress:
372 case ISD::TargetJumpTable:
373 cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as "
374 << "A-form address.\n";
378 case SPUISD::AFormAddr:
379 // Just load from memory if there's only a single use of the location,
380 // otherwise, this will get handled below with D-form offset addresses
382 SDValue Op0 = N.getOperand(0);
383 switch (Op0.getOpcode()) {
384 case ISD::TargetConstantPool:
385 case ISD::TargetJumpTable:
390 case ISD::TargetGlobalAddress: {
391 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
392 GlobalValue *GV = GSDN->getGlobal();
393 if (GV->getAlignment() == 16) {
408 SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
410 const int minDForm2Offset = -(1 << 7);
411 const int maxDForm2Offset = (1 << 7) - 1;
412 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
417 \arg Op The ISD instruction (ignored)
418 \arg N The address to be tested
419 \arg Base Base address register/pointer
420 \arg Index Base address index
422 Examine the input address by a base register plus a signed 10-bit
423 displacement, [r+I10] (D-form address).
425 \return true if \a N is a D-form address with \a Base and \a Index set
426 to non-empty SDValue instances.
429 SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
431 return DFormAddressPredicate(Op, N, Base, Index,
432 SPUFrameInfo::minFrameOffset(),
433 SPUFrameInfo::maxFrameOffset());
437 SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
438 SDValue &Index, int minOffset,
440 unsigned Opc = N.getOpcode();
441 MVT PtrTy = SPUtli.getPointerTy();
443 if (Opc == ISD::FrameIndex) {
444 // Stack frame index must be less than 512 (divided by 16):
445 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
446 int FI = int(FIN->getIndex());
447 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
449 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
450 Base = CurDAG->getTargetConstant(0, PtrTy);
451 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
454 } else if (Opc == ISD::ADD) {
455 // Generated by getelementptr
456 const SDValue Op0 = N.getOperand(0);
457 const SDValue Op1 = N.getOperand(1);
459 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
460 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
461 Base = CurDAG->getTargetConstant(0, PtrTy);
464 } else if (Op1.getOpcode() == ISD::Constant
465 || Op1.getOpcode() == ISD::TargetConstant) {
466 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
467 int32_t offset = int32_t(CN->getSExtValue());
469 if (Op0.getOpcode() == ISD::FrameIndex) {
470 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
471 int FI = int(FIN->getIndex());
472 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
473 << " frame index = " << FI << "\n");
475 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
476 Base = CurDAG->getTargetConstant(offset, PtrTy);
477 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
480 } else if (offset > minOffset && offset < maxOffset) {
481 Base = CurDAG->getTargetConstant(offset, PtrTy);
485 } else if (Op0.getOpcode() == ISD::Constant
486 || Op0.getOpcode() == ISD::TargetConstant) {
487 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
488 int32_t offset = int32_t(CN->getSExtValue());
490 if (Op1.getOpcode() == ISD::FrameIndex) {
491 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
492 int FI = int(FIN->getIndex());
493 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
494 << " frame index = " << FI << "\n");
496 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
497 Base = CurDAG->getTargetConstant(offset, PtrTy);
498 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
501 } else if (offset > minOffset && offset < maxOffset) {
502 Base = CurDAG->getTargetConstant(offset, PtrTy);
507 } else if (Opc == SPUISD::IndirectAddr) {
508 // Indirect with constant offset -> D-Form address
509 const SDValue Op0 = N.getOperand(0);
510 const SDValue Op1 = N.getOperand(1);
512 if (Op0.getOpcode() == SPUISD::Hi
513 && Op1.getOpcode() == SPUISD::Lo) {
514 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
515 Base = CurDAG->getTargetConstant(0, PtrTy);
518 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
522 if (isa<ConstantSDNode>(Op1)) {
523 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
524 offset = int32_t(CN->getSExtValue());
526 } else if (isa<ConstantSDNode>(Op0)) {
527 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
528 offset = int32_t(CN->getSExtValue());
532 if (offset >= minOffset && offset <= maxOffset) {
533 Base = CurDAG->getTargetConstant(offset, PtrTy);
538 } else if (Opc == SPUISD::AFormAddr) {
539 Base = CurDAG->getTargetConstant(0, N.getValueType());
542 } else if (Opc == SPUISD::LDRESULT) {
543 Base = CurDAG->getTargetConstant(0, N.getValueType());
546 } else if (Opc == ISD::Register || Opc == ISD::CopyFromReg) {
547 unsigned OpOpc = Op.getOpcode();
549 if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
550 // Direct load/store without getelementptr
553 // Get the register from CopyFromReg
554 if (Opc == ISD::CopyFromReg)
555 Addr = N.getOperand(1);
557 Addr = N; // Register
559 Offs = ((OpOpc == ISD::STORE) ? Op.getOperand(3) : Op.getOperand(2));
561 if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
562 if (Offs.getOpcode() == ISD::UNDEF)
563 Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
570 /* If otherwise unadorned, default to D-form address with 0 offset: */
571 if (Opc == ISD::CopyFromReg) {
572 Index = N.getOperand(1);
577 Base = CurDAG->getTargetConstant(0, Index.getValueType());
586 \arg Op The ISD instruction operand
587 \arg N The address operand
588 \arg Base The base pointer operand
589 \arg Index The offset/index operand
591 If the address \a N can be expressed as an A-form or D-form address, returns
592 false. Otherwise, creates two operands, Base and Index that will become the
593 (r)(r) X-form address.
596 SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
598 if (!SelectAFormAddr(Op, N, Base, Index)
599 && !SelectDFormAddr(Op, N, Base, Index)) {
600 // If the address is neither A-form or D-form, punt and use an X-form
602 Base = N.getOperand(1);
603 Index = N.getOperand(0);
610 //! Convert the operand from a target-independent to a target-specific node
614 SPUDAGToDAGISel::Select(SDValue Op) {
615 SDNode *N = Op.getNode();
616 unsigned Opc = N->getOpcode();
619 MVT OpVT = Op.getValueType();
622 if (N->isMachineOpcode()) {
623 return NULL; // Already selected.
624 } else if (Opc == ISD::FrameIndex) {
625 // Selects to (add $sp, FI * stackSlotSize)
627 SPUFrameInfo::FItoStackOffset(cast<FrameIndexSDNode>(N)->getIndex());
628 MVT PtrVT = SPUtli.getPointerTy();
630 // Adjust stack slot to actual offset in frame:
631 if (isS10Constant(FI)) {
632 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AIr32 $sp, "
636 Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
637 Ops[1] = CurDAG->getTargetConstant(FI, PtrVT);
640 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with Ar32 $sp, "
644 Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
645 Ops[1] = CurDAG->getConstant(FI, PtrVT);
648 } else if (Opc == ISD::ZERO_EXTEND) {
649 // (zero_extend:i16 (and:i8 <arg>, <const>))
650 const SDValue &Op1 = N->getOperand(0);
652 if (Op.getValueType() == MVT::i16 && Op1.getValueType() == MVT::i8) {
653 if (Op1.getOpcode() == ISD::AND) {
654 // Fold this into a single ANDHI. This is often seen in expansions of i1
655 // to i8, then i8 to i16 in logical/branching operations.
656 DEBUG(cerr << "CellSPU: Coalescing (zero_extend:i16 (and:i8 "
657 "<arg>, <const>))\n");
658 NewOpc = SPU::ANDHIi8i16;
659 Ops[0] = Op1.getOperand(0);
660 Ops[1] = Op1.getOperand(1);
664 } else if (Opc == SPUISD::LDRESULT) {
665 // Custom select instructions for LDRESULT
666 MVT VT = N->getValueType(0);
667 SDValue Arg = N->getOperand(0);
668 SDValue Chain = N->getOperand(1);
670 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
672 if (vtm->ldresult_ins == 0) {
673 cerr << "LDRESULT for unsupported type: "
679 Opc = vtm->ldresult_ins;
680 if (vtm->ldresult_imm) {
681 SDValue Zero = CurDAG->getTargetConstant(0, VT);
683 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
685 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Arg, Chain);
689 } else if (Opc == SPUISD::IndirectAddr) {
690 // Look at the operands: SelectCode() will catch the cases that aren't
691 // specifically handled here.
693 // SPUInstrInfo catches the following patterns:
694 // (SPUindirect (SPUhi ...), (SPUlo ...))
695 // (SPUindirect $sp, imm)
696 MVT VT = Op.getValueType();
697 SDValue Op0 = N->getOperand(0);
698 SDValue Op1 = N->getOperand(1);
701 if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
702 || (Op0.getOpcode() == ISD::Register
703 && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
704 && RN->getReg() != SPU::R1))) {
706 if (Op1.getOpcode() == ISD::Constant) {
707 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
708 Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
709 NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
719 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
721 return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops);
723 return SelectCode(Op);
726 /// createPPCISelDag - This pass converts a legalized DAG into a
727 /// SPU-specific DAG, ready for instruction scheduling.
729 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
730 return new SPUDAGToDAGISel(TM);