1 //===- BlackfinRegisterInfo.td - Blackfin Register defs ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the Blackfin register file
12 //===----------------------------------------------------------------------===//
14 // Registers are identified with 3-bit group and 3-bit ID numbers.
16 class BlackfinReg<string n> : Register<n> {
22 // Rc - 1-bit registers
23 class Rc<bits<5> bitno, string n> : BlackfinReg<n> {
24 field bits<5> BitNum = bitno;
27 // Rs - 16-bit integer registers
28 class Rs<bits<3> group, bits<3> num, bits<1> hi, string n> : BlackfinReg<n> {
31 field bits<1> High = hi;
34 // Ri - 32-bit integer registers with subregs
35 class Ri<bits<3> group, bits<3> num, string n> : BlackfinReg<n> {
40 // Ra 40-bit accumulator registers
41 class Ra<bits<3> num, string n, list<Register> subs> : BlackfinReg<n> {
47 // Ywo halves of 32-bit register
48 multiclass Rss<bits<3> group, bits<3> num, string n> {
49 def H : Rs<group, num, 1, !strconcat(n, ".h")>;
50 def L : Rs<group, num, 0, !strconcat(n, ".l")>;
53 // Rii - 32-bit integer registers with subregs
54 class Rii<bits<3> group, bits<3> num, string n, list<Register> subs>
61 // Status bits are all part of ASTAT
64 def CC : Rc<5, "cc">, DwarfRegNum<[34]>;
65 def NCC : Rc<5, "!cc"> { let Aliases = [CC]; }
67 def AC0 : Rc<12, "ac0">;
68 def AC1 : Rc<13, "ac1">;
69 def AV0 : Rc<16, "av0">;
70 def AV0S : Rc<17, "av0s">;
71 def AV1 : Rc<18, "av1">;
72 def AV1S : Rc<19, "av1s">;
74 def VS : Rc<25, "vs">;
75 // Skipped non-status bits: AC0_COPY, V_COPY, RND_MOD
77 // Group 0: Integer registers
78 defm R0 : Rss<0, 0, "r0">;
79 def R0 : Rii<0, 0, "r0", [R0H, R0L]>, DwarfRegNum<[0]>;
80 defm R1 : Rss<0, 1, "r1">;
81 def R1 : Rii<0, 1, "r1", [R1H, R1L]>, DwarfRegNum<[1]>;
82 defm R2 : Rss<0, 2, "r2">;
83 def R2 : Rii<0, 2, "r2", [R2H, R2L]>, DwarfRegNum<[2]>;
84 defm R3 : Rss<0, 3, "r3">;
85 def R3 : Rii<0, 3, "r3", [R3H, R3L]>, DwarfRegNum<[3]>;
86 defm R4 : Rss<0, 4, "r4">;
87 def R4 : Rii<0, 4, "r4", [R4H, R4L]>, DwarfRegNum<[4]>;
88 defm R5 : Rss<0, 5, "r5">;
89 def R5 : Rii<0, 5, "r5", [R5H, R5L]>, DwarfRegNum<[5]>;
90 defm R6 : Rss<0, 6, "r6">;
91 def R6 : Rii<0, 6, "r6", [R6H, R6L]>, DwarfRegNum<[6]>;
92 defm R7 : Rss<0, 7, "r7">;
93 def R7 : Rii<0, 7, "r7", [R7H, R7L]>, DwarfRegNum<[7]>;
95 // Group 1: Pointer registers
96 defm P0 : Rss<1, 0, "p0">;
97 def P0 : Rii<1, 0, "p0", [P0H, P0L]>, DwarfRegNum<[8]>;
98 defm P1 : Rss<1, 1, "p1">;
99 def P1 : Rii<1, 1, "p1", [P1H, P1L]>, DwarfRegNum<[9]>;
100 defm P2 : Rss<1, 2, "p2">;
101 def P2 : Rii<1, 2, "p2", [P2H, P2L]>, DwarfRegNum<[10]>;
102 defm P3 : Rss<1, 3, "p3">;
103 def P3 : Rii<1, 3, "p3", [P3H, P3L]>, DwarfRegNum<[11]>;
104 defm P4 : Rss<1, 4, "p4">;
105 def P4 : Rii<1, 4, "p4", [P4H, P4L]>, DwarfRegNum<[12]>;
106 defm P5 : Rss<1, 5, "p5">;
107 def P5 : Rii<1, 5, "p5", [P5H, P5L]>, DwarfRegNum<[13]>;
108 defm SP : Rss<1, 6, "sp">;
109 def SP : Rii<1, 6, "sp", [SPH, SPL]>, DwarfRegNum<[14]>;
110 defm FP : Rss<1, 7, "fp">;
111 def FP : Rii<1, 7, "fp", [FPH, FPL]>, DwarfRegNum<[15]>;
113 // Group 2: Index registers
114 defm I0 : Rss<2, 0, "i0">;
115 def I0 : Rii<2, 0, "i0", [I0H, I0L]>, DwarfRegNum<[16]>;
116 defm I1 : Rss<2, 1, "i1">;
117 def I1 : Rii<2, 1, "i1", [I1H, I1L]>, DwarfRegNum<[17]>;
118 defm I2 : Rss<2, 2, "i2">;
119 def I2 : Rii<2, 2, "i2", [I2H, I2L]>, DwarfRegNum<[18]>;
120 defm I3 : Rss<2, 3, "i3">;
121 def I3 : Rii<2, 3, "i3", [I3H, I3L]>, DwarfRegNum<[19]>;
122 defm M0 : Rss<2, 4, "m0">;
123 def M0 : Rii<2, 4, "m0", [M0H, M0L]>, DwarfRegNum<[20]>;
124 defm M1 : Rss<2, 5, "m1">;
125 def M1 : Rii<2, 5, "m1", [M1H, M1L]>, DwarfRegNum<[21]>;
126 defm M2 : Rss<2, 6, "m2">;
127 def M2 : Rii<2, 6, "m2", [M2H, M2L]>, DwarfRegNum<[22]>;
128 defm M3 : Rss<2, 7, "m3">;
129 def M3 : Rii<2, 7, "m3", [M3H, M3L]>, DwarfRegNum<[23]>;
131 // Group 3: Cyclic indexing registers
132 defm B0 : Rss<3, 0, "b0">;
133 def B0 : Rii<3, 0, "b0", [B0H, B0L]>, DwarfRegNum<[24]>;
134 defm B1 : Rss<3, 1, "b1">;
135 def B1 : Rii<3, 1, "b1", [B1H, B1L]>, DwarfRegNum<[25]>;
136 defm B2 : Rss<3, 2, "b2">;
137 def B2 : Rii<3, 2, "b2", [B2H, B2L]>, DwarfRegNum<[26]>;
138 defm B3 : Rss<3, 3, "b3">;
139 def B3 : Rii<3, 3, "b3", [B3H, B3L]>, DwarfRegNum<[27]>;
140 defm L0 : Rss<3, 4, "l0">;
141 def L0 : Rii<3, 4, "l0", [L0H, L0L]>, DwarfRegNum<[28]>;
142 defm L1 : Rss<3, 5, "l1">;
143 def L1 : Rii<3, 5, "l1", [L1H, L1L]>, DwarfRegNum<[29]>;
144 defm L2 : Rss<3, 6, "l2">;
145 def L2 : Rii<3, 6, "l2", [L2H, L2L]>, DwarfRegNum<[30]>;
146 defm L3 : Rss<3, 7, "l3">;
147 def L3 : Rii<3, 7, "l3", [L3H, L3L]>, DwarfRegNum<[31]>;
150 def A0X : Ri <4, 0, "a0.x">;
151 defm A0 : Rss<4, 1, "a0">;
152 def A0W : Rii<4, 1, "a0.w", [A0H, A0L]>, DwarfRegNum<[32]>;
153 def A0 : Ra <0, "a0", [A0X, A0W]>;
155 def A1X : Ri <4, 2, "a1.x">;
156 defm A1 : Rss<4, 3, "a1">;
157 def A1W : Rii<4, 3, "a1.w", [A1H, A1L]>, DwarfRegNum<[33]>;
158 def A1 : Ra <2, "a1", [A1X, A1W]>;
160 def RETS : Ri<4, 7, "rets">, DwarfRegNum<[35]>;
161 def RETI : Ri<7, 3, "reti">, DwarfRegNum<[36]>;
162 def RETX : Ri<7, 4, "retx">, DwarfRegNum<[37]>;
163 def RETN : Ri<7, 5, "retn">, DwarfRegNum<[38]>;
164 def RETE : Ri<7, 6, "rete">, DwarfRegNum<[39]>;
166 def ASTAT : Ri<4, 6, "astat">, DwarfRegNum<[40]> {
167 let SubRegs = [AZ, AN, CC, NCC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS];
170 def SEQSTAT : Ri<7, 1, "seqstat">, DwarfRegNum<[41]>;
171 def USP : Ri<7, 0, "usp">, DwarfRegNum<[42]>;
172 def EMUDAT : Ri<7, 7, "emudat">, DwarfRegNum<[43]>;
173 def SYSCFG : Ri<7, 2, "syscfg">;
174 def CYCLES : Ri<6, 6, "cycles">;
175 def CYCLES2 : Ri<6, 7, "cycles2">;
178 def LT0 : Ri<6, 1, "lt0">, DwarfRegNum<[44]>;
179 def LT1 : Ri<6, 4, "lt1">, DwarfRegNum<[45]>;
180 def LC0 : Ri<6, 0, "lc0">, DwarfRegNum<[46]>;
181 def LC1 : Ri<6, 3, "lc1">, DwarfRegNum<[47]>;
182 def LB0 : Ri<6, 2, "lb0">, DwarfRegNum<[48]>;
183 def LB1 : Ri<6, 5, "lb1">, DwarfRegNum<[49]>;
188 // 3: .W (32 low bits of 40-bit accu)
189 // Keep in sync with enum in BlackfinRegisterInfo.h
190 def bfin_subreg_lo16 : PatLeaf<(i32 1)>;
191 def bfin_subreg_hi16 : PatLeaf<(i32 2)>;
192 def bfin_subreg_32bit : PatLeaf<(i32 3)>;
195 [R0, R1, R2, R3, R4, R5, R6, R7,
196 P0, P1, P2, P3, P4, P5, SP, FP,
197 I0, I1, I2, I3, M0, M1, M2, M3,
198 B0, B1, B2, B3, L0, L1, L2, L3],
199 [R0L, R1L, R2L, R3L, R4L, R5L, R6L, R7L,
200 P0L, P1L, P2L, P3L, P4L, P5L, SPL, FPL,
201 I0L, I1L, I2L, I3L, M0L, M1L, M2L, M3L,
202 B0L, B1L, B2L, B3L, L0L, L1L, L2L, L3L]>;
205 [R0, R1, R2, R3, R4, R5, R6, R7,
206 P0, P1, P2, P3, P4, P5, SP, FP,
207 I0, I1, I2, I3, M0, M1, M2, M3,
208 B0, B1, B2, B3, L0, L1, L2, L3],
209 [R0H, R1H, R2H, R3H, R4H, R5H, R6H, R7H,
210 P0H, P1H, P2H, P3H, P4H, P5H, SPH, FPH,
211 I0H, I1H, I2H, I3H, M0H, M1H, M2H, M3H,
212 B0H, B1H, B2H, B3H, L0H, L1H, L2H, L3H]>;
214 def : SubRegSet<1, [A0, A0W, A1, A1W], [A0L, A0L, A1L, A1L]>;
215 def : SubRegSet<2, [A0, A0W, A1, A1W], [A0H, A0H, A1H, A1H]>;
218 def D16 : RegisterClass<"BF", [i16], 16,
219 [R0H, R0L, R1H, R1L, R2H, R2L, R3H, R3L,
220 R4H, R4L, R5H, R5L, R6H, R6L, R7H, R7L]>;
222 def D16L : RegisterClass<"BF", [i16], 16,
223 [R0L, R1L, R2L, R3L, R4L, R5L, R6L, R7L]>;
225 def D16H : RegisterClass<"BF", [i16], 16,
226 [R0H, R1H, R2H, R3H, R4H, R5H, R6H, R7H]>;
228 def P16 : RegisterClass<"BF", [i16], 16,
229 [P0H, P0L, P1H, P1L, P2H, P2L, P3H, P3L,
230 P4H, P4L, P5H, P5L, SPH, SPL, FPH, FPL]>;
232 def P16L : RegisterClass<"BF", [i16], 16,
233 [P0L, P1L, P2L, P3L, P4L, P5L, SPL, FPL]>;
235 def P16H : RegisterClass<"BF", [i16], 16,
236 [P0H, P1H, P2H, P3H, P4H, P5H, SPH, FPH]>;
238 def DP16 : RegisterClass<"BF", [i16], 16,
239 [R0H, R0L, R1H, R1L, R2H, R2L, R3H, R3L,
240 R4H, R4L, R5H, R5L, R6H, R6L, R7H, R7L,
241 P0H, P0L, P1H, P1L, P2H, P2L, P3H, P3L,
242 P4H, P4L, P5H, P5L, SPH, SPL, FPH, FPL]>;
244 def DP16L : RegisterClass<"BF", [i16], 16,
245 [R0L, R1L, R2L, R3L, R4L, R5L, R6L, R7L,
246 P0L, P1L, P2L, P3L, P4L, P5L, SPL, FPL]>;
248 def DP16H : RegisterClass<"BF", [i16], 16,
249 [R0H, R1H, R2H, R3H, R4H, R5H, R6H, R7H,
250 P0H, P1H, P2H, P3H, P4H, P5H, SPH, FPH]>;
252 def GR16 : RegisterClass<"BF", [i16], 16,
253 [R0H, R0L, R1H, R1L, R2H, R2L, R3H, R3L,
254 R4H, R4L, R5H, R5L, R6H, R6L, R7H, R7L,
255 P0H, P0L, P1H, P1L, P2H, P2L, P3H, P3L,
256 P4H, P4L, P5H, P5L, SPH, SPL, FPH, FPL,
257 I0H, I0L, I1H, I1L, I2H, I2L, I3H, I3L,
258 M0H, M0L, M1H, M1L, M2H, M2L, M3H, M3L,
259 B0H, B0L, B1H, B1L, B2H, B2L, B3H, B3L,
260 L0H, L0L, L1H, L1L, L2H, L2L, L3H, L3L]>;
262 def D : RegisterClass<"BF", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> {
263 let SubRegClassList = [D16L, D16H];
266 def P : RegisterClass<"BF", [i32], 32, [P0, P1, P2, P3, P4, P5, FP, SP]> {
267 let SubRegClassList = [P16L, P16H];
268 let MethodProtos = [{
269 iterator allocation_order_end(const MachineFunction &MF) const;
271 let MethodBodies = [{
273 PClass::allocation_order_end(const MachineFunction &MF) const {
274 const TargetMachine &TM = MF.getTarget();
275 const TargetRegisterInfo *RI = TM.getRegisterInfo();
276 return allocation_order_begin(MF)
277 + (RI->hasFP(MF) ? 7 : 6);
282 def I : RegisterClass<"BF", [i32], 32, [I0, I1, I2, I3]>;
283 def M : RegisterClass<"BF", [i32], 32, [M0, M1, M2, M3]>;
285 def DP : RegisterClass<"BF", [i32], 32,
286 [R0, R1, R2, R3, R4, R5, R6, R7,
287 P0, P1, P2, P3, P4, P5, FP, SP]> {
288 let SubRegClassList = [DP16L, DP16H];
289 let MethodProtos = [{
290 iterator allocation_order_end(const MachineFunction &MF) const;
292 let MethodBodies = [{
294 DPClass::allocation_order_end(const MachineFunction &MF) const {
295 const TargetMachine &TM = MF.getTarget();
296 const TargetRegisterInfo *RI = TM.getRegisterInfo();
297 return allocation_order_begin(MF)
298 + (RI->hasFP(MF) ? 15 : 14);
303 def GR : RegisterClass<"BF", [i32], 32,
304 [R0, R1, R2, R3, R4, R5, R6, R7,
305 P0, P1, P2, P3, P4, P5,
306 I0, I1, I2, I3, M0, M1, M2, M3,
307 B0, B1, B2, B3, L0, L1, L2, L3,
309 let MethodProtos = [{
310 iterator allocation_order_end(const MachineFunction &MF) const;
312 let MethodBodies = [{
314 GRClass::allocation_order_end(const MachineFunction &MF) const {
315 const TargetMachine &TM = MF.getTarget();
316 const TargetRegisterInfo *RI = TM.getRegisterInfo();
317 return allocation_order_begin(MF)
318 + (RI->hasFP(MF) ? 31 : 30);
323 def ALL : RegisterClass<"BF", [i32], 32,
324 [R0, R1, R2, R3, R4, R5, R6, R7,
325 P0, P1, P2, P3, P4, P5,
326 I0, I1, I2, I3, M0, M1, M2, M3,
327 B0, B1, B2, B3, L0, L1, L2, L3,
329 A0X, A0W, A1X, A1W, ASTAT, RETS,
330 LC0, LT0, LB0, LC1, LT1, LB1, CYCLES, CYCLES2,
331 USP, SEQSTAT, SYSCFG, RETI, RETX, RETN, RETE, EMUDAT]> {
332 let MethodProtos = [{
333 iterator allocation_order_end(const MachineFunction &MF) const;
335 let MethodBodies = [{
337 ALLClass::allocation_order_end(const MachineFunction &MF) const {
338 const TargetMachine &TM = MF.getTarget();
339 const TargetRegisterInfo *RI = TM.getRegisterInfo();
340 return allocation_order_begin(MF)
341 + (RI->hasFP(MF) ? 31 : 30);
346 def PI : RegisterClass<"BF", [i32], 32,
347 [P0, P1, P2, P3, P4, P5, I0, I1, I2, I3, FP, SP]> {
348 let MethodProtos = [{
349 iterator allocation_order_end(const MachineFunction &MF) const;
351 let MethodBodies = [{
353 PIClass::allocation_order_end(const MachineFunction &MF) const {
354 const TargetMachine &TM = MF.getTarget();
355 const TargetRegisterInfo *RI = TM.getRegisterInfo();
356 return allocation_order_begin(MF)
357 + (RI->hasFP(MF) ? 11 : 10);
362 // We are going to pretend that CC and !CC are 32-bit registers, even though
363 // they only can hold 1 bit.
364 let CopyCost = -1, Size = 8 in {
365 def JustCC : RegisterClass<"BF", [i32], 8, [CC]>;
366 def NotCC : RegisterClass<"BF", [i32], 8, [NCC]>;
367 def AnyCC : RegisterClass<"BF", [i32], 8, [CC, NCC]> {
368 let MethodProtos = [{
369 iterator allocation_order_end(const MachineFunction &MF) const;
371 let MethodBodies = [{
373 AnyCCClass::allocation_order_end(const MachineFunction &MF) const {
374 return allocation_order_begin(MF)+1;
378 def StatBit : RegisterClass<"BF", [i1], 8,
379 [AZ, AN, CC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS]>;