1 //===- BlackfinRegisterInfo.cpp - Blackfin Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Blackfin implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
16 #include "BlackfinRegisterInfo.h"
17 #include "BlackfinSubtarget.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineLocation.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Type.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
34 BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
35 const TargetInstrInfo &tii)
36 : BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
41 BlackfinRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
43 static const unsigned CalleeSavedRegs[] = {
48 return CalleeSavedRegs;
52 BlackfinRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
54 BitVector Reserved(getNumRegs());
66 Reserved.set(CYCLES).set(CYCLES2);
78 // hasFP - Return true if the specified function should have a dedicated frame
79 // pointer register. This is true if the function has variable sized allocas or
80 // if frame pointer elimination is disabled.
81 bool BlackfinRegisterInfo::hasFP(const MachineFunction &MF) const {
82 const MachineFrameInfo *MFI = MF.getFrameInfo();
83 return DisableFramePointerElim(MF) ||
84 MFI->adjustsStack() || MFI->hasVarSizedObjects();
87 bool BlackfinRegisterInfo::
88 requiresRegisterScavenging(const MachineFunction &MF) const {
92 // Emit instructions to add delta to D/P register. ScratchReg must be of the
93 // same class as Reg (P).
94 void BlackfinRegisterInfo::adjustRegister(MachineBasicBlock &MBB,
95 MachineBasicBlock::iterator I,
102 if (isInt<7>(delta)) {
103 BuildMI(MBB, I, DL, TII.get(BF::ADDpp_imm7), Reg)
104 .addReg(Reg) // No kill on two-addr operand
109 // We must load delta into ScratchReg and add that.
110 loadConstant(MBB, I, DL, ScratchReg, delta);
111 if (BF::PRegClass.contains(Reg)) {
112 assert(BF::PRegClass.contains(ScratchReg) &&
113 "ScratchReg must be a P register");
114 BuildMI(MBB, I, DL, TII.get(BF::ADDpp), Reg)
115 .addReg(Reg, RegState::Kill)
116 .addReg(ScratchReg, RegState::Kill);
118 assert(BF::DRegClass.contains(Reg) && "Reg must be a D or P register");
119 assert(BF::DRegClass.contains(ScratchReg) &&
120 "ScratchReg must be a D register");
121 BuildMI(MBB, I, DL, TII.get(BF::ADD), Reg)
122 .addReg(Reg, RegState::Kill)
123 .addReg(ScratchReg, RegState::Kill);
127 // Emit instructions to load a constant into D/P register
128 void BlackfinRegisterInfo::loadConstant(MachineBasicBlock &MBB,
129 MachineBasicBlock::iterator I,
133 if (isInt<7>(value)) {
134 BuildMI(MBB, I, DL, TII.get(BF::LOADimm7), Reg).addImm(value);
138 if (isUInt<16>(value)) {
139 BuildMI(MBB, I, DL, TII.get(BF::LOADuimm16), Reg).addImm(value);
143 if (isInt<16>(value)) {
144 BuildMI(MBB, I, DL, TII.get(BF::LOADimm16), Reg).addImm(value);
148 // We must split into halves
150 TII.get(BF::LOAD16i), getSubReg(Reg, BF::hi16))
151 .addImm((value >> 16) & 0xffff)
152 .addReg(Reg, RegState::ImplicitDefine);
154 TII.get(BF::LOAD16i), getSubReg(Reg, BF::lo16))
155 .addImm(value & 0xffff)
156 .addReg(Reg, RegState::ImplicitKill)
157 .addReg(Reg, RegState::ImplicitDefine);
160 void BlackfinRegisterInfo::
161 eliminateCallFramePseudoInstr(MachineFunction &MF,
162 MachineBasicBlock &MBB,
163 MachineBasicBlock::iterator I) const {
164 if (!hasReservedCallFrame(MF)) {
165 int64_t Amount = I->getOperand(0).getImm();
167 assert(Amount%4 == 0 && "Unaligned call frame size");
168 if (I->getOpcode() == BF::ADJCALLSTACKDOWN) {
169 adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, -Amount);
171 assert(I->getOpcode() == BF::ADJCALLSTACKUP &&
172 "Unknown call frame pseudo instruction");
173 adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, Amount);
180 /// findScratchRegister - Find a 'free' register. Try for a call-clobbered
181 /// register first and then a spilled callee-saved register if that fails.
182 static unsigned findScratchRegister(MachineBasicBlock::iterator II,
184 const TargetRegisterClass *RC,
186 assert(RS && "Register scavenging must be on");
187 unsigned Reg = RS->FindUnusedReg(RC);
189 Reg = RS->scavengeRegister(RC, II, SPAdj);
194 BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
195 int SPAdj, RegScavenger *RS) const {
196 MachineInstr &MI = *II;
197 MachineBasicBlock &MBB = *MI.getParent();
198 MachineFunction &MF = *MBB.getParent();
199 DebugLoc DL = MI.getDebugLoc();
202 for (FIPos=0; !MI.getOperand(FIPos).isFI(); ++FIPos) {
203 assert(FIPos < MI.getNumOperands() &&
204 "Instr doesn't have FrameIndex operand!");
206 int FrameIndex = MI.getOperand(FIPos).getIndex();
207 assert(FIPos+1 < MI.getNumOperands() && MI.getOperand(FIPos+1).isImm());
208 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex)
209 + MI.getOperand(FIPos+1).getImm();
210 unsigned BaseReg = BF::FP;
212 assert(SPAdj==0 && "Unexpected SP adjust in function with frame pointer");
215 Offset += MF.getFrameInfo()->getStackSize() + SPAdj;
218 bool isStore = false;
220 switch (MI.getOpcode()) {
224 assert(Offset%4 == 0 && "Unaligned i32 stack access");
225 assert(FIPos==1 && "Bad frame index operand");
226 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
227 MI.getOperand(FIPos+1).setImm(Offset);
228 if (isUInt<6>(Offset)) {
229 MI.setDesc(TII.get(isStore
230 ? BF::STORE32p_uimm6m4
231 : BF::LOAD32p_uimm6m4));
234 if (BaseReg == BF::FP && isUInt<7>(-Offset)) {
235 MI.setDesc(TII.get(isStore
236 ? BF::STORE32fp_nimm7m4
237 : BF::LOAD32fp_nimm7m4));
238 MI.getOperand(FIPos+1).setImm(-Offset);
241 if (isInt<18>(Offset)) {
242 MI.setDesc(TII.get(isStore
243 ? BF::STORE32p_imm18m4
244 : BF::LOAD32p_imm18m4));
247 // Use RegScavenger to calculate proper offset...
249 llvm_unreachable("Stack frame offset too big");
253 assert(MI.getOperand(0).isReg() && "ADD instruction needs a register");
254 unsigned DestReg = MI.getOperand(0).getReg();
255 // We need to produce a stack offset in a P register. We emit:
258 assert(FIPos==1 && "Bad frame index operand");
259 loadConstant(MBB, II, DL, DestReg, Offset);
260 MI.getOperand(1).ChangeToRegister(DestReg, false, false, true);
261 MI.getOperand(2).ChangeToRegister(BaseReg, false);
267 assert(Offset%2 == 0 && "Unaligned i16 stack access");
268 assert(FIPos==1 && "Bad frame index operand");
269 // We need a P register to use as an address
270 unsigned ScratchReg = findScratchRegister(II, RS, &BF::PRegClass, SPAdj);
271 assert(ScratchReg && "Could not scavenge register");
272 loadConstant(MBB, II, DL, ScratchReg, Offset);
273 BuildMI(MBB, II, DL, TII.get(BF::ADDpp), ScratchReg)
274 .addReg(ScratchReg, RegState::Kill)
276 MI.setDesc(TII.get(isStore ? BF::STORE16pi : BF::LOAD16pi));
277 MI.getOperand(1).ChangeToRegister(ScratchReg, false, false, true);
282 // This is an AnyCC spill, we need a scratch register.
283 assert(FIPos==1 && "Bad frame index operand");
284 MachineOperand SpillReg = MI.getOperand(0);
285 unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
286 assert(ScratchReg && "Could not scavenge register");
287 if (SpillReg.getReg()==BF::NCC) {
288 BuildMI(MBB, II, DL, TII.get(BF::MOVENCC_z), ScratchReg)
289 .addOperand(SpillReg);
290 BuildMI(MBB, II, DL, TII.get(BF::BITTGL), ScratchReg)
291 .addReg(ScratchReg).addImm(0);
293 BuildMI(MBB, II, DL, TII.get(BF::MOVECC_zext), ScratchReg)
294 .addOperand(SpillReg);
297 MI.setDesc(TII.get(BF::STORE8p_imm16));
298 MI.getOperand(0).ChangeToRegister(ScratchReg, false, false, true);
299 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
300 MI.getOperand(FIPos+1).setImm(Offset);
304 // This is an restore, we need a scratch register.
305 assert(FIPos==1 && "Bad frame index operand");
306 MachineOperand SpillReg = MI.getOperand(0);
307 unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
308 assert(ScratchReg && "Could not scavenge register");
309 MI.setDesc(TII.get(BF::LOAD32p_imm16_8z));
310 MI.getOperand(0).ChangeToRegister(ScratchReg, true);
311 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
312 MI.getOperand(FIPos+1).setImm(Offset);
314 if (SpillReg.getReg()==BF::CC) {
316 BuildMI(MBB, II, DL, TII.get(BF::MOVECC_nz), BF::CC)
317 .addReg(ScratchReg, RegState::Kill);
319 // Restore NCC (CC = D==0)
320 BuildMI(MBB, II, DL, TII.get(BF::SETEQri_not), BF::NCC)
321 .addReg(ScratchReg, RegState::Kill)
327 llvm_unreachable("Cannot eliminate frame index");
332 void BlackfinRegisterInfo::
333 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
334 RegScavenger *RS) const {
335 MachineFrameInfo *MFI = MF.getFrameInfo();
336 const TargetRegisterClass *RC = BF::DPRegisterClass;
337 if (requiresRegisterScavenging(MF)) {
338 // Reserve a slot close to SP or frame pointer.
339 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
345 // Emit a prologue that sets up a stack frame.
346 // On function entry, R0-R2 and P0 may hold arguments.
347 // R3, P1, and P2 may be used as scratch registers
348 void BlackfinRegisterInfo::emitPrologue(MachineFunction &MF) const {
349 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
350 MachineBasicBlock::iterator MBBI = MBB.begin();
351 MachineFrameInfo *MFI = MF.getFrameInfo();
352 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
354 int FrameSize = MFI->getStackSize();
356 FrameSize = (FrameSize+3) & ~3;
357 MFI->setStackSize(FrameSize);
361 assert(!MFI->adjustsStack() &&
362 "FP elimination on a non-leaf function is not supported");
363 adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize);
367 // emit a LINK instruction
368 if (FrameSize <= 0x3ffff) {
369 BuildMI(MBB, MBBI, dl, TII.get(BF::LINK)).addImm(FrameSize);
373 // Frame is too big, do a manual LINK:
379 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
380 .addReg(BF::RETS, RegState::Kill);
381 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
382 .addReg(BF::FP, RegState::Kill);
383 BuildMI(MBB, MBBI, dl, TII.get(BF::MOVE), BF::FP)
385 loadConstant(MBB, MBBI, dl, BF::P1, -FrameSize);
386 BuildMI(MBB, MBBI, dl, TII.get(BF::ADDpp), BF::SP)
387 .addReg(BF::SP, RegState::Kill)
388 .addReg(BF::P1, RegState::Kill);
392 void BlackfinRegisterInfo::emitEpilogue(MachineFunction &MF,
393 MachineBasicBlock &MBB) const {
394 MachineFrameInfo *MFI = MF.getFrameInfo();
395 MachineBasicBlock::iterator MBBI = prior(MBB.end());
396 DebugLoc dl = MBBI->getDebugLoc();
398 int FrameSize = MFI->getStackSize();
399 assert(FrameSize%4 == 0 && "Misaligned frame size");
402 assert(!MFI->adjustsStack() &&
403 "FP elimination on a non-leaf function is not supported");
404 adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, FrameSize);
408 // emit an UNLINK instruction
409 BuildMI(MBB, MBBI, dl, TII.get(BF::UNLINK));
412 unsigned BlackfinRegisterInfo::getRARegister() const {
417 BlackfinRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
418 return hasFP(MF) ? BF::FP : BF::SP;
421 unsigned BlackfinRegisterInfo::getEHExceptionRegister() const {
422 llvm_unreachable("What is the exception register");
426 unsigned BlackfinRegisterInfo::getEHHandlerRegister() const {
427 llvm_unreachable("What is the exception handler register");
431 int BlackfinRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
432 llvm_unreachable("What is the dwarf register number");
436 #include "BlackfinGenRegisterInfo.inc"