1 //===- Blackfin.td - Describe the Blackfin Target Machine --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // Blackfin Subtarget features.
21 //===----------------------------------------------------------------------===//
23 def FeatureSSYNC : SubtargetFeature<"ssync","ssyncWorkaround", "true",
24 "Work around SSYNC bugs">;
26 //===----------------------------------------------------------------------===//
27 // Register File, Calling Conv, Instruction Descriptions
28 //===----------------------------------------------------------------------===//
30 include "BlackfinRegisterInfo.td"
31 include "BlackfinCallingConv.td"
32 include "BlackfinInstrInfo.td"
34 def BlackfinInstrInfo : InstrInfo {}
36 //===----------------------------------------------------------------------===//
37 // Blackfin processors supported.
38 //===----------------------------------------------------------------------===//
40 class Proc<string Name, list<SubtargetFeature> Features>
41 : Processor<Name, NoItineraries, Features>;
43 def : Proc<"generic", [FeatureSSYNC]>;
45 //===----------------------------------------------------------------------===//
46 // Declare the target which we are implementing
47 //===----------------------------------------------------------------------===//
49 def Blackfin : Target {
50 // Pull in Instruction Info:
51 let InstructionSet = BlackfinInstrInfo;