1 //===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "AlphaRegisterInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Type.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/ADT/STLExtras.h"
35 extern cl::opt<bool> EnableAlphaLSMark;
39 static const int IMM_LOW = -32768;
40 static const int IMM_HIGH = 32767;
41 static const int IMM_MULT = 65536;
43 static long getUpper16(long l)
45 long y = l / IMM_MULT;
46 if (l % IMM_MULT > IMM_HIGH)
51 static long getLower16(long l)
53 long h = getUpper16(l);
54 return l - h * IMM_MULT;
63 AlphaRegisterInfo::AlphaRegisterInfo()
64 : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP)
69 AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
70 MachineBasicBlock::iterator MI,
71 unsigned SrcReg, int FrameIdx,
72 const TargetRegisterClass *RC) const {
73 //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
74 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
75 if (EnableAlphaLSMark)
76 BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(1)
78 if (RC == Alpha::F4RCRegisterClass)
79 BuildMI(MBB, MI, Alpha::STS, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
80 else if (RC == Alpha::F8RCRegisterClass)
81 BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
82 else if (RC == Alpha::GPRCRegisterClass)
83 BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
89 AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator MI,
91 unsigned DestReg, int FrameIdx,
92 const TargetRegisterClass *RC) const {
93 //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
94 if (EnableAlphaLSMark)
95 BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2)
97 if (RC == Alpha::F4RCRegisterClass)
98 BuildMI(MBB, MI, Alpha::LDS, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
99 else if (RC == Alpha::F8RCRegisterClass)
100 BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
101 else if (RC == Alpha::GPRCRegisterClass)
102 BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
108 AlphaRegisterInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const
110 switch (MI->getOpcode()) {
117 if (MI->getOperand(1).isFrameIndex()) {
118 FrameIndex = MI->getOperand(1).getFrameIndex();
119 return MI->getOperand(0).getReg();
126 MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
128 int FrameIndex) const {
129 // Make sure this is a reg-reg copy.
130 unsigned Opc = MI->getOpcode();
132 if ((Opc == Alpha::BIS &&
133 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
134 if (OpNum == 0) { // move -> store
135 unsigned InReg = MI->getOperand(1).getReg();
136 return BuildMI(Alpha::STQ, 3).addReg(InReg).addFrameIndex(FrameIndex)
138 } else { // load -> move
139 unsigned OutReg = MI->getOperand(0).getReg();
140 return BuildMI(Alpha::LDQ, 2, OutReg).addFrameIndex(FrameIndex)
143 } else if ((Opc == Alpha::CPYSS &&
144 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
145 if (OpNum == 0) { // move -> store
146 unsigned InReg = MI->getOperand(1).getReg();
147 return BuildMI(Alpha::STS, 3).addReg(InReg).addFrameIndex(FrameIndex)
149 } else { // load -> move
150 unsigned OutReg = MI->getOperand(0).getReg();
151 return BuildMI(Alpha::LDS, 2, OutReg).addFrameIndex(FrameIndex)
154 } else if ((Opc == Alpha::CPYST &&
155 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
156 if (OpNum == 0) { // move -> store
157 unsigned InReg = MI->getOperand(1).getReg();
158 return BuildMI(Alpha::STT, 3).addReg(InReg).addFrameIndex(FrameIndex)
160 } else { // load -> move
161 unsigned OutReg = MI->getOperand(0).getReg();
162 return BuildMI(Alpha::LDT, 2, OutReg).addFrameIndex(FrameIndex)
170 void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
171 MachineBasicBlock::iterator MI,
172 unsigned DestReg, unsigned SrcReg,
173 const TargetRegisterClass *RC) const {
174 // std::cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
175 if (RC == Alpha::GPRCRegisterClass) {
176 BuildMI(MBB, MI, Alpha::BIS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
177 } else if (RC == Alpha::F4RCRegisterClass) {
178 BuildMI(MBB, MI, Alpha::CPYSS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
179 } else if (RC == Alpha::F8RCRegisterClass) {
180 BuildMI(MBB, MI, Alpha::CPYST, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
182 std::cerr << "Attempt to copy register that is not GPR or FPR";
187 //===----------------------------------------------------------------------===//
188 // Stack Frame Processing methods
189 //===----------------------------------------------------------------------===//
191 // hasFP - Return true if the specified function should have a dedicated frame
192 // pointer register. This is true if the function has variable sized allocas or
193 // if frame pointer elimination is disabled.
195 static bool hasFP(MachineFunction &MF) {
196 MachineFrameInfo *MFI = MF.getFrameInfo();
197 return MFI->hasVarSizedObjects();
200 void AlphaRegisterInfo::
201 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
202 MachineBasicBlock::iterator I) const {
204 // If we have a frame pointer, turn the adjcallstackup instruction into a
205 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
207 MachineInstr *Old = I;
208 unsigned Amount = Old->getOperand(0).getImmedValue();
210 // We need to keep the stack aligned properly. To do this, we round the
211 // amount of space needed for the outgoing arguments up to the next
212 // alignment boundary.
213 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
214 Amount = (Amount+Align-1)/Align*Align;
217 if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
218 New=BuildMI(Alpha::LDA, 2, Alpha::R30)
219 .addImm(-Amount).addReg(Alpha::R30);
221 assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
222 New=BuildMI(Alpha::LDA, 2, Alpha::R30)
223 .addImm(Amount).addReg(Alpha::R30);
226 // Replace the pseudo instruction with a new instruction...
234 //Alpha has a slightly funny stack:
237 //fixed locals (and spills, callee saved, etc)
243 AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
245 MachineInstr &MI = *II;
246 MachineBasicBlock &MBB = *MI.getParent();
247 MachineFunction &MF = *MBB.getParent();
250 while (!MI.getOperand(i).isFrameIndex()) {
252 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
255 int FrameIndex = MI.getOperand(i).getFrameIndex();
257 // Add the base register of R30 (SP) or R15 (FP).
258 MI.SetMachineOperandReg(i + 1, FP ? Alpha::R15 : Alpha::R30);
260 // Now add the frame object offset to the offset from the virtual frame index.
261 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
263 DEBUG(std::cerr << "FI: " << FrameIndex << " Offset: " << Offset << "\n");
265 Offset += MF.getFrameInfo()->getStackSize();
267 DEBUG(std::cerr << "Corrected Offset " << Offset <<
268 " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
270 if (Offset > IMM_HIGH || Offset < IMM_LOW) {
271 //so in this case, we need to use a temporary register, and move the original
274 MI.SetMachineOperandReg(i + 1, Alpha::R28);
275 MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed,
278 MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
279 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
282 MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, Offset);
287 void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
288 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
289 MachineBasicBlock::iterator MBBI = MBB.begin();
290 MachineFrameInfo *MFI = MF.getFrameInfo();
293 static int curgpdist = 0;
296 BuildMI(MBB, MBBI, Alpha::LDAHg, 3, Alpha::R29)
297 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
298 .addReg(Alpha::R27).addImm(++curgpdist);
299 BuildMI(MBB, MBBI, Alpha::LDAg, 3, Alpha::R29)
300 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
301 .addReg(Alpha::R29).addImm(curgpdist);
303 //evil const_cast until MO stuff setup to handle const
304 BuildMI(MBB, MBBI, Alpha::ALTENT, 1).addGlobalAddress(const_cast<Function*>(MF.getFunction()), true);
306 // Get the number of bytes to allocate from the FrameInfo
307 long NumBytes = MFI->getStackSize();
309 if (MFI->hasCalls() && !FP) {
310 // We reserve argument space for call sites in the function immediately on
311 // entry to the current function. This eliminates the need for add/sub
312 // brackets around call sites.
313 //If there is a frame pointer, then we don't do this
314 NumBytes += MFI->getMaxCallFrameSize();
315 DEBUG(std::cerr << "Added " << MFI->getMaxCallFrameSize()
316 << " to the stack due to calls\n");
320 NumBytes += 8; //reserve space for the old FP
322 // Do we need to allocate space on the stack?
323 if (NumBytes == 0) return;
325 // Update frame info to pretend that this is part of the stack...
326 MFI->setStackSize(NumBytes);
328 // adjust stack pointer: r30 -= numbytes
329 NumBytes = -NumBytes;
330 if (NumBytes >= IMM_LOW) {
331 BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(NumBytes)
333 } else if (getUpper16(NumBytes) >= IMM_LOW) {
334 BuildMI(MBB, MBBI, Alpha::LDAH, 2, Alpha::R30).addImm(getUpper16(NumBytes))
336 BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(getLower16(NumBytes))
339 std::cerr << "Too big a stack frame at " << NumBytes << "\n";
343 //now if we need to, save the old FP and set the new
346 if (EnableAlphaLSMark)
347 BuildMI(MBB, MBBI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(1)
349 BuildMI(MBB, MBBI, Alpha::STQ, 3).addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
350 //this must be the last instr in the prolog
351 BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R15).addReg(Alpha::R30).addReg(Alpha::R30);
356 void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
357 MachineBasicBlock &MBB) const {
358 const MachineFrameInfo *MFI = MF.getFrameInfo();
359 MachineBasicBlock::iterator MBBI = prior(MBB.end());
360 assert(((MBBI->getOpcode() == Alpha::RET) || (MBBI->getOpcode() == Alpha::RETDAG))
361 && "Can only insert epilog into returning blocks");
365 // Get the number of bytes allocated from the FrameInfo...
366 long NumBytes = MFI->getStackSize();
368 //now if we need to, restore the old FP
371 //copy the FP into the SP (discards allocas)
372 BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R30).addReg(Alpha::R15)
375 if (EnableAlphaLSMark)
376 BuildMI(MBB, MBBI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2)
378 BuildMI(MBB, MBBI, Alpha::LDQ, 2, Alpha::R15).addImm(0).addReg(Alpha::R15);
383 if (NumBytes <= IMM_HIGH) {
384 BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(NumBytes)
386 } else if (getUpper16(NumBytes) <= IMM_HIGH) {
387 BuildMI(MBB, MBBI, Alpha::LDAH, 2, Alpha::R30)
388 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
389 BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30)
390 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
392 std::cerr << "Too big a stack frame at " << NumBytes << "\n";
398 #include "AlphaGenRegisterInfo.inc"
400 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
402 std::string s(RegisterDescriptors[reg].Name);