1 //===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "AlphaRegisterInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Type.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineLocation.h"
25 #include "llvm/Target/TargetFrameLowering.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/STLExtras.h"
36 #include "AlphaGenRegisterDesc.inc"
37 #include "AlphaGenRegisterInfo.inc"
40 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
41 : AlphaGenRegisterInfo(AlphaRegDesc, AlphaRegInfoDesc,
42 Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
46 static long getUpper16(long l) {
47 long y = l / Alpha::IMM_MULT;
48 if (l % Alpha::IMM_MULT > Alpha::IMM_HIGH)
53 static long getLower16(long l) {
54 long h = getUpper16(l);
55 return l - h * Alpha::IMM_MULT;
58 const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
60 static const unsigned CalleeSavedRegs[] = {
61 Alpha::R9, Alpha::R10,
62 Alpha::R11, Alpha::R12,
63 Alpha::R13, Alpha::R14,
67 Alpha::F8, Alpha::F9, 0
69 return CalleeSavedRegs;
72 BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
73 BitVector Reserved(getNumRegs());
74 Reserved.set(Alpha::R15);
75 Reserved.set(Alpha::R29);
76 Reserved.set(Alpha::R30);
77 Reserved.set(Alpha::R31);
81 //===----------------------------------------------------------------------===//
82 // Stack Frame Processing methods
83 //===----------------------------------------------------------------------===//
85 void AlphaRegisterInfo::
86 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator I) const {
88 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
91 // If we have a frame pointer, turn the adjcallstackup instruction into a
92 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
94 MachineInstr *Old = I;
95 uint64_t Amount = Old->getOperand(0).getImm();
97 // We need to keep the stack aligned properly. To do this, we round the
98 // amount of space needed for the outgoing arguments up to the next
99 // alignment boundary.
100 unsigned Align = TFI->getStackAlignment();
101 Amount = (Amount+Align-1)/Align*Align;
104 if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
105 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30)
106 .addImm(-Amount).addReg(Alpha::R30);
108 assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
109 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30)
110 .addImm(Amount).addReg(Alpha::R30);
113 // Replace the pseudo instruction with a new instruction...
121 //Alpha has a slightly funny stack:
124 //fixed locals (and spills, callee saved, etc)
130 AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
131 int SPAdj, RegScavenger *RS) const {
132 assert(SPAdj == 0 && "Unexpected");
135 MachineInstr &MI = *II;
136 MachineBasicBlock &MBB = *MI.getParent();
137 MachineFunction &MF = *MBB.getParent();
138 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
140 bool FP = TFI->hasFP(MF);
142 while (!MI.getOperand(i).isFI()) {
144 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
147 int FrameIndex = MI.getOperand(i).getIndex();
149 // Add the base register of R30 (SP) or R15 (FP).
150 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
152 // Now add the frame object offset to the offset from the virtual frame index.
153 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
155 DEBUG(errs() << "FI: " << FrameIndex << " Offset: " << Offset << "\n");
157 Offset += MF.getFrameInfo()->getStackSize();
159 DEBUG(errs() << "Corrected Offset " << Offset
160 << " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
162 if (Offset > Alpha::IMM_HIGH || Offset < Alpha::IMM_LOW) {
163 DEBUG(errs() << "Unconditionally using R28 for evil purposes Offset: "
165 //so in this case, we need to use a temporary register, and move the
166 //original inst off the SP/FP
168 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
169 MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
171 MachineInstr* nMI=BuildMI(MF, MI.getDebugLoc(),
172 TII.get(Alpha::LDAH), Alpha::R28)
173 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
176 MI.getOperand(i).ChangeToImmediate(Offset);
180 unsigned AlphaRegisterInfo::getRARegister() const {
184 unsigned AlphaRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
185 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
187 return TFI->hasFP(MF) ? Alpha::R15 : Alpha::R30;
190 unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
191 llvm_unreachable("What is the exception register");
195 unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
196 llvm_unreachable("What is the exception handler register");
200 int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
201 llvm_unreachable("What is the dwarf register number");
205 int AlphaRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
206 llvm_unreachable("What is the dwarf register number");
210 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
212 std::string s(AlphaRegDesc[reg].Name);