lib/Target/Alpha/AlphaLLRP.cpp

   1 //===-- AlphaLLRP.cpp - Alpha Load Load Replay Trap elimination pass. -- --===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by Andrew Lenharth and is distributed under the
   6 // University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Here we check for potential replay traps introduced by the spiller
  11 // We also align some branch targets if we can do so for free
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 #include "Alpha.h"
  16 #include "llvm/CodeGen/MachineFunctionPass.h"
  17 #include "llvm/CodeGen/MachineInstrBuilder.h"
  18 #include "llvm/Target/TargetMachine.h"
  19 #include "llvm/Target/TargetInstrInfo.h"
  20 #include "llvm/ADT/SetOperations.h"
  21 #include "llvm/ADT/Statistic.h"
  22 #include "llvm/Support/CommandLine.h"
  23 using namespace llvm;
  24
  25 namespace {
  26   Statistic nopintro("alpha-nops", "Number of nops inserted");
  27   Statistic nopalign("alpha-nops-align",
  28                        "Number of nops inserted for alignment");
  29
  30   cl::opt<bool>
  31   AlignAll("alpha-align-all", cl::Hidden,
  32                    cl::desc("Align all blocks"));
  33
  34   struct AlphaLLRPPass : public MachineFunctionPass {
  35     /// Target machine description which we query for reg. names, data
  36     /// layout, etc.
  37     ///
  38     AlphaTargetMachine &TM;
  39
  40     AlphaLLRPPass(AlphaTargetMachine &tm) : TM(tm) { }
  41
  42     virtual const char *getPassName() const {
  43       return "Alpha NOP inserter";
  44     }
  45
  46     bool runOnMachineFunction(MachineFunction &F) {
  47       const TargetInstrInfo *TII = F.getTarget().getInstrInfo();
  48       bool Changed = false;
  49       MachineInstr* prev[3] = {0,0,0};
  50       unsigned count = 0;
  51       for (MachineFunction::iterator FI = F.begin(), FE = F.end();
  52            FI != FE; ++FI) {
  53         MachineBasicBlock& MBB = *FI;
  54         bool ub = false;
  55           for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
  56             if (count%4 == 0)
  57               prev[0] = prev[1] = prev[2] = 0; //Slots cleared at fetch boundary
  58             ++count;
  59             MachineInstr *MI = I++;
  60             switch (MI->getOpcode()) {
  61             case Alpha::LDQ:  case Alpha::LDL:
  62             case Alpha::LDWU: case Alpha::LDBU:
  63             case Alpha::LDT: case Alpha::LDS:
  64             case Alpha::STQ:  case Alpha::STL:
  65             case Alpha::STW:  case Alpha::STB:
  66             case Alpha::STT: case Alpha::STS:
  67               if (MI->getOperand(2).getReg() == Alpha::R30) {
  68                 if (prev[0]
  69                     && prev[0]->getOperand(2).getReg() ==
  70                     MI->getOperand(2).getReg()
  71                     && prev[0]->getOperand(1).getImmedValue() ==
  72                     MI->getOperand(1).getImmedValue()) {
  73                   prev[0] = prev[1];
  74                   prev[1] = prev[2];
  75                   prev[2] = 0;
  76                   BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
  77                     .addReg(Alpha::R31);
  78                   Changed = true; nopintro += 1;
  79                   count += 1;
  80                 } else if (prev[1]
  81                            && prev[1]->getOperand(2).getReg() ==
  82                            MI->getOperand(2).getReg()
  83                            && prev[1]->getOperand(1).getImmedValue() ==
  84                            MI->getOperand(1).getImmedValue()) {
  85                   prev[0] = prev[2];
  86                   prev[1] = prev[2] = 0;
  87                   BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
  88                     .addReg(Alpha::R31);
  89                   BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
  90                     .addReg(Alpha::R31);
  91                   Changed = true; nopintro += 2;
  92                   count += 2;
  93                 } else if (prev[2]
  94                            && prev[2]->getOperand(2).getReg() ==
  95                            MI->getOperand(2).getReg()
  96                            && prev[2]->getOperand(1).getImmedValue() ==
  97                            MI->getOperand(1).getImmedValue()) {
  98                   prev[0] = prev[1] = prev[2] = 0;
  99                   BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
 100                     .addReg(Alpha::R31);
 101                   BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
 102                     .addReg(Alpha::R31);
 103                   BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
 104                     .addReg(Alpha::R31);
 105                   Changed = true; nopintro += 3;
 106                   count += 3;
 107                 }
 108                 prev[0] = prev[1];
 109                 prev[1] = prev[2];
 110                 prev[2] = MI;
 111                 break;
 112               }
 113               prev[0] = prev[1];
 114               prev[1] = prev[2];
 115               prev[2] = 0;
 116               break;
 117             case Alpha::ALTENT:
 118             case Alpha::MEMLABEL:
 119             case Alpha::PCLABEL:
 120               --count;
 121               break;
 122             case Alpha::BR:
 123             case Alpha::JMP:
 124               ub = true;
 125               //fall through
 126             default:
 127               prev[0] = prev[1];
 128               prev[1] = prev[2];
 129               prev[2] = 0;
 130               break;
 131             }
 132           }
 133           if (ub || AlignAll) {
 134             //we can align stuff for free at this point
 135             while (count % 4) {
 136               BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31)
 137                 .addReg(Alpha::R31).addReg(Alpha::R31);
 138               ++count;
 139               ++nopalign;
 140               prev[0] = prev[1];
 141               prev[1] = prev[2];
 142               prev[2] = 0;
 143             }
 144           }
 145       }
 146       return Changed;
 147     }
 148   };
 149 } // end of anonymous namespace
 150
 151 FunctionPass *llvm::createAlphaLLRPPass(AlphaTargetMachine &tm) {
 152   return new AlphaLLRPPass(tm);
 153 }