1 //===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "AlphaInstrInfo.h"
16 #include "AlphaGenInstrInfo.inc"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 AlphaInstrInfo::AlphaInstrInfo()
22 : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts)),
26 bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
28 unsigned& destReg) const {
29 unsigned oc = MI.getOpcode();
30 if (oc == Alpha::BISr ||
33 oc == Alpha::CPYSSt ||
34 oc == Alpha::CPYSTs) {
37 assert(MI.getNumOperands() >= 3 &&
38 MI.getOperand(0).isRegister() &&
39 MI.getOperand(1).isRegister() &&
40 MI.getOperand(2).isRegister() &&
41 "invalid Alpha BIS instruction!");
42 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
43 sourceReg = MI.getOperand(1).getReg();
44 destReg = MI.getOperand(0).getReg();
52 AlphaInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
53 switch (MI->getOpcode()) {
60 if (MI->getOperand(1).isFrameIndex()) {
61 FrameIndex = MI->getOperand(1).getIndex();
62 return MI->getOperand(0).getReg();
70 AlphaInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
71 switch (MI->getOpcode()) {
78 if (MI->getOperand(1).isFrameIndex()) {
79 FrameIndex = MI->getOperand(1).getIndex();
80 return MI->getOperand(0).getReg();
87 static bool isAlphaIntCondCode(unsigned Opcode) {
103 unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
104 MachineBasicBlock *TBB,
105 MachineBasicBlock *FBB,
106 const SmallVectorImpl<MachineOperand> &Cond) const {
107 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
108 assert((Cond.size() == 2 || Cond.size() == 0) &&
109 "Alpha branch conditions have two components!");
113 if (Cond.empty()) // Unconditional branch
114 BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB);
115 else // Conditional branch
116 if (isAlphaIntCondCode(Cond[0].getImm()))
117 BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
118 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
120 BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
121 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
125 // Two-way Conditional Branch.
126 if (isAlphaIntCondCode(Cond[0].getImm()))
127 BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
128 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
130 BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
131 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
132 BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB);
136 bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
137 MachineBasicBlock::iterator MI,
138 unsigned DestReg, unsigned SrcReg,
139 const TargetRegisterClass *DestRC,
140 const TargetRegisterClass *SrcRC) const {
141 //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
142 if (DestRC != SrcRC) {
143 // Not yet supported!
147 if (DestRC == Alpha::GPRCRegisterClass) {
148 BuildMI(MBB, MI, get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
149 } else if (DestRC == Alpha::F4RCRegisterClass) {
150 BuildMI(MBB, MI, get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
151 } else if (DestRC == Alpha::F8RCRegisterClass) {
152 BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
154 // Attempt to copy register that is not GPR or FPR
162 AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
163 MachineBasicBlock::iterator MI,
164 unsigned SrcReg, bool isKill, int FrameIdx,
165 const TargetRegisterClass *RC) const {
166 //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
167 // << FrameIdx << "\n";
168 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
169 if (RC == Alpha::F4RCRegisterClass)
170 BuildMI(MBB, MI, get(Alpha::STS))
171 .addReg(SrcReg, false, false, isKill)
172 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
173 else if (RC == Alpha::F8RCRegisterClass)
174 BuildMI(MBB, MI, get(Alpha::STT))
175 .addReg(SrcReg, false, false, isKill)
176 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
177 else if (RC == Alpha::GPRCRegisterClass)
178 BuildMI(MBB, MI, get(Alpha::STQ))
179 .addReg(SrcReg, false, false, isKill)
180 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
185 void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
187 SmallVectorImpl<MachineOperand> &Addr,
188 const TargetRegisterClass *RC,
189 SmallVectorImpl<MachineInstr*> &NewMIs) const {
191 if (RC == Alpha::F4RCRegisterClass)
193 else if (RC == Alpha::F8RCRegisterClass)
195 else if (RC == Alpha::GPRCRegisterClass)
199 MachineInstrBuilder MIB =
200 BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
201 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
202 MachineOperand &MO = Addr[i];
204 MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
206 MIB.addImm(MO.getImm());
208 NewMIs.push_back(MIB);
212 AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
213 MachineBasicBlock::iterator MI,
214 unsigned DestReg, int FrameIdx,
215 const TargetRegisterClass *RC) const {
216 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
217 // << FrameIdx << "\n";
218 if (RC == Alpha::F4RCRegisterClass)
219 BuildMI(MBB, MI, get(Alpha::LDS), DestReg)
220 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
221 else if (RC == Alpha::F8RCRegisterClass)
222 BuildMI(MBB, MI, get(Alpha::LDT), DestReg)
223 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
224 else if (RC == Alpha::GPRCRegisterClass)
225 BuildMI(MBB, MI, get(Alpha::LDQ), DestReg)
226 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
231 void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
232 SmallVectorImpl<MachineOperand> &Addr,
233 const TargetRegisterClass *RC,
234 SmallVectorImpl<MachineInstr*> &NewMIs) const {
236 if (RC == Alpha::F4RCRegisterClass)
238 else if (RC == Alpha::F8RCRegisterClass)
240 else if (RC == Alpha::GPRCRegisterClass)
244 MachineInstrBuilder MIB =
245 BuildMI(MF, get(Opc), DestReg);
246 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
247 MachineOperand &MO = Addr[i];
249 MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
251 MIB.addImm(MO.getImm());
253 NewMIs.push_back(MIB);
256 MachineInstr *AlphaInstrInfo::foldMemoryOperand(MachineFunction &MF,
258 SmallVectorImpl<unsigned> &Ops,
259 int FrameIndex) const {
260 if (Ops.size() != 1) return NULL;
262 // Make sure this is a reg-reg copy.
263 unsigned Opc = MI->getOpcode();
265 MachineInstr *NewMI = NULL;
272 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
273 if (Ops[0] == 0) { // move -> store
274 unsigned InReg = MI->getOperand(1).getReg();
275 bool isKill = MI->getOperand(1).isKill();
276 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
277 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
278 NewMI = BuildMI(MF, get(Opc)).addReg(InReg, false, false, isKill)
279 .addFrameIndex(FrameIndex)
281 } else { // load -> move
282 unsigned OutReg = MI->getOperand(0).getReg();
283 bool isDead = MI->getOperand(0).isDead();
284 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
285 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
286 NewMI = BuildMI(MF, get(Opc)).addReg(OutReg, true, false, false, isDead)
287 .addFrameIndex(FrameIndex)
296 static unsigned AlphaRevCondCode(unsigned Opcode) {
298 case Alpha::BEQ: return Alpha::BNE;
299 case Alpha::BNE: return Alpha::BEQ;
300 case Alpha::BGE: return Alpha::BLT;
301 case Alpha::BGT: return Alpha::BLE;
302 case Alpha::BLE: return Alpha::BGT;
303 case Alpha::BLT: return Alpha::BGE;
304 case Alpha::BLBC: return Alpha::BLBS;
305 case Alpha::BLBS: return Alpha::BLBC;
306 case Alpha::FBEQ: return Alpha::FBNE;
307 case Alpha::FBNE: return Alpha::FBEQ;
308 case Alpha::FBGE: return Alpha::FBLT;
309 case Alpha::FBGT: return Alpha::FBLE;
310 case Alpha::FBLE: return Alpha::FBGT;
311 case Alpha::FBLT: return Alpha::FBGE;
313 assert(0 && "Unknown opcode");
315 return 0; // Not reached
319 bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
320 MachineBasicBlock *&FBB,
321 SmallVectorImpl<MachineOperand> &Cond) const {
322 // If the block has no terminators, it just falls into the block after it.
323 MachineBasicBlock::iterator I = MBB.end();
324 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
327 // Get the last instruction in the block.
328 MachineInstr *LastInst = I;
330 // If there is only one terminator instruction, process it.
331 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
332 if (LastInst->getOpcode() == Alpha::BR) {
333 TBB = LastInst->getOperand(0).getMBB();
335 } else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
336 LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
337 // Block ends with fall-through condbranch.
338 TBB = LastInst->getOperand(2).getMBB();
339 Cond.push_back(LastInst->getOperand(0));
340 Cond.push_back(LastInst->getOperand(1));
343 // Otherwise, don't know what this is.
347 // Get the instruction before it if it's a terminator.
348 MachineInstr *SecondLastInst = I;
350 // If there are three terminators, we don't know what sort of block this is.
351 if (SecondLastInst && I != MBB.begin() &&
352 isUnpredicatedTerminator(--I))
355 // If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.
356 if ((SecondLastInst->getOpcode() == Alpha::COND_BRANCH_I ||
357 SecondLastInst->getOpcode() == Alpha::COND_BRANCH_F) &&
358 LastInst->getOpcode() == Alpha::BR) {
359 TBB = SecondLastInst->getOperand(2).getMBB();
360 Cond.push_back(SecondLastInst->getOperand(0));
361 Cond.push_back(SecondLastInst->getOperand(1));
362 FBB = LastInst->getOperand(0).getMBB();
366 // If the block ends with two Alpha::BRs, handle it. The second one is not
367 // executed, so remove it.
368 if (SecondLastInst->getOpcode() == Alpha::BR &&
369 LastInst->getOpcode() == Alpha::BR) {
370 TBB = SecondLastInst->getOperand(0).getMBB();
372 I->eraseFromParent();
376 // Otherwise, can't handle this.
380 unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
381 MachineBasicBlock::iterator I = MBB.end();
382 if (I == MBB.begin()) return 0;
384 if (I->getOpcode() != Alpha::BR &&
385 I->getOpcode() != Alpha::COND_BRANCH_I &&
386 I->getOpcode() != Alpha::COND_BRANCH_F)
389 // Remove the branch.
390 I->eraseFromParent();
394 if (I == MBB.begin()) return 1;
396 if (I->getOpcode() != Alpha::COND_BRANCH_I &&
397 I->getOpcode() != Alpha::COND_BRANCH_F)
400 // Remove the branch.
401 I->eraseFromParent();
405 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
406 MachineBasicBlock::iterator MI) const {
407 BuildMI(MBB, MI, get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
411 bool AlphaInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
412 if (MBB.empty()) return false;
414 switch (MBB.back().getOpcode()) {
415 case Alpha::RETDAG: // Return.
417 case Alpha::BR: // Uncond branch.
418 case Alpha::JMP: // Indirect branch.
420 default: return false;
423 bool AlphaInstrInfo::
424 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
425 assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
426 Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm()));