1 //===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "AlphaInstrInfo.h"
16 #include "AlphaMachineFunctionInfo.h"
17 #include "AlphaGenInstrInfo.inc"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 AlphaInstrInfo::AlphaInstrInfo()
25 : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts)),
29 bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
30 unsigned& sourceReg, unsigned& destReg,
31 unsigned& SrcSR, unsigned& DstSR) const {
32 unsigned oc = MI.getOpcode();
33 if (oc == Alpha::BISr ||
36 oc == Alpha::CPYSSt ||
37 oc == Alpha::CPYSTs) {
40 assert(MI.getNumOperands() >= 3 &&
41 MI.getOperand(0).isReg() &&
42 MI.getOperand(1).isReg() &&
43 MI.getOperand(2).isReg() &&
44 "invalid Alpha BIS instruction!");
45 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
46 sourceReg = MI.getOperand(1).getReg();
47 destReg = MI.getOperand(0).getReg();
56 AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
57 int &FrameIndex) const {
58 switch (MI->getOpcode()) {
65 if (MI->getOperand(1).isFI()) {
66 FrameIndex = MI->getOperand(1).getIndex();
67 return MI->getOperand(0).getReg();
75 AlphaInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
76 int &FrameIndex) const {
77 switch (MI->getOpcode()) {
84 if (MI->getOperand(1).isFI()) {
85 FrameIndex = MI->getOperand(1).getIndex();
86 return MI->getOperand(0).getReg();
93 static bool isAlphaIntCondCode(unsigned Opcode) {
109 unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
110 MachineBasicBlock *TBB,
111 MachineBasicBlock *FBB,
112 const SmallVectorImpl<MachineOperand> &Cond) const {
113 // FIXME this should probably have a DebugLoc argument
114 DebugLoc dl = DebugLoc::getUnknownLoc();
115 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
116 assert((Cond.size() == 2 || Cond.size() == 0) &&
117 "Alpha branch conditions have two components!");
121 if (Cond.empty()) // Unconditional branch
122 BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(TBB);
123 else // Conditional branch
124 if (isAlphaIntCondCode(Cond[0].getImm()))
125 BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
126 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
128 BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
129 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
133 // Two-way Conditional Branch.
134 if (isAlphaIntCondCode(Cond[0].getImm()))
135 BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
136 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
138 BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
139 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
140 BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(FBB);
144 bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
145 MachineBasicBlock::iterator MI,
146 unsigned DestReg, unsigned SrcReg,
147 const TargetRegisterClass *DestRC,
148 const TargetRegisterClass *SrcRC) const {
149 //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
150 if (DestRC != SrcRC) {
151 // Not yet supported!
155 DebugLoc DL = DebugLoc::getUnknownLoc();
156 if (MI != MBB.end()) DL = MI->getDebugLoc();
158 if (DestRC == Alpha::GPRCRegisterClass) {
159 BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg)
162 } else if (DestRC == Alpha::F4RCRegisterClass) {
163 BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg)
166 } else if (DestRC == Alpha::F8RCRegisterClass) {
167 BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg)
171 // Attempt to copy register that is not GPR or FPR
179 AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
180 MachineBasicBlock::iterator MI,
181 unsigned SrcReg, bool isKill, int FrameIdx,
182 const TargetRegisterClass *RC) const {
183 //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
184 // << FrameIdx << "\n";
185 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
187 DebugLoc DL = DebugLoc::getUnknownLoc();
188 if (MI != MBB.end()) DL = MI->getDebugLoc();
190 if (RC == Alpha::F4RCRegisterClass)
191 BuildMI(MBB, MI, DL, get(Alpha::STS))
192 .addReg(SrcReg, getKillRegState(isKill))
193 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
194 else if (RC == Alpha::F8RCRegisterClass)
195 BuildMI(MBB, MI, DL, get(Alpha::STT))
196 .addReg(SrcReg, getKillRegState(isKill))
197 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
198 else if (RC == Alpha::GPRCRegisterClass)
199 BuildMI(MBB, MI, DL, get(Alpha::STQ))
200 .addReg(SrcReg, getKillRegState(isKill))
201 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
206 void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
208 SmallVectorImpl<MachineOperand> &Addr,
209 const TargetRegisterClass *RC,
210 SmallVectorImpl<MachineInstr*> &NewMIs) const {
212 if (RC == Alpha::F4RCRegisterClass)
214 else if (RC == Alpha::F8RCRegisterClass)
216 else if (RC == Alpha::GPRCRegisterClass)
220 DebugLoc DL = DebugLoc::getUnknownLoc();
221 MachineInstrBuilder MIB =
222 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
223 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
224 MIB.addOperand(Addr[i]);
225 NewMIs.push_back(MIB);
229 AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
230 MachineBasicBlock::iterator MI,
231 unsigned DestReg, int FrameIdx,
232 const TargetRegisterClass *RC) const {
233 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
234 // << FrameIdx << "\n";
235 DebugLoc DL = DebugLoc::getUnknownLoc();
236 if (MI != MBB.end()) DL = MI->getDebugLoc();
238 if (RC == Alpha::F4RCRegisterClass)
239 BuildMI(MBB, MI, DL, get(Alpha::LDS), DestReg)
240 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
241 else if (RC == Alpha::F8RCRegisterClass)
242 BuildMI(MBB, MI, DL, get(Alpha::LDT), DestReg)
243 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
244 else if (RC == Alpha::GPRCRegisterClass)
245 BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg)
246 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
251 void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
252 SmallVectorImpl<MachineOperand> &Addr,
253 const TargetRegisterClass *RC,
254 SmallVectorImpl<MachineInstr*> &NewMIs) const {
256 if (RC == Alpha::F4RCRegisterClass)
258 else if (RC == Alpha::F8RCRegisterClass)
260 else if (RC == Alpha::GPRCRegisterClass)
264 DebugLoc DL = DebugLoc::getUnknownLoc();
265 MachineInstrBuilder MIB =
266 BuildMI(MF, DL, get(Opc), DestReg);
267 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
268 MIB.addOperand(Addr[i]);
269 NewMIs.push_back(MIB);
272 MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
274 const SmallVectorImpl<unsigned> &Ops,
275 int FrameIndex) const {
276 if (Ops.size() != 1) return NULL;
278 // Make sure this is a reg-reg copy.
279 unsigned Opc = MI->getOpcode();
281 MachineInstr *NewMI = NULL;
288 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
289 if (Ops[0] == 0) { // move -> store
290 unsigned InReg = MI->getOperand(1).getReg();
291 bool isKill = MI->getOperand(1).isKill();
292 bool isUndef = MI->getOperand(1).isUndef();
293 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
294 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
295 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
296 .addReg(InReg, getKillRegState(isKill) | getUndefRegState(isUndef))
297 .addFrameIndex(FrameIndex)
299 } else { // load -> move
300 unsigned OutReg = MI->getOperand(0).getReg();
301 bool isDead = MI->getOperand(0).isDead();
302 bool isUndef = MI->getOperand(0).isUndef();
303 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
304 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
305 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
306 .addReg(OutReg, RegState::Define | getDeadRegState(isDead) |
307 getUndefRegState(isUndef))
308 .addFrameIndex(FrameIndex)
317 static unsigned AlphaRevCondCode(unsigned Opcode) {
319 case Alpha::BEQ: return Alpha::BNE;
320 case Alpha::BNE: return Alpha::BEQ;
321 case Alpha::BGE: return Alpha::BLT;
322 case Alpha::BGT: return Alpha::BLE;
323 case Alpha::BLE: return Alpha::BGT;
324 case Alpha::BLT: return Alpha::BGE;
325 case Alpha::BLBC: return Alpha::BLBS;
326 case Alpha::BLBS: return Alpha::BLBC;
327 case Alpha::FBEQ: return Alpha::FBNE;
328 case Alpha::FBNE: return Alpha::FBEQ;
329 case Alpha::FBGE: return Alpha::FBLT;
330 case Alpha::FBGT: return Alpha::FBLE;
331 case Alpha::FBLE: return Alpha::FBGT;
332 case Alpha::FBLT: return Alpha::FBGE;
334 assert(0 && "Unknown opcode");
336 return 0; // Not reached
340 bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
341 MachineBasicBlock *&FBB,
342 SmallVectorImpl<MachineOperand> &Cond,
343 bool AllowModify) const {
344 // If the block has no terminators, it just falls into the block after it.
345 MachineBasicBlock::iterator I = MBB.end();
346 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
349 // Get the last instruction in the block.
350 MachineInstr *LastInst = I;
352 // If there is only one terminator instruction, process it.
353 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
354 if (LastInst->getOpcode() == Alpha::BR) {
355 TBB = LastInst->getOperand(0).getMBB();
357 } else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
358 LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
359 // Block ends with fall-through condbranch.
360 TBB = LastInst->getOperand(2).getMBB();
361 Cond.push_back(LastInst->getOperand(0));
362 Cond.push_back(LastInst->getOperand(1));
365 // Otherwise, don't know what this is.
369 // Get the instruction before it if it's a terminator.
370 MachineInstr *SecondLastInst = I;
372 // If there are three terminators, we don't know what sort of block this is.
373 if (SecondLastInst && I != MBB.begin() &&
374 isUnpredicatedTerminator(--I))
377 // If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.
378 if ((SecondLastInst->getOpcode() == Alpha::COND_BRANCH_I ||
379 SecondLastInst->getOpcode() == Alpha::COND_BRANCH_F) &&
380 LastInst->getOpcode() == Alpha::BR) {
381 TBB = SecondLastInst->getOperand(2).getMBB();
382 Cond.push_back(SecondLastInst->getOperand(0));
383 Cond.push_back(SecondLastInst->getOperand(1));
384 FBB = LastInst->getOperand(0).getMBB();
388 // If the block ends with two Alpha::BRs, handle it. The second one is not
389 // executed, so remove it.
390 if (SecondLastInst->getOpcode() == Alpha::BR &&
391 LastInst->getOpcode() == Alpha::BR) {
392 TBB = SecondLastInst->getOperand(0).getMBB();
395 I->eraseFromParent();
399 // Otherwise, can't handle this.
403 unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
404 MachineBasicBlock::iterator I = MBB.end();
405 if (I == MBB.begin()) return 0;
407 if (I->getOpcode() != Alpha::BR &&
408 I->getOpcode() != Alpha::COND_BRANCH_I &&
409 I->getOpcode() != Alpha::COND_BRANCH_F)
412 // Remove the branch.
413 I->eraseFromParent();
417 if (I == MBB.begin()) return 1;
419 if (I->getOpcode() != Alpha::COND_BRANCH_I &&
420 I->getOpcode() != Alpha::COND_BRANCH_F)
423 // Remove the branch.
424 I->eraseFromParent();
428 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
429 MachineBasicBlock::iterator MI) const {
430 DebugLoc DL = DebugLoc::getUnknownLoc();
431 if (MI != MBB.end()) DL = MI->getDebugLoc();
432 BuildMI(MBB, MI, DL, get(Alpha::BISr), Alpha::R31)
437 bool AlphaInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
438 if (MBB.empty()) return false;
440 switch (MBB.back().getOpcode()) {
441 case Alpha::RETDAG: // Return.
443 case Alpha::BR: // Uncond branch.
444 case Alpha::JMP: // Indirect branch.
446 default: return false;
449 bool AlphaInstrInfo::
450 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
451 assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
452 Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm()));
456 /// getGlobalBaseReg - Return a virtual register initialized with the
457 /// the global base register value. Output instructions required to
458 /// initialize the register in the function entry block, if necessary.
460 unsigned AlphaInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
461 AlphaMachineFunctionInfo *AlphaFI = MF->getInfo<AlphaMachineFunctionInfo>();
462 unsigned GlobalBaseReg = AlphaFI->getGlobalBaseReg();
463 if (GlobalBaseReg != 0)
464 return GlobalBaseReg;
466 // Insert the set of GlobalBaseReg into the first MBB of the function
467 MachineBasicBlock &FirstMBB = MF->front();
468 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
469 MachineRegisterInfo &RegInfo = MF->getRegInfo();
470 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
472 GlobalBaseReg = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
473 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Alpha::R29,
474 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass);
475 assert(Ok && "Couldn't assign to global base register!");
476 RegInfo.addLiveIn(Alpha::R29);
478 AlphaFI->setGlobalBaseReg(GlobalBaseReg);
479 return GlobalBaseReg;
482 /// getGlobalRetAddr - Return a virtual register initialized with the
483 /// the global base register value. Output instructions required to
484 /// initialize the register in the function entry block, if necessary.
486 unsigned AlphaInstrInfo::getGlobalRetAddr(MachineFunction *MF) const {
487 AlphaMachineFunctionInfo *AlphaFI = MF->getInfo<AlphaMachineFunctionInfo>();
488 unsigned GlobalRetAddr = AlphaFI->getGlobalRetAddr();
489 if (GlobalRetAddr != 0)
490 return GlobalRetAddr;
492 // Insert the set of GlobalRetAddr into the first MBB of the function
493 MachineBasicBlock &FirstMBB = MF->front();
494 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
495 MachineRegisterInfo &RegInfo = MF->getRegInfo();
496 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
498 GlobalRetAddr = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
499 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalRetAddr, Alpha::R26,
500 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass);
501 assert(Ok && "Couldn't assign to global return address register!");
502 RegInfo.addLiveIn(Alpha::R26);
504 AlphaFI->setGlobalRetAddr(GlobalRetAddr);
505 return GlobalRetAddr;