1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Module.h"
24 #include "llvm/Support/CommandLine.h"
29 /// AddLiveIn - This helper function adds the specified physical register to the
30 /// MachineFunction as a live in value. It also creates a corresponding virtual
32 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
33 TargetRegisterClass *RC) {
34 assert(RC->contains(PReg) && "Not the correct regclass!");
35 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
36 MF.addLiveIn(PReg, VReg);
40 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
41 // Set up the TargetLowering object.
42 //I am having problems with shr n ubyte 1
43 setShiftAmountType(MVT::i64);
44 setSetCCResultType(MVT::i64);
45 setSetCCResultContents(ZeroOrOneSetCCResult);
47 setUsesGlobalOffsetTable(true);
49 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
50 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
51 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
53 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
54 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
56 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
57 setLoadXAction(ISD::ZEXTLOAD, MVT::i32, Expand);
59 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
60 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
61 setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand);
63 // setOperationAction(ISD::BRIND, MVT::i64, Expand);
64 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
65 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
67 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
69 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
71 setOperationAction(ISD::FREM, MVT::f32, Expand);
72 setOperationAction(ISD::FREM, MVT::f64, Expand);
74 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
75 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
76 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
77 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
79 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
80 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
81 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
82 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
84 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
85 setOperationAction(ISD::ROTL , MVT::i64, Expand);
86 setOperationAction(ISD::ROTR , MVT::i64, Expand);
88 setOperationAction(ISD::SREM , MVT::i64, Custom);
89 setOperationAction(ISD::UREM , MVT::i64, Custom);
90 setOperationAction(ISD::SDIV , MVT::i64, Custom);
91 setOperationAction(ISD::UDIV , MVT::i64, Custom);
93 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
94 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
95 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
97 // We don't support sin/cos/sqrt
98 setOperationAction(ISD::FSIN , MVT::f64, Expand);
99 setOperationAction(ISD::FCOS , MVT::f64, Expand);
100 setOperationAction(ISD::FSIN , MVT::f32, Expand);
101 setOperationAction(ISD::FCOS , MVT::f32, Expand);
103 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
104 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
106 setOperationAction(ISD::SETCC, MVT::f32, Promote);
108 // We don't have line number support yet.
109 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
110 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
111 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
113 // Not implemented yet.
114 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
115 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
116 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
118 // We want to legalize GlobalAddress and ConstantPool and
119 // ExternalSymbols nodes into the appropriate instructions to
120 // materialize the address.
121 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
122 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
123 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
125 setOperationAction(ISD::VASTART, MVT::Other, Custom);
126 setOperationAction(ISD::VAEND, MVT::Other, Expand);
127 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
128 setOperationAction(ISD::VAARG, MVT::Other, Custom);
129 setOperationAction(ISD::VAARG, MVT::i32, Custom);
131 setOperationAction(ISD::RET, MVT::Other, Custom);
133 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
134 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
135 setOperationAction(ISD::JumpTableRelocBase, MVT::i64, Custom);
137 setStackPointerRegisterToSaveRestore(Alpha::R30);
139 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
140 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
141 addLegalFPImmediate(+0.0); //F31
142 addLegalFPImmediate(-0.0); //-F31
145 setJumpBufAlignment(16);
147 computeRegisterProperties();
149 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
152 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
155 case AlphaISD::ITOFT_: return "Alpha::ITOFT_";
156 case AlphaISD::FTOIT_: return "Alpha::FTOIT_";
157 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
158 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
159 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
160 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
161 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
162 case AlphaISD::RelLit: return "Alpha::RelLit";
163 case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
164 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
165 case AlphaISD::CALL: return "Alpha::CALL";
166 case AlphaISD::DivCall: return "Alpha::DivCall";
167 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
171 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
172 MVT::ValueType PtrVT = Op.getValueType();
173 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
174 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
175 SDOperand Zero = DAG.getConstant(0, PtrVT);
177 const TargetMachine &TM = DAG.getTarget();
179 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
180 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
181 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
185 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
186 //AA-PY8AC-TET1_html/callCH3.html#BLOCK21
188 //For now, just use variable size stack frame format
190 //In a standard call, the first six items are passed in registers $16
191 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
192 //of argument-to-register correspondence.) The remaining items are
193 //collected in a memory argument list that is a naturally aligned
194 //array of quadwords. In a standard call, this list, if present, must
195 //be passed at 0(SP).
196 //7 ... n 0(SP) ... (n-7)*8(SP)
204 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
209 MachineFunction &MF = DAG.getMachineFunction();
210 MachineFrameInfo *MFI = MF.getFrameInfo();
211 SSARegMap *RegMap = MF.getSSARegMap();
212 std::vector<SDOperand> ArgValues;
213 SDOperand Root = Op.getOperand(0);
215 GP = AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass);
216 RA = AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass);
218 unsigned args_int[] = {
219 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
220 unsigned args_float[] = {
221 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
223 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
225 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
232 std::cerr << "Unknown Type " << ObjectVT << "\n";
235 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
236 &Alpha::F8RCRegClass);
237 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
240 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
241 &Alpha::F4RCRegClass);
242 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
245 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
246 &Alpha::GPRCRegClass);
247 ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
251 // Create the frame index object for this incoming parameter...
252 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
254 // Create the SelectionDAG nodes corresponding to a load
255 //from this parameter
256 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
257 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, DAG.getSrcValue(NULL));
259 ArgValues.push_back(ArgVal);
262 // If the functions takes variable number of arguments, copy all regs to stack
263 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
265 VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
266 std::vector<SDOperand> LS;
267 for (int i = 0; i < 6; ++i) {
268 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
269 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
270 SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
271 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
272 if (i == 0) VarArgsBase = FI;
273 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
274 LS.push_back(DAG.getStore(Root, argt, SDFI, DAG.getSrcValue(NULL)));
276 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
277 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
278 argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
279 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
280 SDFI = DAG.getFrameIndex(FI, MVT::i64);
281 LS.push_back(DAG.getStore(Root, argt, SDFI, DAG.getSrcValue(NULL)));
284 //Set up a token factor with all the stack traffic
285 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size());
288 ArgValues.push_back(Root);
290 // Return the new list of results.
291 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
292 Op.Val->value_end());
293 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
296 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, unsigned int RA) {
297 SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
298 DAG.getNode(AlphaISD::GlobalRetAddr,
301 switch (Op.getNumOperands()) {
303 assert(0 && "Do not know how to return this many arguments!");
307 //return SDOperand(); // ret void is legal
309 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
311 if (MVT::isInteger(ArgVT))
314 assert(MVT::isFloatingPoint(ArgVT));
317 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
318 if(DAG.getMachineFunction().liveout_empty())
319 DAG.getMachineFunction().addLiveOut(ArgReg);
323 return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
326 std::pair<SDOperand, SDOperand>
327 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
328 const Type *RetTy, bool isVarArg,
329 unsigned CallingConv, bool isTailCall,
330 SDOperand Callee, ArgListTy &Args,
334 NumBytes = (Args.size() - 6) * 8;
336 Chain = DAG.getCALLSEQ_START(Chain,
337 DAG.getConstant(NumBytes, getPointerTy()));
338 std::vector<SDOperand> args_to_use;
339 for (unsigned i = 0, e = Args.size(); i != e; ++i)
341 switch (getValueType(Args[i].second)) {
342 default: assert(0 && "Unexpected ValueType for argument!");
347 // Promote the integer to 64 bits. If the input type is signed use a
348 // sign extend, otherwise use a zero extend.
349 if (Args[i].second->isSigned())
350 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
352 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
359 args_to_use.push_back(Args[i].first);
362 std::vector<MVT::ValueType> RetVals;
363 MVT::ValueType RetTyVT = getValueType(RetTy);
364 MVT::ValueType ActualRetTyVT = RetTyVT;
365 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
366 ActualRetTyVT = MVT::i64;
368 if (RetTyVT != MVT::isVoid)
369 RetVals.push_back(ActualRetTyVT);
370 RetVals.push_back(MVT::Other);
372 std::vector<SDOperand> Ops;
373 Ops.push_back(Chain);
374 Ops.push_back(Callee);
375 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
376 SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
377 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
378 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
379 DAG.getConstant(NumBytes, getPointerTy()));
380 SDOperand RetVal = TheCall;
382 if (RetTyVT != ActualRetTyVT) {
383 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
384 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
385 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
388 return std::make_pair(RetVal, Chain);
391 void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
393 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
395 void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
397 BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
406 /// LowerOperation - Provide custom lowering hooks for some operations.
408 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
409 switch (Op.getOpcode()) {
410 default: assert(0 && "Wasn't expecting to be able to lower this!");
411 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
415 case ISD::RET: return LowerRET(Op,DAG, getVRegRA());
416 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
417 case ISD::JumpTableRelocBase:
418 return DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64);
420 case ISD::SINT_TO_FP: {
421 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
422 "Unhandled SINT_TO_FP type in custom expander!");
424 bool isDouble = MVT::f64 == Op.getValueType();
426 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
429 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
430 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
431 SDOperand ST = DAG.getStore(DAG.getEntryNode(),
432 Op.getOperand(0), FI, DAG.getSrcValue(0));
433 LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
435 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
436 isDouble?MVT::f64:MVT::f32, LD);
439 case ISD::FP_TO_SINT: {
440 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
441 SDOperand src = Op.getOperand(0);
443 if (!isDouble) //Promote
444 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
446 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
449 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
452 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
453 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
454 SDOperand ST = DAG.getStore(DAG.getEntryNode(),
455 src, FI, DAG.getSrcValue(0));
456 return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
459 case ISD::ConstantPool: {
460 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
461 Constant *C = CP->getConstVal();
462 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
464 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
465 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
466 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
469 case ISD::GlobalAddress: {
470 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
471 GlobalValue *GV = GSDN->getGlobal();
472 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
474 // if (!GV->hasWeakLinkage() && !GV->isExternal() && !GV->hasLinkOnceLinkage()) {
475 if (GV->hasInternalLinkage()) {
476 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
477 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
478 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
481 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
483 case ISD::ExternalSymbol: {
484 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
485 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64),
486 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
491 //Expand only on constant case
492 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
493 MVT::ValueType VT = Op.Val->getValueType(0);
494 unsigned Opc = Op.Val->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
495 SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
496 BuildUDIV(Op.Val, DAG, NULL) :
497 BuildSDIV(Op.Val, DAG, NULL);
498 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
499 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
505 if (MVT::isInteger(Op.getValueType())) {
506 if (Op.getOperand(1).getOpcode() == ISD::Constant)
507 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
508 : BuildUDIV(Op.Val, DAG, NULL);
509 const char* opstr = 0;
510 switch(Op.getOpcode()) {
511 case ISD::UREM: opstr = "__remqu"; break;
512 case ISD::SREM: opstr = "__remq"; break;
513 case ISD::UDIV: opstr = "__divqu"; break;
514 case ISD::SDIV: opstr = "__divq"; break;
516 SDOperand Tmp1 = Op.getOperand(0),
517 Tmp2 = Op.getOperand(1),
518 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
519 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
524 SDOperand Chain = Op.getOperand(0);
525 SDOperand VAListP = Op.getOperand(1);
526 SDOperand VAListS = Op.getOperand(2);
528 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS);
529 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
530 DAG.getConstant(8, MVT::i64));
531 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
532 Tmp, DAG.getSrcValue(0), MVT::i32);
533 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
534 if (MVT::isFloatingPoint(Op.getValueType()))
536 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
537 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
538 DAG.getConstant(8*6, MVT::i64));
539 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
540 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
541 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
544 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
545 DAG.getConstant(8, MVT::i64));
546 SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
547 Offset.getValue(1), NewOffset,
548 Tmp, DAG.getSrcValue(0),
549 DAG.getValueType(MVT::i32));
552 if (Op.getValueType() == MVT::i32)
553 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
554 DAG.getSrcValue(0), MVT::i32);
556 Result = DAG.getLoad(Op.getValueType(), Update, DataPtr,
561 SDOperand Chain = Op.getOperand(0);
562 SDOperand DestP = Op.getOperand(1);
563 SDOperand SrcP = Op.getOperand(2);
564 SDOperand DestS = Op.getOperand(3);
565 SDOperand SrcS = Op.getOperand(4);
567 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS);
568 SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS);
569 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
570 DAG.getConstant(8, MVT::i64));
571 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
572 DAG.getSrcValue(0), MVT::i32);
573 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
574 DAG.getConstant(8, MVT::i64));
575 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
576 Val, NPD, DAG.getSrcValue(0),DAG.getValueType(MVT::i32));
579 SDOperand Chain = Op.getOperand(0);
580 SDOperand VAListP = Op.getOperand(1);
581 SDOperand VAListS = Op.getOperand(2);
583 // vastart stores the address of the VarArgsBase and VarArgsOffset
584 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
585 SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS);
586 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
587 DAG.getConstant(8, MVT::i64));
588 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
589 DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
590 DAG.getSrcValue(0), DAG.getValueType(MVT::i32));
597 SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
599 assert(Op.getValueType() == MVT::i32 &&
600 Op.getOpcode() == ISD::VAARG &&
601 "Unknown node to custom promote!");
603 // The code in LowerOperation already handles i32 vaarg
604 return LowerOperation(Op, DAG);
610 /// getConstraintType - Given a constraint letter, return the type of
611 /// constraint it is for this target.
612 AlphaTargetLowering::ConstraintType
613 AlphaTargetLowering::getConstraintType(char ConstraintLetter) const {
614 switch (ConstraintLetter) {
618 return C_RegisterClass;
620 return TargetLowering::getConstraintType(ConstraintLetter);
623 std::vector<unsigned> AlphaTargetLowering::
624 getRegClassForInlineAsmConstraint(const std::string &Constraint,
625 MVT::ValueType VT) const {
626 if (Constraint.size() == 1) {
627 switch (Constraint[0]) {
628 default: break; // Unknown constriant letter
630 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
631 Alpha::F3 , Alpha::F4 , Alpha::F5 ,
632 Alpha::F6 , Alpha::F7 , Alpha::F8 ,
633 Alpha::F9 , Alpha::F10, Alpha::F11,
634 Alpha::F12, Alpha::F13, Alpha::F14,
635 Alpha::F15, Alpha::F16, Alpha::F17,
636 Alpha::F18, Alpha::F19, Alpha::F20,
637 Alpha::F21, Alpha::F22, Alpha::F23,
638 Alpha::F24, Alpha::F25, Alpha::F26,
639 Alpha::F27, Alpha::F28, Alpha::F29,
640 Alpha::F30, Alpha::F31, 0);
642 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
643 Alpha::R3 , Alpha::R4 , Alpha::R5 ,
644 Alpha::R6 , Alpha::R7 , Alpha::R8 ,
645 Alpha::R9 , Alpha::R10, Alpha::R11,
646 Alpha::R12, Alpha::R13, Alpha::R14,
647 Alpha::R15, Alpha::R16, Alpha::R17,
648 Alpha::R18, Alpha::R19, Alpha::R20,
649 Alpha::R21, Alpha::R22, Alpha::R23,
650 Alpha::R24, Alpha::R25, Alpha::R26,
651 Alpha::R27, Alpha::R28, Alpha::R29,
652 Alpha::R30, Alpha::R31, 0);
657 return std::vector<unsigned>();