1 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AlphaISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AlphaISelLowering.h"
15 #include "AlphaTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Module.h"
24 #include "llvm/Support/CommandLine.h"
29 /// AddLiveIn - This helper function adds the specified physical register to the
30 /// MachineFunction as a live in value. It also creates a corresponding virtual
32 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
33 TargetRegisterClass *RC) {
34 assert(RC->contains(PReg) && "Not the correct regclass!");
35 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
36 MF.addLiveIn(PReg, VReg);
40 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
41 // Set up the TargetLowering object.
42 //I am having problems with shr n ubyte 1
43 setShiftAmountType(MVT::i64);
44 setSetCCResultType(MVT::i64);
45 setSetCCResultContents(ZeroOrOneSetCCResult);
47 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
48 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
49 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
51 setOperationAction(ISD::BRIND, MVT::i64, Expand);
52 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
53 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
55 setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
56 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
58 setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote);
59 setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
61 setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote);
62 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
63 setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
65 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
67 setOperationAction(ISD::FREM, MVT::f32, Expand);
68 setOperationAction(ISD::FREM, MVT::f64, Expand);
70 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
71 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
72 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
73 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
75 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
76 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
77 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
78 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
80 setOperationAction(ISD::BSWAP , MVT::i64, Expand);
81 setOperationAction(ISD::ROTL , MVT::i64, Expand);
82 setOperationAction(ISD::ROTR , MVT::i64, Expand);
84 setOperationAction(ISD::SREM , MVT::i64, Custom);
85 setOperationAction(ISD::UREM , MVT::i64, Custom);
86 setOperationAction(ISD::SDIV , MVT::i64, Custom);
87 setOperationAction(ISD::UDIV , MVT::i64, Custom);
89 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
90 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
91 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
93 // We don't support sin/cos/sqrt
94 setOperationAction(ISD::FSIN , MVT::f64, Expand);
95 setOperationAction(ISD::FCOS , MVT::f64, Expand);
96 setOperationAction(ISD::FSIN , MVT::f32, Expand);
97 setOperationAction(ISD::FCOS , MVT::f32, Expand);
99 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
100 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
102 // FIXME: Alpha supports fcopysign natively!?
103 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
104 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
106 setOperationAction(ISD::SETCC, MVT::f32, Promote);
108 // We don't have line number support yet.
109 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
110 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
111 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
113 // Not implemented yet.
114 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
115 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
116 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
118 // We want to legalize GlobalAddress and ConstantPool and
119 // ExternalSymbols nodes into the appropriate instructions to
120 // materialize the address.
121 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
122 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
123 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
125 setOperationAction(ISD::VASTART, MVT::Other, Custom);
126 setOperationAction(ISD::VAEND, MVT::Other, Expand);
127 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
128 setOperationAction(ISD::VAARG, MVT::Other, Custom);
129 setOperationAction(ISD::VAARG, MVT::i32, Custom);
131 setStackPointerRegisterToSaveRestore(Alpha::R30);
133 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
134 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
135 addLegalFPImmediate(+0.0); //F31
136 addLegalFPImmediate(-0.0); //-F31
138 computeRegisterProperties();
140 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
143 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
146 case AlphaISD::ITOFT_: return "Alpha::ITOFT_";
147 case AlphaISD::FTOIT_: return "Alpha::FTOIT_";
148 case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
149 case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
150 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
151 case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
152 case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
153 case AlphaISD::RelLit: return "Alpha::RelLit";
154 case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
155 case AlphaISD::CALL: return "Alpha::CALL";
156 case AlphaISD::DivCall: return "Alpha::DivCall";
160 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
162 //For now, just use variable size stack frame format
164 //In a standard call, the first six items are passed in registers $16
165 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
166 //of argument-to-register correspondence.) The remaining items are
167 //collected in a memory argument list that is a naturally aligned
168 //array of quadwords. In a standard call, this list, if present, must
169 //be passed at 0(SP).
170 //7 ... n 0(SP) ... (n-7)*8(SP)
178 std::vector<SDOperand>
179 AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
181 MachineFunction &MF = DAG.getMachineFunction();
182 MachineFrameInfo *MFI = MF.getFrameInfo();
183 std::vector<SDOperand> ArgValues;
185 unsigned args_int[] = {
186 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
187 unsigned args_float[] = {
188 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
192 GP = AddLiveIn(MF, Alpha::R29, getRegClassFor(MVT::i64));
193 RA = AddLiveIn(MF, Alpha::R26, getRegClassFor(MVT::i64));
195 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
200 MVT::ValueType VT = getValueType(I->getType());
203 std::cerr << "Unknown Type " << VT << "\n";
207 args_float[count] = AddLiveIn(MF, args_float[count], getRegClassFor(VT));
208 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
209 DAG.setRoot(argt.getValue(1));
216 args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64));
217 argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
218 DAG.setRoot(argt.getValue(1));
219 if (VT != MVT::i64) {
221 I->getType()->isSigned() ? ISD::AssertSext : ISD::AssertZext;
222 argt = DAG.getNode(AssertOp, MVT::i64, argt,
223 DAG.getValueType(VT));
224 argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
229 // Create the frame index object for this incoming parameter...
230 int FI = MFI->CreateFixedObject(8, 8 * (count - 6));
232 // Create the SelectionDAG nodes corresponding to a load
233 //from this parameter
234 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
235 argt = DAG.getLoad(getValueType(I->getType()),
236 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
239 ArgValues.push_back(argt);
242 // If the functions takes variable number of arguments, copy all regs to stack
244 VarArgsOffset = count * 8;
245 std::vector<SDOperand> LS;
246 for (int i = 0; i < 6; ++i) {
247 if (MRegisterInfo::isPhysicalRegister(args_int[i]))
248 args_int[i] = AddLiveIn(MF, args_int[i], getRegClassFor(MVT::i64));
249 SDOperand argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[i], MVT::i64);
250 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
251 if (i == 0) VarArgsBase = FI;
252 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
253 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
254 SDFI, DAG.getSrcValue(NULL)));
256 if (MRegisterInfo::isPhysicalRegister(args_float[i]))
257 args_float[i] = AddLiveIn(MF, args_float[i], getRegClassFor(MVT::f64));
258 argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[i], MVT::f64);
259 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
260 SDFI = DAG.getFrameIndex(FI, MVT::i64);
261 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
262 SDFI, DAG.getSrcValue(NULL)));
265 //Set up a token factor with all the stack traffic
266 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, LS));
269 // Finally, inform the code generator which regs we return values in.
270 switch (getValueType(F.getReturnType())) {
271 default: assert(0 && "Unknown type!");
272 case MVT::isVoid: break;
278 MF.addLiveOut(Alpha::R0);
282 MF.addLiveOut(Alpha::F0);
286 //return the arguments+
290 std::pair<SDOperand, SDOperand>
291 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
292 const Type *RetTy, bool isVarArg,
293 unsigned CallingConv, bool isTailCall,
294 SDOperand Callee, ArgListTy &Args,
298 NumBytes = (Args.size() - 6) * 8;
300 Chain = DAG.getCALLSEQ_START(Chain,
301 DAG.getConstant(NumBytes, getPointerTy()));
302 std::vector<SDOperand> args_to_use;
303 for (unsigned i = 0, e = Args.size(); i != e; ++i)
305 switch (getValueType(Args[i].second)) {
306 default: assert(0 && "Unexpected ValueType for argument!");
311 // Promote the integer to 64 bits. If the input type is signed use a
312 // sign extend, otherwise use a zero extend.
313 if (Args[i].second->isSigned())
314 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
316 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
323 args_to_use.push_back(Args[i].first);
326 std::vector<MVT::ValueType> RetVals;
327 MVT::ValueType RetTyVT = getValueType(RetTy);
328 MVT::ValueType ActualRetTyVT = RetTyVT;
329 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
330 ActualRetTyVT = MVT::i64;
332 if (RetTyVT != MVT::isVoid)
333 RetVals.push_back(ActualRetTyVT);
334 RetVals.push_back(MVT::Other);
336 std::vector<SDOperand> Ops;
337 Ops.push_back(Chain);
338 Ops.push_back(Callee);
339 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
340 SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, Ops);
341 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
342 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
343 DAG.getConstant(NumBytes, getPointerTy()));
344 SDOperand RetVal = TheCall;
346 if (RetTyVT != ActualRetTyVT) {
347 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
348 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
349 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
352 return std::make_pair(RetVal, Chain);
355 void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
357 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
359 void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
361 BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
370 /// LowerOperation - Provide custom lowering hooks for some operations.
372 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
373 switch (Op.getOpcode()) {
374 default: assert(0 && "Wasn't expecting to be able to lower this!");
375 case ISD::SINT_TO_FP: {
376 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
377 "Unhandled SINT_TO_FP type in custom expander!");
379 bool isDouble = MVT::f64 == Op.getValueType();
381 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
384 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
385 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
386 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
387 Op.getOperand(0), FI, DAG.getSrcValue(0));
388 LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
390 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
391 isDouble?MVT::f64:MVT::f32, LD);
394 case ISD::FP_TO_SINT: {
395 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
396 SDOperand src = Op.getOperand(0);
398 if (!isDouble) //Promote
399 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
401 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
404 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
407 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
408 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
409 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
410 src, FI, DAG.getSrcValue(0));
411 return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
414 case ISD::ConstantPool: {
415 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
416 Constant *C = CP->get();
417 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
419 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
420 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
421 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
424 case ISD::GlobalAddress: {
425 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
426 GlobalValue *GV = GSDN->getGlobal();
427 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
429 // if (!GV->hasWeakLinkage() && !GV->isExternal() && !GV->hasLinkOnceLinkage()) {
430 if (GV->hasInternalLinkage()) {
431 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
432 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
433 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
436 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
438 case ISD::ExternalSymbol: {
439 return DAG.getNode(AlphaISD::RelLit, MVT::i64,
440 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64),
441 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
446 //Expand only on constant case
447 if (Op.getOperand(1).getOpcode() == ISD::Constant) {
448 MVT::ValueType VT = Op.Val->getValueType(0);
449 unsigned Opc = Op.Val->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
450 SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
451 BuildUDIV(Op.Val, DAG, NULL) :
452 BuildSDIV(Op.Val, DAG, NULL);
453 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
454 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
460 if (MVT::isInteger(Op.getValueType())) {
461 if (Op.getOperand(1).getOpcode() == ISD::Constant)
462 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
463 : BuildUDIV(Op.Val, DAG, NULL);
464 const char* opstr = 0;
465 switch(Op.getOpcode()) {
466 case ISD::UREM: opstr = "__remqu"; break;
467 case ISD::SREM: opstr = "__remq"; break;
468 case ISD::UDIV: opstr = "__divqu"; break;
469 case ISD::SDIV: opstr = "__divq"; break;
471 SDOperand Tmp1 = Op.getOperand(0),
472 Tmp2 = Op.getOperand(1),
473 Addr = DAG.getExternalSymbol(opstr, MVT::i64);
474 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
479 SDOperand Chain = Op.getOperand(0);
480 SDOperand VAListP = Op.getOperand(1);
481 SDOperand VAListS = Op.getOperand(2);
483 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS);
484 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
485 DAG.getConstant(8, MVT::i64));
486 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
487 Tmp, DAG.getSrcValue(0), MVT::i32);
488 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
489 if (MVT::isFloatingPoint(Op.getValueType()))
491 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
492 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
493 DAG.getConstant(8*6, MVT::i64));
494 SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
495 DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
496 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
499 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
500 DAG.getConstant(8, MVT::i64));
501 SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
502 Offset.getValue(1), NewOffset,
503 Tmp, DAG.getSrcValue(0),
504 DAG.getValueType(MVT::i32));
507 if (Op.getValueType() == MVT::i32)
508 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
509 DAG.getSrcValue(0), MVT::i32);
511 Result = DAG.getLoad(Op.getValueType(), Update, DataPtr,
516 SDOperand Chain = Op.getOperand(0);
517 SDOperand DestP = Op.getOperand(1);
518 SDOperand SrcP = Op.getOperand(2);
519 SDOperand DestS = Op.getOperand(3);
520 SDOperand SrcS = Op.getOperand(4);
522 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS);
523 SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), Val,
525 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
526 DAG.getConstant(8, MVT::i64));
527 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
528 DAG.getSrcValue(0), MVT::i32);
529 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
530 DAG.getConstant(8, MVT::i64));
531 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
532 Val, NPD, DAG.getSrcValue(0),DAG.getValueType(MVT::i32));
535 SDOperand Chain = Op.getOperand(0);
536 SDOperand VAListP = Op.getOperand(1);
537 SDOperand VAListS = Op.getOperand(2);
539 // vastart stores the address of the VarArgsBase and VarArgsOffset
540 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
541 SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
543 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
544 DAG.getConstant(8, MVT::i64));
545 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
546 DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
547 DAG.getSrcValue(0), DAG.getValueType(MVT::i32));
554 SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
556 assert(Op.getValueType() == MVT::i32 &&
557 Op.getOpcode() == ISD::VAARG &&
558 "Unknown node to custom promote!");
560 // The code in LowerOperation already handles i32 vaarg
561 return LowerOperation(Op, DAG);