1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/Constants.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
39 //===--------------------------------------------------------------------===//
40 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
41 /// instructions for SelectionDAG operations.
42 class AlphaDAGToDAGISel : public SelectionDAGISel {
43 static const int64_t IMM_LOW = -32768;
44 static const int64_t IMM_HIGH = 32767;
45 static const int64_t IMM_MULT = 65536;
46 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
47 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
49 static int64_t get_ldah16(int64_t x) {
50 int64_t y = x / IMM_MULT;
51 if (x % IMM_MULT > IMM_HIGH)
56 static int64_t get_lda16(int64_t x) {
57 return x - get_ldah16(x) * IMM_MULT;
60 /// get_zapImm - Return a zap mask if X is a valid immediate for a zapnot
61 /// instruction (if not, return 0). Note that this code accepts partial
62 /// zap masks. For example (and LHS, 1) is a valid zap, as long we know
63 /// that the bits 1-7 of LHS are already zero. If LHS is non-null, we are
64 /// in checking mode. If LHS is null, we assume that the mask has already
65 /// been validated before.
66 uint64_t get_zapImm(SDValue LHS, uint64_t Constant) const {
67 uint64_t BitsToCheck = 0;
69 for (unsigned i = 0; i != 8; ++i) {
70 if (((Constant >> 8*i) & 0xFF) == 0) {
74 if (((Constant >> 8*i) & 0xFF) == 0xFF) {
75 // If the entire byte is set, zapnot the byte.
76 } else if (LHS.getNode() == 0) {
77 // Otherwise, if the mask was previously validated, we know its okay
78 // to zapnot this entire byte even though all the bits aren't set.
80 // Otherwise we don't know that the it's okay to zapnot this entire
81 // byte. Only do this iff we can prove that the missing bits are
82 // already null, so the bytezap doesn't need to really null them.
83 BitsToCheck |= ~Constant & (0xFF << 8*i);
88 // If there are missing bits in a byte (for example, X & 0xEF00), check to
89 // see if the missing bits (0x1000) are already known zero if not, the zap
90 // isn't okay to do, as it won't clear all the required bits.
92 !CurDAG->MaskedValueIsZero(LHS,
93 APInt(LHS.getValueSizeInBits(),
100 static uint64_t get_zapImm(uint64_t x) {
102 for(int i = 0; i != 8; ++i) {
103 if ((x & 0x00FF) == 0x00FF)
105 else if ((x & 0x00FF) != 0)
113 static uint64_t getNearPower2(uint64_t x) {
115 unsigned at = CountLeadingZeros_64(x);
116 uint64_t complow = 1ULL << (63 - at);
117 uint64_t comphigh = 1ULL << (64 - at);
118 //cerr << x << ":" << complow << ":" << comphigh << "\n";
119 if (abs64(complow - x) <= abs64(comphigh - x))
125 static bool chkRemNearPower2(uint64_t x, uint64_t r, bool swap) {
126 uint64_t y = getNearPower2(x);
133 static bool isFPZ(SDValue N) {
134 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
135 return (CN && (CN->getValueAPF().isZero()));
137 static bool isFPZn(SDValue N) {
138 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
139 return (CN && CN->getValueAPF().isNegZero());
141 static bool isFPZp(SDValue N) {
142 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
143 return (CN && CN->getValueAPF().isPosZero());
147 explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
148 : SelectionDAGISel(TM)
151 /// getI64Imm - Return a target constant with the specified value, of type
153 inline SDValue getI64Imm(int64_t Imm) {
154 return CurDAG->getTargetConstant(Imm, MVT::i64);
157 // Select - Convert the specified operand from a target-independent to a
158 // target-specific node if it hasn't already been changed.
159 SDNode *Select(SDNode *N);
161 virtual const char *getPassName() const {
162 return "Alpha DAG->DAG Pattern Instruction Selection";
165 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
166 /// inline asm expressions.
167 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
169 std::vector<SDValue> &OutOps) {
171 switch (ConstraintCode) {
172 default: return true;
178 OutOps.push_back(Op0);
182 // Include the pieces autogenerated from the target description.
183 #include "AlphaGenDAGISel.inc"
186 /// getTargetMachine - Return a reference to the TargetMachine, casted
187 /// to the target-specific type.
188 const AlphaTargetMachine &getTargetMachine() {
189 return static_cast<const AlphaTargetMachine &>(TM);
192 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
193 /// to the target-specific type.
194 const AlphaInstrInfo *getInstrInfo() {
195 return getTargetMachine().getInstrInfo();
198 SDNode *getGlobalBaseReg();
199 SDNode *getGlobalRetAddr();
200 void SelectCALL(SDNode *Op);
205 /// getGlobalBaseReg - Output the instructions required to put the
206 /// GOT address into a register.
208 SDNode *AlphaDAGToDAGISel::getGlobalBaseReg() {
209 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
210 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
213 /// getGlobalRetAddr - Grab the return address.
215 SDNode *AlphaDAGToDAGISel::getGlobalRetAddr() {
216 unsigned GlobalRetAddr = getInstrInfo()->getGlobalRetAddr(MF);
217 return CurDAG->getRegister(GlobalRetAddr, TLI.getPointerTy()).getNode();
220 // Select - Convert the specified operand from a target-independent to a
221 // target-specific node if it hasn't already been changed.
222 SDNode *AlphaDAGToDAGISel::Select(SDNode *N) {
223 if (N->isMachineOpcode())
224 return NULL; // Already selected.
225 DebugLoc dl = N->getDebugLoc();
227 switch (N->getOpcode()) {
233 case ISD::FrameIndex: {
234 int FI = cast<FrameIndexSDNode>(N)->getIndex();
235 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
236 CurDAG->getTargetFrameIndex(FI, MVT::i32),
239 case ISD::GLOBAL_OFFSET_TABLE:
240 return getGlobalBaseReg();
241 case AlphaISD::GlobalRetAddr:
242 return getGlobalRetAddr();
244 case AlphaISD::DivCall: {
245 SDValue Chain = CurDAG->getEntryNode();
246 SDValue N0 = N->getOperand(0);
247 SDValue N1 = N->getOperand(1);
248 SDValue N2 = N->getOperand(2);
249 Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R24, N1,
251 Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R25, N2,
253 Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0,
256 CurDAG->getMachineNode(Alpha::JSRs, dl, MVT::Other, MVT::Flag,
257 Chain, Chain.getValue(1));
258 Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64,
260 return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
263 case ISD::READCYCLECOUNTER: {
264 SDValue Chain = N->getOperand(0);
265 return CurDAG->getMachineNode(Alpha::RPCC, dl, MVT::i64, MVT::Other,
269 case ISD::Constant: {
270 uint64_t uval = cast<ConstantSDNode>(N)->getZExtValue();
273 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
274 Alpha::R31, MVT::i64);
275 ReplaceUses(SDValue(N, 0), Result);
279 int64_t val = (int64_t)uval;
280 int32_t val32 = (int32_t)val;
281 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
282 val >= IMM_LOW + IMM_LOW * IMM_MULT)
283 break; //(LDAH (LDA))
284 if ((uval >> 32) == 0 && //empty upper bits
285 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
286 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
287 break; //(zext (LDAH (LDA)))
288 //Else use the constant pool
289 ConstantInt *C = ConstantInt::get(
290 Type::getInt64Ty(*CurDAG->getContext()), uval);
291 SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
292 SDNode *Tmp = CurDAG->getMachineNode(Alpha::LDAHr, dl, MVT::i64, CPI,
293 SDValue(getGlobalBaseReg(), 0));
294 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
295 CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
297 case ISD::TargetConstantFP:
298 case ISD::ConstantFP: {
299 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
300 bool isDouble = N->getValueType(0) == MVT::f64;
301 EVT T = isDouble ? MVT::f64 : MVT::f32;
302 if (CN->getValueAPF().isPosZero()) {
303 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
304 T, CurDAG->getRegister(Alpha::F31, T),
305 CurDAG->getRegister(Alpha::F31, T));
306 } else if (CN->getValueAPF().isNegZero()) {
307 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
308 T, CurDAG->getRegister(Alpha::F31, T),
309 CurDAG->getRegister(Alpha::F31, T));
311 report_fatal_error("Unhandled FP constant type");
317 if (N->getOperand(0).getNode()->getValueType(0).isFloatingPoint()) {
318 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
320 unsigned Opc = Alpha::WTF;
324 default: DEBUG(N->dump(CurDAG)); llvm_unreachable("Unknown FP comparison!");
325 case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
326 Opc = Alpha::CMPTEQ; break;
327 case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
328 Opc = Alpha::CMPTLT; break;
329 case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE:
330 Opc = Alpha::CMPTLE; break;
331 case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT:
332 Opc = Alpha::CMPTLT; rev = true; break;
333 case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE:
334 Opc = Alpha::CMPTLE; rev = true; break;
335 case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE:
336 Opc = Alpha::CMPTEQ; inv = true; break;
338 Opc = Alpha::CMPTUN; inv = true; break;
340 Opc = Alpha::CMPTUN; break;
342 SDValue tmp1 = N->getOperand(rev?1:0);
343 SDValue tmp2 = N->getOperand(rev?0:1);
344 SDNode *cmp = CurDAG->getMachineNode(Opc, dl, MVT::f64, tmp1, tmp2);
346 cmp = CurDAG->getMachineNode(Alpha::CMPTEQ, dl,
347 MVT::f64, SDValue(cmp, 0),
348 CurDAG->getRegister(Alpha::F31, MVT::f64));
350 case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
351 case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
353 SDNode* cmp2 = CurDAG->getMachineNode(Alpha::CMPTUN, dl, MVT::f64,
355 cmp = CurDAG->getMachineNode(Alpha::ADDT, dl, MVT::f64,
356 SDValue(cmp2, 0), SDValue(cmp, 0));
362 SDNode* LD = CurDAG->getMachineNode(Alpha::FTOIT, dl,
363 MVT::i64, SDValue(cmp, 0));
364 return CurDAG->getMachineNode(Alpha::CMPULT, dl, MVT::i64,
365 CurDAG->getRegister(Alpha::R31, MVT::i64),
371 ConstantSDNode* SC = NULL;
372 ConstantSDNode* MC = NULL;
373 if (N->getOperand(0).getOpcode() == ISD::SRL &&
374 (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
375 (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) {
376 uint64_t sval = SC->getZExtValue();
377 uint64_t mval = MC->getZExtValue();
378 // If the result is a zap, let the autogened stuff handle it.
379 if (get_zapImm(N->getOperand(0), mval))
381 // given mask X, and shift S, we want to see if there is any zap in the
382 // mask if we play around with the botton S bits
383 uint64_t dontcare = (~0ULL) >> (64 - sval);
384 uint64_t mask = mval << sval;
386 if (get_zapImm(mask | dontcare))
387 mask = mask | dontcare;
389 if (get_zapImm(mask)) {
391 SDValue(CurDAG->getMachineNode(Alpha::ZAPNOTi, dl, MVT::i64,
392 N->getOperand(0).getOperand(0),
393 getI64Imm(get_zapImm(mask))), 0);
394 return CurDAG->getMachineNode(Alpha::SRLr, dl, MVT::i64, Z,
403 return SelectCode(N);
406 void AlphaDAGToDAGISel::SelectCALL(SDNode *N) {
407 //TODO: add flag stuff to prevent nondeturministic breakage!
409 SDValue Chain = N->getOperand(0);
410 SDValue Addr = N->getOperand(1);
411 SDValue InFlag = N->getOperand(N->getNumOperands() - 1);
412 DebugLoc dl = N->getDebugLoc();
414 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
415 SDValue GOT = SDValue(getGlobalBaseReg(), 0);
416 Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag);
417 InFlag = Chain.getValue(1);
418 Chain = SDValue(CurDAG->getMachineNode(Alpha::BSR, dl, MVT::Other,
419 MVT::Flag, Addr.getOperand(0),
422 Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag);
423 InFlag = Chain.getValue(1);
424 Chain = SDValue(CurDAG->getMachineNode(Alpha::JSR, dl, MVT::Other,
425 MVT::Flag, Chain, InFlag), 0);
427 InFlag = Chain.getValue(1);
429 ReplaceUses(SDValue(N, 0), Chain);
430 ReplaceUses(SDValue(N, 1), InFlag);
434 /// createAlphaISelDag - This pass converts a legalized DAG into a
435 /// Alpha-specific DAG, ready for instruction scheduling.
437 FunctionPass *llvm::createAlphaISelDag(AlphaTargetMachine &TM) {
438 return new AlphaDAGToDAGISel(TM);