1 //===- ARM64InstrInfo.td - Describe the ARM64 Instructions -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // ARM64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto", "crypto">;
23 def HasCRC : Predicate<"Subtarget->hasCRC()">,
24 AssemblerPredicate<"FeatureCRC", "crc">;
25 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
26 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
28 //===----------------------------------------------------------------------===//
29 // ARM64-specific DAG Nodes.
32 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
33 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
36 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
39 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
45 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
46 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
53 def SDT_ARM64Brcond : SDTypeProfile<0, 3,
54 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
56 def SDT_ARM64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
57 def SDT_ARM64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
58 SDTCisVT<2, OtherVT>]>;
61 def SDT_ARM64CSel : SDTypeProfile<1, 4,
66 def SDT_ARM64FCmp : SDTypeProfile<0, 2,
69 def SDT_ARM64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
70 def SDT_ARM64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
71 def SDT_ARM64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
74 def SDT_ARM64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
75 def SDT_ARM64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
76 def SDT_ARM64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
77 SDTCisInt<2>, SDTCisInt<3>]>;
78 def SDT_ARM64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
79 def SDT_ARM64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
80 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
81 def SDT_ARM64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
83 def SDT_ARM64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
84 def SDT_ARM64fcmpz : SDTypeProfile<1, 1, []>;
85 def SDT_ARM64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
86 def SDT_ARM64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
88 def SDT_ARM64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
91 def SDT_ARM64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
92 def SDT_ARM64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
94 def SDT_ARM64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
96 def SDT_ARM64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
98 def SDT_ARM64WrapperLarge : SDTypeProfile<1, 4,
99 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
100 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
101 SDTCisSameAs<1, 4>]>;
105 def ARM64adrp : SDNode<"ARM64ISD::ADRP", SDTIntUnaryOp, []>;
106 def ARM64addlow : SDNode<"ARM64ISD::ADDlow", SDTIntBinOp, []>;
107 def ARM64LOADgot : SDNode<"ARM64ISD::LOADgot", SDTIntUnaryOp>;
108 def ARM64callseq_start : SDNode<"ISD::CALLSEQ_START",
109 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
110 [SDNPHasChain, SDNPOutGlue]>;
111 def ARM64callseq_end : SDNode<"ISD::CALLSEQ_END",
112 SDCallSeqEnd<[ SDTCisVT<0, i32>,
114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
115 def ARM64call : SDNode<"ARM64ISD::CALL",
116 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def ARM64brcond : SDNode<"ARM64ISD::BRCOND", SDT_ARM64Brcond,
121 def ARM64cbz : SDNode<"ARM64ISD::CBZ", SDT_ARM64cbz,
123 def ARM64cbnz : SDNode<"ARM64ISD::CBNZ", SDT_ARM64cbz,
125 def ARM64tbz : SDNode<"ARM64ISD::TBZ", SDT_ARM64tbz,
127 def ARM64tbnz : SDNode<"ARM64ISD::TBNZ", SDT_ARM64tbz,
131 def ARM64csel : SDNode<"ARM64ISD::CSEL", SDT_ARM64CSel>;
132 def ARM64csinv : SDNode<"ARM64ISD::CSINV", SDT_ARM64CSel>;
133 def ARM64csneg : SDNode<"ARM64ISD::CSNEG", SDT_ARM64CSel>;
134 def ARM64csinc : SDNode<"ARM64ISD::CSINC", SDT_ARM64CSel>;
135 def ARM64retflag : SDNode<"ARM64ISD::RET_FLAG", SDTNone,
136 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
137 def ARM64adc : SDNode<"ARM64ISD::ADC", SDTBinaryArithWithFlagsIn >;
138 def ARM64sbc : SDNode<"ARM64ISD::SBC", SDTBinaryArithWithFlagsIn>;
139 def ARM64add_flag : SDNode<"ARM64ISD::ADDS", SDTBinaryArithWithFlagsOut,
141 def ARM64sub_flag : SDNode<"ARM64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
142 def ARM64and_flag : SDNode<"ARM64ISD::ANDS", SDTBinaryArithWithFlagsOut,
144 def ARM64adc_flag : SDNode<"ARM64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
145 def ARM64sbc_flag : SDNode<"ARM64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
147 def ARM64threadpointer : SDNode<"ARM64ISD::THREAD_POINTER", SDTPtrLeaf>;
149 def ARM64fcmp : SDNode<"ARM64ISD::FCMP", SDT_ARM64FCmp>;
151 def ARM64fmax : SDNode<"ARM64ISD::FMAX", SDTFPBinOp>;
152 def ARM64fmin : SDNode<"ARM64ISD::FMIN", SDTFPBinOp>;
154 def ARM64dup : SDNode<"ARM64ISD::DUP", SDT_ARM64Dup>;
155 def ARM64duplane8 : SDNode<"ARM64ISD::DUPLANE8", SDT_ARM64DupLane>;
156 def ARM64duplane16 : SDNode<"ARM64ISD::DUPLANE16", SDT_ARM64DupLane>;
157 def ARM64duplane32 : SDNode<"ARM64ISD::DUPLANE32", SDT_ARM64DupLane>;
158 def ARM64duplane64 : SDNode<"ARM64ISD::DUPLANE64", SDT_ARM64DupLane>;
160 def ARM64zip1 : SDNode<"ARM64ISD::ZIP1", SDT_ARM64Zip>;
161 def ARM64zip2 : SDNode<"ARM64ISD::ZIP2", SDT_ARM64Zip>;
162 def ARM64uzp1 : SDNode<"ARM64ISD::UZP1", SDT_ARM64Zip>;
163 def ARM64uzp2 : SDNode<"ARM64ISD::UZP2", SDT_ARM64Zip>;
164 def ARM64trn1 : SDNode<"ARM64ISD::TRN1", SDT_ARM64Zip>;
165 def ARM64trn2 : SDNode<"ARM64ISD::TRN2", SDT_ARM64Zip>;
167 def ARM64movi_edit : SDNode<"ARM64ISD::MOVIedit", SDT_ARM64MOVIedit>;
168 def ARM64movi_shift : SDNode<"ARM64ISD::MOVIshift", SDT_ARM64MOVIshift>;
169 def ARM64movi_msl : SDNode<"ARM64ISD::MOVImsl", SDT_ARM64MOVIshift>;
170 def ARM64mvni_shift : SDNode<"ARM64ISD::MVNIshift", SDT_ARM64MOVIshift>;
171 def ARM64mvni_msl : SDNode<"ARM64ISD::MVNImsl", SDT_ARM64MOVIshift>;
172 def ARM64movi : SDNode<"ARM64ISD::MOVI", SDT_ARM64MOVIedit>;
173 def ARM64fmov : SDNode<"ARM64ISD::FMOV", SDT_ARM64MOVIedit>;
175 def ARM64rev16 : SDNode<"ARM64ISD::REV16", SDT_ARM64UnaryVec>;
176 def ARM64rev32 : SDNode<"ARM64ISD::REV32", SDT_ARM64UnaryVec>;
177 def ARM64rev64 : SDNode<"ARM64ISD::REV64", SDT_ARM64UnaryVec>;
178 def ARM64ext : SDNode<"ARM64ISD::EXT", SDT_ARM64ExtVec>;
180 def ARM64vashr : SDNode<"ARM64ISD::VASHR", SDT_ARM64vshift>;
181 def ARM64vlshr : SDNode<"ARM64ISD::VLSHR", SDT_ARM64vshift>;
182 def ARM64vshl : SDNode<"ARM64ISD::VSHL", SDT_ARM64vshift>;
183 def ARM64sqshli : SDNode<"ARM64ISD::SQSHL_I", SDT_ARM64vshift>;
184 def ARM64uqshli : SDNode<"ARM64ISD::UQSHL_I", SDT_ARM64vshift>;
185 def ARM64sqshlui : SDNode<"ARM64ISD::SQSHLU_I", SDT_ARM64vshift>;
186 def ARM64srshri : SDNode<"ARM64ISD::SRSHR_I", SDT_ARM64vshift>;
187 def ARM64urshri : SDNode<"ARM64ISD::URSHR_I", SDT_ARM64vshift>;
189 def ARM64not: SDNode<"ARM64ISD::NOT", SDT_ARM64unvec>;
190 def ARM64bit: SDNode<"ARM64ISD::BIT", SDT_ARM64trivec>;
191 def ARM64bsl: SDNode<"ARM64ISD::BSL", SDT_ARM64trivec>;
193 def ARM64cmeq: SDNode<"ARM64ISD::CMEQ", SDT_ARM64binvec>;
194 def ARM64cmge: SDNode<"ARM64ISD::CMGE", SDT_ARM64binvec>;
195 def ARM64cmgt: SDNode<"ARM64ISD::CMGT", SDT_ARM64binvec>;
196 def ARM64cmhi: SDNode<"ARM64ISD::CMHI", SDT_ARM64binvec>;
197 def ARM64cmhs: SDNode<"ARM64ISD::CMHS", SDT_ARM64binvec>;
199 def ARM64fcmeq: SDNode<"ARM64ISD::FCMEQ", SDT_ARM64fcmp>;
200 def ARM64fcmge: SDNode<"ARM64ISD::FCMGE", SDT_ARM64fcmp>;
201 def ARM64fcmgt: SDNode<"ARM64ISD::FCMGT", SDT_ARM64fcmp>;
203 def ARM64cmeqz: SDNode<"ARM64ISD::CMEQz", SDT_ARM64unvec>;
204 def ARM64cmgez: SDNode<"ARM64ISD::CMGEz", SDT_ARM64unvec>;
205 def ARM64cmgtz: SDNode<"ARM64ISD::CMGTz", SDT_ARM64unvec>;
206 def ARM64cmlez: SDNode<"ARM64ISD::CMLEz", SDT_ARM64unvec>;
207 def ARM64cmltz: SDNode<"ARM64ISD::CMLTz", SDT_ARM64unvec>;
208 def ARM64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
209 (ARM64not (ARM64cmeqz (and node:$LHS, node:$RHS)))>;
211 def ARM64fcmeqz: SDNode<"ARM64ISD::FCMEQz", SDT_ARM64fcmpz>;
212 def ARM64fcmgez: SDNode<"ARM64ISD::FCMGEz", SDT_ARM64fcmpz>;
213 def ARM64fcmgtz: SDNode<"ARM64ISD::FCMGTz", SDT_ARM64fcmpz>;
214 def ARM64fcmlez: SDNode<"ARM64ISD::FCMLEz", SDT_ARM64fcmpz>;
215 def ARM64fcmltz: SDNode<"ARM64ISD::FCMLTz", SDT_ARM64fcmpz>;
217 def ARM64bici: SDNode<"ARM64ISD::BICi", SDT_ARM64vecimm>;
218 def ARM64orri: SDNode<"ARM64ISD::ORRi", SDT_ARM64vecimm>;
220 def ARM64neg : SDNode<"ARM64ISD::NEG", SDT_ARM64unvec>;
222 def ARM64tcret: SDNode<"ARM64ISD::TC_RETURN", SDT_ARM64TCRET,
223 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
225 def ARM64Prefetch : SDNode<"ARM64ISD::PREFETCH", SDT_ARM64PREFETCH,
226 [SDNPHasChain, SDNPSideEffect]>;
228 def ARM64sitof: SDNode<"ARM64ISD::SITOF", SDT_ARM64ITOF>;
229 def ARM64uitof: SDNode<"ARM64ISD::UITOF", SDT_ARM64ITOF>;
231 def ARM64tlsdesc_call : SDNode<"ARM64ISD::TLSDESC_CALL", SDT_ARM64TLSDescCall,
232 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
235 def ARM64WrapperLarge : SDNode<"ARM64ISD::WrapperLarge", SDT_ARM64WrapperLarge>;
238 //===----------------------------------------------------------------------===//
240 //===----------------------------------------------------------------------===//
242 // ARM64 Instruction Predicate Definitions.
244 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
245 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
246 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
247 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
248 def ForCodeSize : Predicate<"ForCodeSize">;
249 def NotForCodeSize : Predicate<"!ForCodeSize">;
251 include "ARM64InstrFormats.td"
253 //===----------------------------------------------------------------------===//
255 //===----------------------------------------------------------------------===//
256 // Miscellaneous instructions.
257 //===----------------------------------------------------------------------===//
259 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
260 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
261 [(ARM64callseq_start timm:$amt)]>;
262 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
263 [(ARM64callseq_end timm:$amt1, timm:$amt2)]>;
264 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
266 let isReMaterializable = 1, isCodeGenOnly = 1 in {
267 // FIXME: The following pseudo instructions are only needed because remat
268 // cannot handle multiple instructions. When that changes, they can be
269 // removed, along with the ARM64Wrapper node.
271 let AddedComplexity = 10 in
272 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
273 [(set GPR64:$dst, (ARM64LOADgot tglobaladdr:$addr))]>,
276 // The MOVaddr instruction should match only when the add is not folded
277 // into a load or store address.
279 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
280 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaladdr:$hi),
281 tglobaladdr:$low))]>,
282 Sched<[WriteAdrAdr]>;
284 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
285 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tjumptable:$hi),
287 Sched<[WriteAdrAdr]>;
289 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
290 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tconstpool:$hi),
292 Sched<[WriteAdrAdr]>;
294 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
295 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tblockaddress:$hi),
296 tblockaddress:$low))]>,
297 Sched<[WriteAdrAdr]>;
299 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
300 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaltlsaddr:$hi),
301 tglobaltlsaddr:$low))]>,
302 Sched<[WriteAdrAdr]>;
304 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
305 [(set GPR64:$dst, (ARM64addlow (ARM64adrp texternalsym:$hi),
306 texternalsym:$low))]>,
307 Sched<[WriteAdrAdr]>;
309 } // isReMaterializable, isCodeGenOnly
311 def : Pat<(ARM64LOADgot tglobaltlsaddr:$addr),
312 (LOADgot tglobaltlsaddr:$addr)>;
314 def : Pat<(ARM64LOADgot texternalsym:$addr),
315 (LOADgot texternalsym:$addr)>;
317 def : Pat<(ARM64LOADgot tconstpool:$addr),
318 (LOADgot tconstpool:$addr)>;
320 //===----------------------------------------------------------------------===//
321 // System instructions.
322 //===----------------------------------------------------------------------===//
324 def HINT : HintI<"hint">;
325 def : InstAlias<"nop", (HINT 0b000)>;
326 def : InstAlias<"yield",(HINT 0b001)>;
327 def : InstAlias<"wfe", (HINT 0b010)>;
328 def : InstAlias<"wfi", (HINT 0b011)>;
329 def : InstAlias<"sev", (HINT 0b100)>;
330 def : InstAlias<"sevl", (HINT 0b101)>;
332 // As far as LLVM is concerned this writes to the system's exclusive monitors.
333 let mayLoad = 1, mayStore = 1 in
334 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
336 def DMB : CRmSystemI<barrier_op, 0b101, "dmb">;
337 def DSB : CRmSystemI<barrier_op, 0b100, "dsb">;
338 def ISB : CRmSystemI<barrier_op, 0b110, "isb">;
339 def : InstAlias<"clrex", (CLREX 0xf)>;
340 def : InstAlias<"isb", (ISB 0xf)>;
344 def MSRpstate: MSRpstateI;
346 // The thread pointer (on Linux, at least, where this has been implemented) is
348 def : Pat<(ARM64threadpointer), (MRS 0xde82)>;
350 // Generic system instructions
351 def SYSxt : SystemXtI<0, "sys">;
352 def SYSLxt : SystemLXtI<1, "sysl">;
354 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
355 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
356 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
358 //===----------------------------------------------------------------------===//
359 // Move immediate instructions.
360 //===----------------------------------------------------------------------===//
362 defm MOVK : InsertImmediate<0b11, "movk">;
363 defm MOVN : MoveImmediate<0b00, "movn">;
365 let PostEncoderMethod = "fixMOVZ" in
366 defm MOVZ : MoveImmediate<0b10, "movz">;
368 // First group of aliases covers an implicit "lsl #0".
369 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
370 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
371 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
372 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
373 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
374 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
376 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
377 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
378 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
379 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
380 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
382 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
383 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
384 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
385 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
387 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
388 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
389 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
390 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
392 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
393 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
395 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
396 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
398 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
399 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
401 // Final group of aliases covers true "mov $Rd, $imm" cases.
402 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
403 int width, int shift> {
404 def _asmoperand : AsmOperandClass {
405 let Name = basename # width # "_lsl" # shift # "MovAlias";
406 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
408 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
411 def _movimm : Operand<i32> {
412 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
415 def : InstAlias<"mov $Rd, $imm",
416 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
419 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
420 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
422 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
423 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
424 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
425 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
427 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
428 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
430 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
431 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
432 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
433 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
435 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
436 isAsCheapAsAMove = 1 in {
437 // FIXME: The following pseudo instructions are only needed because remat
438 // cannot handle multiple instructions. When that changes, we can select
439 // directly to the real instructions and get rid of these pseudos.
442 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
443 [(set GPR32:$dst, imm:$src)]>,
446 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
447 [(set GPR64:$dst, imm:$src)]>,
449 } // isReMaterializable, isCodeGenOnly
451 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
452 // eventual expansion code fewer bits to worry about getting right. Marshalling
453 // the types is a little tricky though:
454 def i64imm_32bit : ImmLeaf<i64, [{
455 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
458 def trunc_imm : SDNodeXForm<imm, [{
459 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
462 def : Pat<(i64 i64imm_32bit:$src),
463 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
465 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
467 def : Pat<(ARM64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
468 tglobaladdr:$g1, tglobaladdr:$g0),
469 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
470 tglobaladdr:$g2, 32),
471 tglobaladdr:$g1, 16),
472 tglobaladdr:$g0, 0)>;
474 def : Pat<(ARM64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
475 tblockaddress:$g1, tblockaddress:$g0),
476 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
477 tblockaddress:$g2, 32),
478 tblockaddress:$g1, 16),
479 tblockaddress:$g0, 0)>;
481 def : Pat<(ARM64WrapperLarge tconstpool:$g3, tconstpool:$g2,
482 tconstpool:$g1, tconstpool:$g0),
483 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
488 def : Pat<(ARM64WrapperLarge tjumptable:$g3, tjumptable:$g2,
489 tjumptable:$g1, tjumptable:$g0),
490 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
496 //===----------------------------------------------------------------------===//
497 // Arithmetic instructions.
498 //===----------------------------------------------------------------------===//
500 // Add/subtract with carry.
501 defm ADC : AddSubCarry<0, "adc", "adcs", ARM64adc, ARM64adc_flag>;
502 defm SBC : AddSubCarry<1, "sbc", "sbcs", ARM64sbc, ARM64sbc_flag>;
504 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
505 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
506 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
507 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
510 defm ADD : AddSub<0, "add", add>;
511 defm SUB : AddSub<1, "sub">;
513 def : InstAlias<"mov $dst, $src",
514 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
515 def : InstAlias<"mov $dst, $src",
516 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
517 def : InstAlias<"mov $dst, $src",
518 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
519 def : InstAlias<"mov $dst, $src",
520 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
522 defm ADDS : AddSubS<0, "adds", ARM64add_flag, "cmn">;
523 defm SUBS : AddSubS<1, "subs", ARM64sub_flag, "cmp">;
525 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
526 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
527 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
528 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
529 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
530 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
531 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
532 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
533 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
534 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
535 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
536 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
537 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
538 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
539 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
540 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
541 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
543 // Because of the immediate format for add/sub-imm instructions, the
544 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
545 // These patterns capture that transformation.
546 let AddedComplexity = 1 in {
547 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
548 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
549 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
550 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
551 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
552 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
553 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
554 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
557 // Because of the immediate format for add/sub-imm instructions, the
558 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
559 // These patterns capture that transformation.
560 let AddedComplexity = 1 in {
561 def : Pat<(ARM64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
562 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
563 def : Pat<(ARM64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
564 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
565 def : Pat<(ARM64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
566 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
567 def : Pat<(ARM64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
568 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
571 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
572 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
573 def : InstAlias<"neg $dst, $src$shift",
574 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
575 def : InstAlias<"neg $dst, $src$shift",
576 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
578 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
579 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
580 def : InstAlias<"negs $dst, $src$shift",
581 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
582 def : InstAlias<"negs $dst, $src$shift",
583 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
586 // Unsigned/Signed divide
587 defm UDIV : Div<0, "udiv", udiv>;
588 defm SDIV : Div<1, "sdiv", sdiv>;
589 let isCodeGenOnly = 1 in {
590 defm UDIV_Int : Div<0, "udiv", int_arm64_udiv>;
591 defm SDIV_Int : Div<1, "sdiv", int_arm64_sdiv>;
595 defm ASRV : Shift<0b10, "asr", sra>;
596 defm LSLV : Shift<0b00, "lsl", shl>;
597 defm LSRV : Shift<0b01, "lsr", srl>;
598 defm RORV : Shift<0b11, "ror", rotr>;
600 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
601 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
602 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
603 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
604 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
605 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
606 def : ShiftAlias<"rorv", RORVWr, GPR32>;
607 def : ShiftAlias<"rorv", RORVXr, GPR64>;
610 let AddedComplexity = 7 in {
611 defm MADD : MulAccum<0, "madd", add>;
612 defm MSUB : MulAccum<1, "msub", sub>;
614 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
615 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
616 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
617 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
619 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
620 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
621 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
622 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
623 } // AddedComplexity = 7
625 let AddedComplexity = 5 in {
626 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
627 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
628 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
629 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
631 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
632 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
633 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
634 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
636 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
637 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
638 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
639 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
640 } // AddedComplexity = 5
642 def : MulAccumWAlias<"mul", MADDWrrr>;
643 def : MulAccumXAlias<"mul", MADDXrrr>;
644 def : MulAccumWAlias<"mneg", MSUBWrrr>;
645 def : MulAccumXAlias<"mneg", MSUBXrrr>;
646 def : WideMulAccumAlias<"smull", SMADDLrrr>;
647 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
648 def : WideMulAccumAlias<"umull", UMADDLrrr>;
649 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
652 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
653 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
656 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_arm64_crc32b, "crc32b">;
657 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_arm64_crc32h, "crc32h">;
658 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_arm64_crc32w, "crc32w">;
659 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_arm64_crc32x, "crc32x">;
661 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_arm64_crc32cb, "crc32cb">;
662 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_arm64_crc32ch, "crc32ch">;
663 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_arm64_crc32cw, "crc32cw">;
664 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_arm64_crc32cx, "crc32cx">;
667 //===----------------------------------------------------------------------===//
668 // Logical instructions.
669 //===----------------------------------------------------------------------===//
672 defm ANDS : LogicalImmS<0b11, "ands", ARM64and_flag>;
673 defm AND : LogicalImm<0b00, "and", and>;
674 defm EOR : LogicalImm<0b10, "eor", xor>;
675 defm ORR : LogicalImm<0b01, "orr", or>;
677 // FIXME: these aliases *are* canonical sometimes (when movz can't be
678 // used). Actually, it seems to be working right now, but putting logical_immXX
679 // here is a bit dodgy on the AsmParser side too.
680 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
681 logical_imm32:$imm), 0>;
682 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
683 logical_imm64:$imm), 0>;
687 defm ANDS : LogicalRegS<0b11, 0, "ands", ARM64and_flag>;
688 defm BICS : LogicalRegS<0b11, 1, "bics",
689 BinOpFrag<(ARM64and_flag node:$LHS, (not node:$RHS))>>;
690 defm AND : LogicalReg<0b00, 0, "and", and>;
691 defm BIC : LogicalReg<0b00, 1, "bic",
692 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
693 defm EON : LogicalReg<0b10, 1, "eon",
694 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
695 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
696 defm ORN : LogicalReg<0b01, 1, "orn",
697 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
698 defm ORR : LogicalReg<0b01, 0, "orr", or>;
700 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
701 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
703 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
704 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
706 def : InstAlias<"mvn $Wd, $Wm$sh",
707 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
708 def : InstAlias<"mvn $Xd, $Xm$sh",
709 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
711 def : InstAlias<"tst $src1, $src2",
712 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
713 def : InstAlias<"tst $src1, $src2",
714 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
716 def : InstAlias<"tst $src1, $src2",
717 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
718 def : InstAlias<"tst $src1, $src2",
719 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
721 def : InstAlias<"tst $src1, $src2$sh",
722 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
723 def : InstAlias<"tst $src1, $src2$sh",
724 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
727 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
728 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
731 //===----------------------------------------------------------------------===//
732 // One operand data processing instructions.
733 //===----------------------------------------------------------------------===//
735 defm CLS : OneOperandData<0b101, "cls">;
736 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
737 defm RBIT : OneOperandData<0b000, "rbit">;
738 def REV16Wr : OneWRegData<0b001, "rev16",
739 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
740 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
742 def : Pat<(cttz GPR32:$Rn),
743 (CLZWr (RBITWr GPR32:$Rn))>;
744 def : Pat<(cttz GPR64:$Rn),
745 (CLZXr (RBITXr GPR64:$Rn))>;
746 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
749 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
753 // Unlike the other one operand instructions, the instructions with the "rev"
754 // mnemonic do *not* just different in the size bit, but actually use different
755 // opcode bits for the different sizes.
756 def REVWr : OneWRegData<0b010, "rev", bswap>;
757 def REVXr : OneXRegData<0b011, "rev", bswap>;
758 def REV32Xr : OneXRegData<0b010, "rev32",
759 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
761 // The bswap commutes with the rotr so we want a pattern for both possible
763 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
764 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
766 //===----------------------------------------------------------------------===//
767 // Bitfield immediate extraction instruction.
768 //===----------------------------------------------------------------------===//
769 let neverHasSideEffects = 1 in
770 defm EXTR : ExtractImm<"extr">;
771 def : InstAlias<"ror $dst, $src, $shift",
772 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
773 def : InstAlias<"ror $dst, $src, $shift",
774 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
776 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
777 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
778 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
779 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
781 //===----------------------------------------------------------------------===//
782 // Other bitfield immediate instructions.
783 //===----------------------------------------------------------------------===//
784 let neverHasSideEffects = 1 in {
785 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
786 defm SBFM : BitfieldImm<0b00, "sbfm">;
787 defm UBFM : BitfieldImm<0b10, "ubfm">;
790 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
791 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
792 return CurDAG->getTargetConstant(enc, MVT::i64);
795 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
796 uint64_t enc = 31 - N->getZExtValue();
797 return CurDAG->getTargetConstant(enc, MVT::i64);
800 // min(7, 31 - shift_amt)
801 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
802 uint64_t enc = 31 - N->getZExtValue();
803 enc = enc > 7 ? 7 : enc;
804 return CurDAG->getTargetConstant(enc, MVT::i64);
807 // min(15, 31 - shift_amt)
808 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
809 uint64_t enc = 31 - N->getZExtValue();
810 enc = enc > 15 ? 15 : enc;
811 return CurDAG->getTargetConstant(enc, MVT::i64);
814 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
815 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
816 return CurDAG->getTargetConstant(enc, MVT::i64);
819 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
820 uint64_t enc = 63 - N->getZExtValue();
821 return CurDAG->getTargetConstant(enc, MVT::i64);
824 // min(7, 63 - shift_amt)
825 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
826 uint64_t enc = 63 - N->getZExtValue();
827 enc = enc > 7 ? 7 : enc;
828 return CurDAG->getTargetConstant(enc, MVT::i64);
831 // min(15, 63 - shift_amt)
832 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
833 uint64_t enc = 63 - N->getZExtValue();
834 enc = enc > 15 ? 15 : enc;
835 return CurDAG->getTargetConstant(enc, MVT::i64);
838 // min(31, 63 - shift_amt)
839 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
840 uint64_t enc = 63 - N->getZExtValue();
841 enc = enc > 31 ? 31 : enc;
842 return CurDAG->getTargetConstant(enc, MVT::i64);
845 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
846 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
847 (i64 (i32shift_b imm0_31:$imm)))>;
848 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
849 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
850 (i64 (i64shift_b imm0_63:$imm)))>;
852 let AddedComplexity = 10 in {
853 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
854 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
855 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
856 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
859 def : InstAlias<"asr $dst, $src, $shift",
860 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
861 def : InstAlias<"asr $dst, $src, $shift",
862 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
863 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
864 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
865 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
866 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
867 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
869 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
870 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
871 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
872 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
874 def : InstAlias<"lsr $dst, $src, $shift",
875 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
876 def : InstAlias<"lsr $dst, $src, $shift",
877 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
878 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
879 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
880 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
881 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
882 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
884 //===----------------------------------------------------------------------===//
885 // Conditionally set flags instructions.
886 //===----------------------------------------------------------------------===//
887 defm CCMN : CondSetFlagsImm<0, "ccmn">;
888 defm CCMP : CondSetFlagsImm<1, "ccmp">;
890 defm CCMN : CondSetFlagsReg<0, "ccmn">;
891 defm CCMP : CondSetFlagsReg<1, "ccmp">;
893 //===----------------------------------------------------------------------===//
894 // Conditional select instructions.
895 //===----------------------------------------------------------------------===//
896 defm CSEL : CondSelect<0, 0b00, "csel">;
898 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
899 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
900 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
901 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
903 def : Pat<(ARM64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
904 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
905 def : Pat<(ARM64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
906 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
907 def : Pat<(ARM64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
908 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
909 def : Pat<(ARM64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
910 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
911 def : Pat<(ARM64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
912 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
913 def : Pat<(ARM64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
914 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
916 def : Pat<(ARM64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
917 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
918 def : Pat<(ARM64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
919 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
920 def : Pat<(ARM64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
921 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
922 def : Pat<(ARM64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
923 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
925 // The inverse of the condition code from the alias instruction is what is used
926 // in the aliased instruction. The parser all ready inverts the condition code
927 // for these aliases.
928 def : InstAlias<"cset $dst, $cc",
929 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
930 def : InstAlias<"cset $dst, $cc",
931 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
933 def : InstAlias<"csetm $dst, $cc",
934 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
935 def : InstAlias<"csetm $dst, $cc",
936 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
938 def : InstAlias<"cinc $dst, $src, $cc",
939 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
940 def : InstAlias<"cinc $dst, $src, $cc",
941 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
943 def : InstAlias<"cinv $dst, $src, $cc",
944 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
945 def : InstAlias<"cinv $dst, $src, $cc",
946 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
948 def : InstAlias<"cneg $dst, $src, $cc",
949 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
950 def : InstAlias<"cneg $dst, $src, $cc",
951 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
953 //===----------------------------------------------------------------------===//
954 // PC-relative instructions.
955 //===----------------------------------------------------------------------===//
956 let isReMaterializable = 1 in {
957 let neverHasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
958 def ADR : ADRI<0, "adr", adrlabel, []>;
959 } // neverHasSideEffects = 1
961 def ADRP : ADRI<1, "adrp", adrplabel,
962 [(set GPR64:$Xd, (ARM64adrp tglobaladdr:$label))]>;
963 } // isReMaterializable = 1
965 // page address of a constant pool entry, block address
966 def : Pat<(ARM64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
967 def : Pat<(ARM64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
969 //===----------------------------------------------------------------------===//
970 // Unconditional branch (register) instructions.
971 //===----------------------------------------------------------------------===//
973 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
974 def RET : BranchReg<0b0010, "ret", []>;
975 def DRPS : SpecialReturn<0b0101, "drps">;
976 def ERET : SpecialReturn<0b0100, "eret">;
977 } // isReturn = 1, isTerminator = 1, isBarrier = 1
979 // Default to the LR register.
980 def : InstAlias<"ret", (RET LR)>;
982 let isCall = 1, Defs = [LR], Uses = [SP] in {
983 def BLR : BranchReg<0b0001, "blr", [(ARM64call GPR64:$Rn)]>;
986 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
987 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
988 } // isBranch, isTerminator, isBarrier, isIndirectBranch
990 // Create a separate pseudo-instruction for codegen to use so that we don't
991 // flag lr as used in every function. It'll be restored before the RET by the
992 // epilogue if it's legitimately used.
993 def RET_ReallyLR : Pseudo<(outs), (ins), [(ARM64retflag)]> {
994 let isTerminator = 1;
999 // This is a directive-like pseudo-instruction. The purpose is to insert an
1000 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1001 // (which in the usual case is a BLR).
1002 let hasSideEffects = 1 in
1003 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1004 let AsmString = ".tlsdesccall $sym";
1007 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
1008 // gets expanded to two MCInsts during lowering.
1009 let isCall = 1, Defs = [LR] in
1011 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
1012 [(ARM64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
1014 def : Pat<(ARM64tlsdesc_call GPR64:$dest, texternalsym:$sym),
1015 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
1016 //===----------------------------------------------------------------------===//
1017 // Conditional branch (immediate) instruction.
1018 //===----------------------------------------------------------------------===//
1019 def Bcc : BranchCond;
1021 //===----------------------------------------------------------------------===//
1022 // Compare-and-branch instructions.
1023 //===----------------------------------------------------------------------===//
1024 defm CBZ : CmpBranch<0, "cbz", ARM64cbz>;
1025 defm CBNZ : CmpBranch<1, "cbnz", ARM64cbnz>;
1027 //===----------------------------------------------------------------------===//
1028 // Test-bit-and-branch instructions.
1029 //===----------------------------------------------------------------------===//
1030 defm TBZ : TestBranch<0, "tbz", ARM64tbz>;
1031 defm TBNZ : TestBranch<1, "tbnz", ARM64tbnz>;
1033 //===----------------------------------------------------------------------===//
1034 // Unconditional branch (immediate) instructions.
1035 //===----------------------------------------------------------------------===//
1036 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1037 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1038 } // isBranch, isTerminator, isBarrier
1040 let isCall = 1, Defs = [LR], Uses = [SP] in {
1041 def BL : CallImm<1, "bl", [(ARM64call tglobaladdr:$addr)]>;
1043 def : Pat<(ARM64call texternalsym:$func), (BL texternalsym:$func)>;
1045 //===----------------------------------------------------------------------===//
1046 // Exception generation instructions.
1047 //===----------------------------------------------------------------------===//
1048 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1049 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1050 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1051 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1052 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1053 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1054 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1055 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1057 // DCPSn defaults to an immediate operand of zero if unspecified.
1058 def : InstAlias<"dcps1", (DCPS1 0)>;
1059 def : InstAlias<"dcps2", (DCPS2 0)>;
1060 def : InstAlias<"dcps3", (DCPS3 0)>;
1062 //===----------------------------------------------------------------------===//
1063 // Load instructions.
1064 //===----------------------------------------------------------------------===//
1066 // Pair (indexed, offset)
1067 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1068 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1069 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1070 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1071 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1073 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1075 // Pair (pre-indexed)
1076 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1077 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1078 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1079 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1080 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1082 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1084 // Pair (post-indexed)
1085 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1086 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1087 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1088 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1089 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1091 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1094 // Pair (no allocate)
1095 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1096 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1097 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1098 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1099 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1102 // (register offset)
1106 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1107 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1108 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1109 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1112 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1113 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1114 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1115 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1116 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1118 // Load sign-extended half-word
1119 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1120 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1122 // Load sign-extended byte
1123 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1124 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1126 // Load sign-extended word
1127 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1130 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1132 // For regular load, we do not have any alignment requirement.
1133 // Thus, it is safe to directly map the vector loads with interesting
1134 // addressing modes.
1135 // FIXME: We could do the same for bitconvert to floating point vectors.
1136 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1137 ValueType ScalTy, ValueType VecTy,
1138 Instruction LOADW, Instruction LOADX,
1140 def : Pat<(VecTy (scalar_to_vector (ScalTy
1141 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1142 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1143 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1146 def : Pat<(VecTy (scalar_to_vector (ScalTy
1147 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1148 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1149 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1153 let AddedComplexity = 10 in {
1154 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1155 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1157 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1158 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1160 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1161 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1163 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1164 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1166 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1168 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1171 def : Pat <(v1i64 (scalar_to_vector (i64
1172 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1173 ro_Wextend64:$extend))))),
1174 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1176 def : Pat <(v1i64 (scalar_to_vector (i64
1177 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1178 ro_Xextend64:$extend))))),
1179 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1182 // Match all load 64 bits width whose type is compatible with FPR64
1183 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1184 Instruction LOADW, Instruction LOADX> {
1186 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1187 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1189 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1190 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1193 let AddedComplexity = 10 in {
1194 let Predicates = [IsLE] in {
1195 // We must do vector loads with LD1 in big-endian.
1196 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1197 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1198 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1199 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1202 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1203 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1205 // Match all load 128 bits width whose type is compatible with FPR128
1206 let Predicates = [IsLE] in {
1207 // We must do vector loads with LD1 in big-endian.
1208 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1209 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1210 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1211 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1212 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1213 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1215 } // AddedComplexity = 10
1218 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1219 Instruction INSTW, Instruction INSTX> {
1220 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1221 (SUBREG_TO_REG (i64 0),
1222 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1225 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1226 (SUBREG_TO_REG (i64 0),
1227 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1231 let AddedComplexity = 10 in {
1232 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1233 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1234 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1236 // zextloadi1 -> zextloadi8
1237 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1239 // extload -> zextload
1240 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1241 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1242 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1244 // extloadi1 -> zextloadi8
1245 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1250 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1251 Instruction INSTW, Instruction INSTX> {
1252 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1253 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1255 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1256 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1260 let AddedComplexity = 10 in {
1261 // extload -> zextload
1262 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1263 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1264 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1266 // zextloadi1 -> zextloadi8
1267 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1271 // (unsigned immediate)
1273 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1275 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1276 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1278 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1279 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1281 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1282 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1283 [(set (f16 FPR16:$Rt),
1284 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1285 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1286 [(set (f32 FPR32:$Rt),
1287 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1288 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1289 [(set (f64 FPR64:$Rt),
1290 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1291 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1292 [(set (f128 FPR128:$Rt),
1293 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1295 // For regular load, we do not have any alignment requirement.
1296 // Thus, it is safe to directly map the vector loads with interesting
1297 // addressing modes.
1298 // FIXME: We could do the same for bitconvert to floating point vectors.
1299 def : Pat <(v8i8 (scalar_to_vector (i32
1300 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1301 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1302 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1303 def : Pat <(v16i8 (scalar_to_vector (i32
1304 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1305 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1306 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1307 def : Pat <(v4i16 (scalar_to_vector (i32
1308 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1309 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1310 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1311 def : Pat <(v8i16 (scalar_to_vector (i32
1312 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1313 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1314 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1315 def : Pat <(v2i32 (scalar_to_vector (i32
1316 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1317 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1318 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1319 def : Pat <(v4i32 (scalar_to_vector (i32
1320 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1321 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1322 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1323 def : Pat <(v1i64 (scalar_to_vector (i64
1324 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1325 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1326 def : Pat <(v2i64 (scalar_to_vector (i64
1327 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1328 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1329 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1331 // Match all load 64 bits width whose type is compatible with FPR64
1332 let Predicates = [IsLE] in {
1333 // We must use LD1 to perform vector loads in big-endian.
1334 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1335 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1336 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1337 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1338 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1339 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1340 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1341 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1343 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1344 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1345 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1346 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1348 // Match all load 128 bits width whose type is compatible with FPR128
1349 let Predicates = [IsLE] in {
1350 // We must use LD1 to perform vector loads in big-endian.
1351 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1352 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1353 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1354 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1355 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1356 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1357 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1358 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1359 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1360 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1361 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1362 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1364 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1365 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1367 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1369 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1370 uimm12s2:$offset)))]>;
1371 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1373 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1374 uimm12s1:$offset)))]>;
1376 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1377 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1378 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1379 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1381 // zextloadi1 -> zextloadi8
1382 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1383 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1384 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1385 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1387 // extload -> zextload
1388 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1389 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1390 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1391 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1392 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1393 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1394 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1395 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1396 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1397 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1398 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1399 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1400 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1401 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1403 // load sign-extended half-word
1404 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1406 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1407 uimm12s2:$offset)))]>;
1408 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1410 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1411 uimm12s2:$offset)))]>;
1413 // load sign-extended byte
1414 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1416 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1417 uimm12s1:$offset)))]>;
1418 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1420 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1421 uimm12s1:$offset)))]>;
1423 // load sign-extended word
1424 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1426 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1427 uimm12s4:$offset)))]>;
1429 // load zero-extended word
1430 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1431 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1434 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1435 [(ARM64Prefetch imm:$Rt,
1436 (am_indexed64 GPR64sp:$Rn,
1437 uimm12s8:$offset))]>;
1439 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1443 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1444 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1445 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1446 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1447 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1449 // load sign-extended word
1450 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1453 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1454 // [(ARM64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1457 // (unscaled immediate)
1458 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1460 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1461 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1463 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1464 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1466 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1467 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1469 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1470 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1471 [(set (f32 FPR32:$Rt),
1472 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1473 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1474 [(set (f64 FPR64:$Rt),
1475 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1476 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1477 [(set (f128 FPR128:$Rt),
1478 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1481 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1483 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1485 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1487 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1489 // Match all load 64 bits width whose type is compatible with FPR64
1490 let Predicates = [IsLE] in {
1491 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1492 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1493 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1494 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1495 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1496 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1497 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1498 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1500 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1501 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1502 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1503 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1505 // Match all load 128 bits width whose type is compatible with FPR128
1506 let Predicates = [IsLE] in {
1507 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1508 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1509 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1510 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1511 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1512 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1513 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1514 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1515 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1516 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1517 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1518 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1522 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1523 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1524 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1525 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1526 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1527 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1528 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1529 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1530 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1531 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1532 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1533 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1534 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1535 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1537 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1538 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1539 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1540 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1541 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1542 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1543 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1544 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1545 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1546 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1547 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1548 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1549 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1550 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1554 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1556 // Define new assembler match classes as we want to only match these when
1557 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1558 // associate a DiagnosticType either, as we want the diagnostic for the
1559 // canonical form (the scaled operand) to take precedence.
1560 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1561 let Name = "SImm9OffsetFB" # Width;
1562 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1563 let RenderMethod = "addImmOperands";
1566 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1567 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1568 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1569 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1570 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1572 def simm9_offset_fb8 : Operand<i64> {
1573 let ParserMatchClass = SImm9OffsetFB8Operand;
1575 def simm9_offset_fb16 : Operand<i64> {
1576 let ParserMatchClass = SImm9OffsetFB16Operand;
1578 def simm9_offset_fb32 : Operand<i64> {
1579 let ParserMatchClass = SImm9OffsetFB32Operand;
1581 def simm9_offset_fb64 : Operand<i64> {
1582 let ParserMatchClass = SImm9OffsetFB64Operand;
1584 def simm9_offset_fb128 : Operand<i64> {
1585 let ParserMatchClass = SImm9OffsetFB128Operand;
1588 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1589 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1590 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1591 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1592 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1593 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1594 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1595 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1596 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1597 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1598 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1599 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1600 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1601 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1604 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1605 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1606 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1607 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1609 // load sign-extended half-word
1611 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1613 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1615 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1617 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1619 // load sign-extended byte
1621 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1623 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1625 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1627 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1629 // load sign-extended word
1631 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1633 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1635 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1636 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1637 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1638 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1639 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1640 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1641 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1642 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1643 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1644 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1645 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1646 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1647 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1648 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1649 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1652 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1653 [(ARM64Prefetch imm:$Rt,
1654 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1657 // (unscaled immediate, unprivileged)
1658 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1659 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1661 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1662 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1664 // load sign-extended half-word
1665 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1666 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1668 // load sign-extended byte
1669 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1670 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1672 // load sign-extended word
1673 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1676 // (immediate pre-indexed)
1677 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1678 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1679 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1680 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1681 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1682 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1683 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1685 // load sign-extended half-word
1686 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1687 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1689 // load sign-extended byte
1690 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1691 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1693 // load zero-extended byte
1694 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1695 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1697 // load sign-extended word
1698 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1701 // (immediate post-indexed)
1702 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1703 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1704 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1705 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1706 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1707 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1708 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1710 // load sign-extended half-word
1711 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1712 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1714 // load sign-extended byte
1715 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1716 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1718 // load zero-extended byte
1719 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1720 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1722 // load sign-extended word
1723 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1725 //===----------------------------------------------------------------------===//
1726 // Store instructions.
1727 //===----------------------------------------------------------------------===//
1729 // Pair (indexed, offset)
1730 // FIXME: Use dedicated range-checked addressing mode operand here.
1731 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1732 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1733 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1734 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1735 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1737 // Pair (pre-indexed)
1738 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1739 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1740 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1741 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1742 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1744 // Pair (pre-indexed)
1745 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1746 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1747 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1748 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1749 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1751 // Pair (no allocate)
1752 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1753 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1754 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1755 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1756 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1759 // (Register offset)
1762 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1763 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1764 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1765 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1769 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1770 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1771 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1772 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1773 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1775 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1776 Instruction STRW, Instruction STRX> {
1778 def : Pat<(storeop GPR64:$Rt,
1779 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1780 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1781 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1783 def : Pat<(storeop GPR64:$Rt,
1784 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1785 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1786 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1789 let AddedComplexity = 10 in {
1791 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1792 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1793 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1796 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1797 Instruction STRW, Instruction STRX> {
1798 def : Pat<(store (VecTy FPR:$Rt),
1799 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1800 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1802 def : Pat<(store (VecTy FPR:$Rt),
1803 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1804 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1807 let AddedComplexity = 10 in {
1808 // Match all store 64 bits width whose type is compatible with FPR64
1809 let Predicates = [IsLE] in {
1810 // We must use ST1 to store vectors in big-endian.
1811 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1812 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1813 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1814 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1817 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1818 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1820 // Match all store 128 bits width whose type is compatible with FPR128
1821 let Predicates = [IsLE] in {
1822 // We must use ST1 to store vectors in big-endian.
1823 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1824 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1825 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1826 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
1827 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
1828 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
1830 } // AddedComplexity = 10
1833 // (unsigned immediate)
1834 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
1836 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1837 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
1839 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1840 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
1842 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
1843 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
1844 [(store (f16 FPR16:$Rt),
1845 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
1846 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
1847 [(store (f32 FPR32:$Rt),
1848 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1849 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
1850 [(store (f64 FPR64:$Rt),
1851 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1852 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
1854 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
1855 [(truncstorei16 GPR32:$Rt,
1856 (am_indexed16 GPR64sp:$Rn,
1857 uimm12s2:$offset))]>;
1858 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
1859 [(truncstorei8 GPR32:$Rt,
1860 (am_indexed8 GPR64sp:$Rn,
1861 uimm12s1:$offset))]>;
1863 // Match all store 64 bits width whose type is compatible with FPR64
1864 let AddedComplexity = 10 in {
1865 let Predicates = [IsLE] in {
1866 // We must use ST1 to store vectors in big-endian.
1867 def : Pat<(store (v2f32 FPR64:$Rt),
1868 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1869 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1870 def : Pat<(store (v8i8 FPR64:$Rt),
1871 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1872 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1873 def : Pat<(store (v4i16 FPR64:$Rt),
1874 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1875 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1876 def : Pat<(store (v2i32 FPR64:$Rt),
1877 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1878 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1880 def : Pat<(store (v1f64 FPR64:$Rt),
1881 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1882 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1883 def : Pat<(store (v1i64 FPR64:$Rt),
1884 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1885 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1887 // Match all store 128 bits width whose type is compatible with FPR128
1888 let Predicates = [IsLE] in {
1889 // We must use ST1 to store vectors in big-endian.
1890 def : Pat<(store (v4f32 FPR128:$Rt),
1891 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1892 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1893 def : Pat<(store (v2f64 FPR128:$Rt),
1894 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1895 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1896 def : Pat<(store (v16i8 FPR128:$Rt),
1897 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1898 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1899 def : Pat<(store (v8i16 FPR128:$Rt),
1900 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1901 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1902 def : Pat<(store (v4i32 FPR128:$Rt),
1903 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1904 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1905 def : Pat<(store (v2i64 FPR128:$Rt),
1906 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1907 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1909 def : Pat<(store (f128 FPR128:$Rt),
1910 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1911 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1914 def : Pat<(truncstorei32 GPR64:$Rt,
1915 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
1916 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
1917 def : Pat<(truncstorei16 GPR64:$Rt,
1918 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
1919 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
1920 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
1921 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
1923 } // AddedComplexity = 10
1926 // (unscaled immediate)
1927 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
1929 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1930 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
1932 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
1933 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
1935 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
1936 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
1937 [(store (f16 FPR16:$Rt),
1938 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
1939 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
1940 [(store (f32 FPR32:$Rt),
1941 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
1942 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
1943 [(store (f64 FPR64:$Rt),
1944 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1945 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
1946 [(store (f128 FPR128:$Rt),
1947 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
1948 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
1949 [(truncstorei16 GPR32:$Rt,
1950 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
1951 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
1952 [(truncstorei8 GPR32:$Rt,
1953 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
1955 // Match all store 64 bits width whose type is compatible with FPR64
1956 let Predicates = [IsLE] in {
1957 // We must use ST1 to store vectors in big-endian.
1958 def : Pat<(store (v2f32 FPR64:$Rt),
1959 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1960 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1961 def : Pat<(store (v8i8 FPR64:$Rt),
1962 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1963 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1964 def : Pat<(store (v4i16 FPR64:$Rt),
1965 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1966 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1967 def : Pat<(store (v2i32 FPR64:$Rt),
1968 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1969 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1971 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1972 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1973 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1974 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1976 // Match all store 128 bits width whose type is compatible with FPR128
1977 let Predicates = [IsLE] in {
1978 // We must use ST1 to store vectors in big-endian.
1979 def : Pat<(store (v4f32 FPR128:$Rt),
1980 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
1981 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1982 def : Pat<(store (v2f64 FPR128:$Rt),
1983 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
1984 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1985 def : Pat<(store (v16i8 FPR128:$Rt),
1986 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
1987 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1988 def : Pat<(store (v8i16 FPR128:$Rt),
1989 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
1990 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1991 def : Pat<(store (v4i32 FPR128:$Rt),
1992 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
1993 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1994 def : Pat<(store (v2i64 FPR128:$Rt),
1995 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
1996 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1997 def : Pat<(store (v2f64 FPR128:$Rt),
1998 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
1999 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2002 // unscaled i64 truncating stores
2003 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2004 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2005 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2006 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2007 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2008 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2011 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2012 def : InstAlias<"str $Rt, [$Rn, $offset]",
2013 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2014 def : InstAlias<"str $Rt, [$Rn, $offset]",
2015 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2016 def : InstAlias<"str $Rt, [$Rn, $offset]",
2017 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2018 def : InstAlias<"str $Rt, [$Rn, $offset]",
2019 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2020 def : InstAlias<"str $Rt, [$Rn, $offset]",
2021 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2022 def : InstAlias<"str $Rt, [$Rn, $offset]",
2023 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2024 def : InstAlias<"str $Rt, [$Rn, $offset]",
2025 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2027 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2028 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2029 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2030 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2033 // (unscaled immediate, unprivileged)
2034 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2035 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2037 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2038 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2041 // (immediate pre-indexed)
2042 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2043 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2044 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2045 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2046 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2047 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2048 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2050 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2051 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2054 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2055 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2057 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2058 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2060 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2061 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2064 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2065 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2066 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2067 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2068 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2069 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2070 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2071 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2072 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2073 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2074 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2075 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2077 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2078 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2079 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2080 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2081 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2082 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2083 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2084 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2085 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2086 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2087 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2088 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2091 // (immediate post-indexed)
2092 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2093 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2094 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2095 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2096 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2097 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2098 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2100 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2101 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2104 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2105 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2107 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2108 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2110 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2111 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2114 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2115 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2116 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2117 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2118 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2119 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2120 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2121 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2122 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2123 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2124 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2125 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2127 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2128 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2129 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2130 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2131 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2132 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2133 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2134 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2135 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2136 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2137 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2138 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2140 //===----------------------------------------------------------------------===//
2141 // Load/store exclusive instructions.
2142 //===----------------------------------------------------------------------===//
2144 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2145 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2146 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2147 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2149 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2150 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2151 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2152 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2154 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2155 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2156 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2157 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2159 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2160 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2161 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2162 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2164 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2165 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2166 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2167 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2169 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2170 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2171 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2172 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2174 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2175 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2177 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2178 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2180 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2181 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2183 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2184 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2186 //===----------------------------------------------------------------------===//
2187 // Scaled floating point to integer conversion instructions.
2188 //===----------------------------------------------------------------------===//
2190 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_arm64_neon_fcvtas>;
2191 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_arm64_neon_fcvtau>;
2192 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_arm64_neon_fcvtms>;
2193 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_arm64_neon_fcvtmu>;
2194 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_arm64_neon_fcvtns>;
2195 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_arm64_neon_fcvtnu>;
2196 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_arm64_neon_fcvtps>;
2197 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_arm64_neon_fcvtpu>;
2198 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2199 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2200 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2201 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2202 let isCodeGenOnly = 1 in {
2203 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
2204 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
2205 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
2206 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
2209 //===----------------------------------------------------------------------===//
2210 // Scaled integer to floating point conversion instructions.
2211 //===----------------------------------------------------------------------===//
2213 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2214 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2216 //===----------------------------------------------------------------------===//
2217 // Unscaled integer to floating point conversion instruction.
2218 //===----------------------------------------------------------------------===//
2220 defm FMOV : UnscaledConversion<"fmov">;
2222 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
2223 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
2225 //===----------------------------------------------------------------------===//
2226 // Floating point conversion instruction.
2227 //===----------------------------------------------------------------------===//
2229 defm FCVT : FPConversion<"fcvt">;
2231 def : Pat<(f32_to_f16 FPR32:$Rn),
2232 (i32 (COPY_TO_REGCLASS
2233 (f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
2236 def FCVTSHpseudo : Pseudo<(outs FPR32:$Rd), (ins FPR32:$Rn),
2237 [(set (f32 FPR32:$Rd), (f16_to_f32 i32:$Rn))]>;
2239 //===----------------------------------------------------------------------===//
2240 // Floating point single operand instructions.
2241 //===----------------------------------------------------------------------===//
2243 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2244 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2245 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2246 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2247 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2248 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2249 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_arm64_neon_frintn>;
2250 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2252 def : Pat<(v1f64 (int_arm64_neon_frintn (v1f64 FPR64:$Rn))),
2253 (FRINTNDr FPR64:$Rn)>;
2255 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2256 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2257 // <rdar://problem/13715968>
2258 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2259 let hasSideEffects = 1 in {
2260 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2263 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2265 let SchedRW = [WriteFDiv] in {
2266 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2269 //===----------------------------------------------------------------------===//
2270 // Floating point two operand instructions.
2271 //===----------------------------------------------------------------------===//
2273 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2274 let SchedRW = [WriteFDiv] in {
2275 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2277 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_arm64_neon_fmaxnm>;
2278 defm FMAX : TwoOperandFPData<0b0100, "fmax", ARM64fmax>;
2279 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_arm64_neon_fminnm>;
2280 defm FMIN : TwoOperandFPData<0b0101, "fmin", ARM64fmin>;
2281 let SchedRW = [WriteFMul] in {
2282 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2283 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2285 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2287 def : Pat<(v1f64 (ARM64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2288 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2289 def : Pat<(v1f64 (ARM64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2290 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2291 def : Pat<(v1f64 (int_arm64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2292 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2293 def : Pat<(v1f64 (int_arm64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2294 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2296 //===----------------------------------------------------------------------===//
2297 // Floating point three operand instructions.
2298 //===----------------------------------------------------------------------===//
2300 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2301 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2302 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2303 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2304 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2305 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2306 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2308 // The following def pats catch the case where the LHS of an FMA is negated.
2309 // The TriOpFrag above catches the case where the middle operand is negated.
2311 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2312 // the NEON variant.
2313 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2314 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2316 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2317 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2319 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2321 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2322 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2324 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2325 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2327 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2328 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2330 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2331 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2333 //===----------------------------------------------------------------------===//
2334 // Floating point comparison instructions.
2335 //===----------------------------------------------------------------------===//
2337 defm FCMPE : FPComparison<1, "fcmpe">;
2338 defm FCMP : FPComparison<0, "fcmp", ARM64fcmp>;
2340 //===----------------------------------------------------------------------===//
2341 // Floating point conditional comparison instructions.
2342 //===----------------------------------------------------------------------===//
2344 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2345 defm FCCMP : FPCondComparison<0, "fccmp">;
2347 //===----------------------------------------------------------------------===//
2348 // Floating point conditional select instruction.
2349 //===----------------------------------------------------------------------===//
2351 defm FCSEL : FPCondSelect<"fcsel">;
2353 // CSEL instructions providing f128 types need to be handled by a
2354 // pseudo-instruction since the eventual code will need to introduce basic
2355 // blocks and control flow.
2356 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2357 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2358 [(set (f128 FPR128:$Rd),
2359 (ARM64csel FPR128:$Rn, FPR128:$Rm,
2360 (i32 imm:$cond), NZCV))]> {
2362 let usesCustomInserter = 1;
2366 //===----------------------------------------------------------------------===//
2367 // Floating point immediate move.
2368 //===----------------------------------------------------------------------===//
2370 let isReMaterializable = 1 in {
2371 defm FMOV : FPMoveImmediate<"fmov">;
2374 //===----------------------------------------------------------------------===//
2375 // Advanced SIMD two vector instructions.
2376 //===----------------------------------------------------------------------===//
2378 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_arm64_neon_abs>;
2379 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_arm64_neon_cls>;
2380 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2381 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", ARM64cmeqz>;
2382 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", ARM64cmgez>;
2383 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", ARM64cmgtz>;
2384 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", ARM64cmlez>;
2385 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", ARM64cmltz>;
2386 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2387 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2389 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2390 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2391 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2392 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2393 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2394 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_arm64_neon_fcvtas>;
2395 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_arm64_neon_fcvtau>;
2396 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2397 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2398 (FCVTLv4i16 V64:$Rn)>;
2399 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2401 (FCVTLv8i16 V128:$Rn)>;
2402 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2403 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2405 (FCVTLv4i32 V128:$Rn)>;
2407 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_arm64_neon_fcvtms>;
2408 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_arm64_neon_fcvtmu>;
2409 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_arm64_neon_fcvtns>;
2410 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_arm64_neon_fcvtnu>;
2411 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2412 def : Pat<(v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2413 (FCVTNv4i16 V128:$Rn)>;
2414 def : Pat<(concat_vectors V64:$Rd,
2415 (v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2416 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2417 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2418 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2419 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2420 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_arm64_neon_fcvtps>;
2421 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_arm64_neon_fcvtpu>;
2422 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2423 int_arm64_neon_fcvtxn>;
2424 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2425 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2426 let isCodeGenOnly = 1 in {
2427 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2428 int_arm64_neon_fcvtzs>;
2429 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2430 int_arm64_neon_fcvtzu>;
2432 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2433 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_arm64_neon_frecpe>;
2434 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2435 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2436 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2437 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_arm64_neon_frintn>;
2438 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2439 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2440 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2441 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_arm64_neon_frsqrte>;
2442 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2443 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2444 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2445 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2446 // Aliases for MVN -> NOT.
2447 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2448 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2449 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2450 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2452 def : Pat<(ARM64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2453 def : Pat<(ARM64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2454 def : Pat<(ARM64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2455 def : Pat<(ARM64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2456 def : Pat<(ARM64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2457 def : Pat<(ARM64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2458 def : Pat<(ARM64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2460 def : Pat<(ARM64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2461 def : Pat<(ARM64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2462 def : Pat<(ARM64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2463 def : Pat<(ARM64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2464 def : Pat<(ARM64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2465 def : Pat<(ARM64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2466 def : Pat<(ARM64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2467 def : Pat<(ARM64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2469 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2470 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2471 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2472 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2473 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2475 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_arm64_neon_rbit>;
2476 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", ARM64rev16>;
2477 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", ARM64rev32>;
2478 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", ARM64rev64>;
2479 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2480 BinOpFrag<(add node:$LHS, (int_arm64_neon_saddlp node:$RHS))> >;
2481 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_arm64_neon_saddlp>;
2482 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2483 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2484 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2485 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2486 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_arm64_neon_sqxtn>;
2487 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_arm64_neon_sqxtun>;
2488 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_arm64_neon_suqadd>;
2489 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2490 BinOpFrag<(add node:$LHS, (int_arm64_neon_uaddlp node:$RHS))> >;
2491 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2492 int_arm64_neon_uaddlp>;
2493 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2494 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_arm64_neon_uqxtn>;
2495 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_arm64_neon_urecpe>;
2496 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_arm64_neon_ursqrte>;
2497 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_arm64_neon_usqadd>;
2498 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2500 def : Pat<(v2f32 (ARM64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2501 def : Pat<(v4f32 (ARM64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2503 // Patterns for vector long shift (by element width). These need to match all
2504 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2506 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2507 def : Pat<(ARM64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2508 (SHLLv8i8 V64:$Rn)>;
2509 def : Pat<(ARM64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2510 (SHLLv16i8 V128:$Rn)>;
2511 def : Pat<(ARM64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2512 (SHLLv4i16 V64:$Rn)>;
2513 def : Pat<(ARM64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2514 (SHLLv8i16 V128:$Rn)>;
2515 def : Pat<(ARM64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2516 (SHLLv2i32 V64:$Rn)>;
2517 def : Pat<(ARM64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2518 (SHLLv4i32 V128:$Rn)>;
2521 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2522 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2523 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2525 //===----------------------------------------------------------------------===//
2526 // Advanced SIMD three vector instructions.
2527 //===----------------------------------------------------------------------===//
2529 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2530 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_arm64_neon_addp>;
2531 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", ARM64cmeq>;
2532 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", ARM64cmge>;
2533 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", ARM64cmgt>;
2534 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", ARM64cmhi>;
2535 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", ARM64cmhs>;
2536 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", ARM64cmtst>;
2537 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_arm64_neon_fabd>;
2538 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_arm64_neon_facge>;
2539 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_arm64_neon_facgt>;
2540 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_arm64_neon_addp>;
2541 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2542 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2543 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2544 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2545 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2546 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_arm64_neon_fmaxnmp>;
2547 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_arm64_neon_fmaxnm>;
2548 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_arm64_neon_fmaxp>;
2549 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", ARM64fmax>;
2550 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_arm64_neon_fminnmp>;
2551 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_arm64_neon_fminnm>;
2552 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_arm64_neon_fminp>;
2553 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", ARM64fmin>;
2555 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2556 // instruction expects the addend first, while the fma intrinsic puts it last.
2557 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2558 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2559 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2560 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2562 // The following def pats catch the case where the LHS of an FMA is negated.
2563 // The TriOpFrag above catches the case where the middle operand is negated.
2564 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2565 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2567 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2568 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2570 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2571 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2573 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_arm64_neon_fmulx>;
2574 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2575 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_arm64_neon_frecps>;
2576 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_arm64_neon_frsqrts>;
2577 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2578 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2579 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2580 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2581 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2582 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2583 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_arm64_neon_pmul>;
2584 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2585 TriOpFrag<(add node:$LHS, (int_arm64_neon_sabd node:$MHS, node:$RHS))> >;
2586 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_arm64_neon_sabd>;
2587 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_arm64_neon_shadd>;
2588 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_arm64_neon_shsub>;
2589 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_arm64_neon_smaxp>;
2590 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_arm64_neon_smax>;
2591 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_arm64_neon_sminp>;
2592 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_arm64_neon_smin>;
2593 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_arm64_neon_sqadd>;
2594 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_arm64_neon_sqdmulh>;
2595 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_arm64_neon_sqrdmulh>;
2596 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_arm64_neon_sqrshl>;
2597 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_arm64_neon_sqshl>;
2598 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_arm64_neon_sqsub>;
2599 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_arm64_neon_srhadd>;
2600 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_arm64_neon_srshl>;
2601 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_arm64_neon_sshl>;
2602 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2603 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2604 TriOpFrag<(add node:$LHS, (int_arm64_neon_uabd node:$MHS, node:$RHS))> >;
2605 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_arm64_neon_uabd>;
2606 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_arm64_neon_uhadd>;
2607 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_arm64_neon_uhsub>;
2608 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_arm64_neon_umaxp>;
2609 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_arm64_neon_umax>;
2610 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_arm64_neon_uminp>;
2611 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_arm64_neon_umin>;
2612 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_arm64_neon_uqadd>;
2613 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_arm64_neon_uqrshl>;
2614 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_arm64_neon_uqshl>;
2615 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_arm64_neon_uqsub>;
2616 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_arm64_neon_urhadd>;
2617 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_arm64_neon_urshl>;
2618 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_arm64_neon_ushl>;
2620 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2621 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2622 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2623 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2624 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", ARM64bit>;
2625 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2626 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2627 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2628 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2629 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2630 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2632 def : Pat<(ARM64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2633 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2634 def : Pat<(ARM64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2635 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2636 def : Pat<(ARM64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2637 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2638 def : Pat<(ARM64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2639 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2641 def : Pat<(ARM64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2642 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2643 def : Pat<(ARM64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2644 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2645 def : Pat<(ARM64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2646 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2647 def : Pat<(ARM64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2648 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2650 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2651 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2652 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2653 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2654 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2655 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2656 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2657 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2659 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2660 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2661 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2662 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2663 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2664 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2665 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2666 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2668 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2669 "|cmls.8b\t$dst, $src1, $src2}",
2670 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2671 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2672 "|cmls.16b\t$dst, $src1, $src2}",
2673 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2674 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2675 "|cmls.4h\t$dst, $src1, $src2}",
2676 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2677 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2678 "|cmls.8h\t$dst, $src1, $src2}",
2679 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2680 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2681 "|cmls.2s\t$dst, $src1, $src2}",
2682 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2683 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2684 "|cmls.4s\t$dst, $src1, $src2}",
2685 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2686 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2687 "|cmls.2d\t$dst, $src1, $src2}",
2688 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2690 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2691 "|cmlo.8b\t$dst, $src1, $src2}",
2692 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2693 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2694 "|cmlo.16b\t$dst, $src1, $src2}",
2695 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2696 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2697 "|cmlo.4h\t$dst, $src1, $src2}",
2698 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2699 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2700 "|cmlo.8h\t$dst, $src1, $src2}",
2701 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2702 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2703 "|cmlo.2s\t$dst, $src1, $src2}",
2704 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2705 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2706 "|cmlo.4s\t$dst, $src1, $src2}",
2707 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2708 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2709 "|cmlo.2d\t$dst, $src1, $src2}",
2710 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2712 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2713 "|cmle.8b\t$dst, $src1, $src2}",
2714 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2715 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2716 "|cmle.16b\t$dst, $src1, $src2}",
2717 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2718 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2719 "|cmle.4h\t$dst, $src1, $src2}",
2720 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2721 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2722 "|cmle.8h\t$dst, $src1, $src2}",
2723 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2724 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2725 "|cmle.2s\t$dst, $src1, $src2}",
2726 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2727 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2728 "|cmle.4s\t$dst, $src1, $src2}",
2729 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2730 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2731 "|cmle.2d\t$dst, $src1, $src2}",
2732 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2734 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2735 "|cmlt.8b\t$dst, $src1, $src2}",
2736 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2737 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2738 "|cmlt.16b\t$dst, $src1, $src2}",
2739 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2740 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2741 "|cmlt.4h\t$dst, $src1, $src2}",
2742 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2743 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2744 "|cmlt.8h\t$dst, $src1, $src2}",
2745 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2746 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2747 "|cmlt.2s\t$dst, $src1, $src2}",
2748 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2749 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2750 "|cmlt.4s\t$dst, $src1, $src2}",
2751 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2752 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2753 "|cmlt.2d\t$dst, $src1, $src2}",
2754 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2756 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2757 "|fcmle.2s\t$dst, $src1, $src2}",
2758 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2759 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2760 "|fcmle.4s\t$dst, $src1, $src2}",
2761 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2762 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2763 "|fcmle.2d\t$dst, $src1, $src2}",
2764 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2766 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2767 "|fcmlt.2s\t$dst, $src1, $src2}",
2768 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2769 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2770 "|fcmlt.4s\t$dst, $src1, $src2}",
2771 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2772 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2773 "|fcmlt.2d\t$dst, $src1, $src2}",
2774 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2776 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2777 "|facle.2s\t$dst, $src1, $src2}",
2778 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2779 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2780 "|facle.4s\t$dst, $src1, $src2}",
2781 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2782 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2783 "|facle.2d\t$dst, $src1, $src2}",
2784 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2786 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2787 "|faclt.2s\t$dst, $src1, $src2}",
2788 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2789 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2790 "|faclt.4s\t$dst, $src1, $src2}",
2791 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2792 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2793 "|faclt.2d\t$dst, $src1, $src2}",
2794 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2796 //===----------------------------------------------------------------------===//
2797 // Advanced SIMD three scalar instructions.
2798 //===----------------------------------------------------------------------===//
2800 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2801 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", ARM64cmeq>;
2802 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", ARM64cmge>;
2803 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", ARM64cmgt>;
2804 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", ARM64cmhi>;
2805 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", ARM64cmhs>;
2806 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", ARM64cmtst>;
2807 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_arm64_sisd_fabd>;
2808 def : Pat<(v1f64 (int_arm64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2809 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2810 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2811 int_arm64_neon_facge>;
2812 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2813 int_arm64_neon_facgt>;
2814 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2815 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2816 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2817 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_arm64_neon_fmulx>;
2818 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_arm64_neon_frecps>;
2819 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_arm64_neon_frsqrts>;
2820 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_arm64_neon_sqadd>;
2821 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_arm64_neon_sqdmulh>;
2822 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_arm64_neon_sqrdmulh>;
2823 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_arm64_neon_sqrshl>;
2824 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_arm64_neon_sqshl>;
2825 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_arm64_neon_sqsub>;
2826 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_arm64_neon_srshl>;
2827 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_arm64_neon_sshl>;
2828 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2829 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_arm64_neon_uqadd>;
2830 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_arm64_neon_uqrshl>;
2831 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_arm64_neon_uqshl>;
2832 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_arm64_neon_uqsub>;
2833 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_arm64_neon_urshl>;
2834 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_arm64_neon_ushl>;
2836 def : InstAlias<"cmls $dst, $src1, $src2",
2837 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2838 def : InstAlias<"cmle $dst, $src1, $src2",
2839 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2840 def : InstAlias<"cmlo $dst, $src1, $src2",
2841 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2842 def : InstAlias<"cmlt $dst, $src1, $src2",
2843 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2844 def : InstAlias<"fcmle $dst, $src1, $src2",
2845 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2846 def : InstAlias<"fcmle $dst, $src1, $src2",
2847 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2848 def : InstAlias<"fcmlt $dst, $src1, $src2",
2849 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2850 def : InstAlias<"fcmlt $dst, $src1, $src2",
2851 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2852 def : InstAlias<"facle $dst, $src1, $src2",
2853 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2854 def : InstAlias<"facle $dst, $src1, $src2",
2855 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2856 def : InstAlias<"faclt $dst, $src1, $src2",
2857 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2858 def : InstAlias<"faclt $dst, $src1, $src2",
2859 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2861 //===----------------------------------------------------------------------===//
2862 // Advanced SIMD three scalar instructions (mixed operands).
2863 //===----------------------------------------------------------------------===//
2864 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2865 int_arm64_neon_sqdmulls_scalar>;
2866 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2867 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
2869 def : Pat<(i64 (int_arm64_neon_sqadd (i64 FPR64:$Rd),
2870 (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2871 (i32 FPR32:$Rm))))),
2872 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2873 def : Pat<(i64 (int_arm64_neon_sqsub (i64 FPR64:$Rd),
2874 (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2875 (i32 FPR32:$Rm))))),
2876 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2878 //===----------------------------------------------------------------------===//
2879 // Advanced SIMD two scalar instructions.
2880 //===----------------------------------------------------------------------===//
2882 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_arm64_neon_abs>;
2883 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", ARM64cmeqz>;
2884 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", ARM64cmgez>;
2885 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", ARM64cmgtz>;
2886 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", ARM64cmlez>;
2887 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", ARM64cmltz>;
2888 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2889 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2890 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2891 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2892 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2893 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
2894 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
2895 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
2896 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
2897 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
2898 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
2899 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
2900 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
2901 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
2902 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
2903 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
2904 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
2905 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
2906 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
2907 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
2908 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2909 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", ARM64sitof>;
2910 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2911 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2912 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_arm64_neon_scalar_sqxtn>;
2913 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_arm64_neon_scalar_sqxtun>;
2914 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
2915 int_arm64_neon_suqadd>;
2916 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", ARM64uitof>;
2917 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_arm64_neon_scalar_uqxtn>;
2918 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
2919 int_arm64_neon_usqadd>;
2921 def : Pat<(ARM64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
2923 def : Pat<(v1i64 (int_arm64_neon_fcvtas (v1f64 FPR64:$Rn))),
2924 (FCVTASv1i64 FPR64:$Rn)>;
2925 def : Pat<(v1i64 (int_arm64_neon_fcvtau (v1f64 FPR64:$Rn))),
2926 (FCVTAUv1i64 FPR64:$Rn)>;
2927 def : Pat<(v1i64 (int_arm64_neon_fcvtms (v1f64 FPR64:$Rn))),
2928 (FCVTMSv1i64 FPR64:$Rn)>;
2929 def : Pat<(v1i64 (int_arm64_neon_fcvtmu (v1f64 FPR64:$Rn))),
2930 (FCVTMUv1i64 FPR64:$Rn)>;
2931 def : Pat<(v1i64 (int_arm64_neon_fcvtns (v1f64 FPR64:$Rn))),
2932 (FCVTNSv1i64 FPR64:$Rn)>;
2933 def : Pat<(v1i64 (int_arm64_neon_fcvtnu (v1f64 FPR64:$Rn))),
2934 (FCVTNUv1i64 FPR64:$Rn)>;
2935 def : Pat<(v1i64 (int_arm64_neon_fcvtps (v1f64 FPR64:$Rn))),
2936 (FCVTPSv1i64 FPR64:$Rn)>;
2937 def : Pat<(v1i64 (int_arm64_neon_fcvtpu (v1f64 FPR64:$Rn))),
2938 (FCVTPUv1i64 FPR64:$Rn)>;
2940 def : Pat<(f32 (int_arm64_neon_frecpe (f32 FPR32:$Rn))),
2941 (FRECPEv1i32 FPR32:$Rn)>;
2942 def : Pat<(f64 (int_arm64_neon_frecpe (f64 FPR64:$Rn))),
2943 (FRECPEv1i64 FPR64:$Rn)>;
2944 def : Pat<(v1f64 (int_arm64_neon_frecpe (v1f64 FPR64:$Rn))),
2945 (FRECPEv1i64 FPR64:$Rn)>;
2947 def : Pat<(f32 (int_arm64_neon_frecpx (f32 FPR32:$Rn))),
2948 (FRECPXv1i32 FPR32:$Rn)>;
2949 def : Pat<(f64 (int_arm64_neon_frecpx (f64 FPR64:$Rn))),
2950 (FRECPXv1i64 FPR64:$Rn)>;
2952 def : Pat<(f32 (int_arm64_neon_frsqrte (f32 FPR32:$Rn))),
2953 (FRSQRTEv1i32 FPR32:$Rn)>;
2954 def : Pat<(f64 (int_arm64_neon_frsqrte (f64 FPR64:$Rn))),
2955 (FRSQRTEv1i64 FPR64:$Rn)>;
2956 def : Pat<(v1f64 (int_arm64_neon_frsqrte (v1f64 FPR64:$Rn))),
2957 (FRSQRTEv1i64 FPR64:$Rn)>;
2959 // If an integer is about to be converted to a floating point value,
2960 // just load it on the floating point unit.
2961 // Here are the patterns for 8 and 16-bits to float.
2963 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
2964 SDPatternOperator loadop, Instruction UCVTF,
2965 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
2967 def : Pat<(DstTy (uint_to_fp (SrcTy
2968 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
2969 ro.Wext:$extend))))),
2970 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
2971 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
2974 def : Pat<(DstTy (uint_to_fp (SrcTy
2975 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
2976 ro.Wext:$extend))))),
2977 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
2978 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
2982 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
2983 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
2984 def : Pat <(f32 (uint_to_fp (i32
2985 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
2986 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2987 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
2988 def : Pat <(f32 (uint_to_fp (i32
2989 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
2990 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2991 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
2992 // 16-bits -> float.
2993 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
2994 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
2995 def : Pat <(f32 (uint_to_fp (i32
2996 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
2997 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2998 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
2999 def : Pat <(f32 (uint_to_fp (i32
3000 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3001 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3002 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3003 // 32-bits are handled in target specific dag combine:
3004 // performIntToFpCombine.
3005 // 64-bits integer to 32-bits floating point, not possible with
3006 // UCVTF on floating point registers (both source and destination
3007 // must have the same size).
3009 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3010 // 8-bits -> double.
3011 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3012 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3013 def : Pat <(f64 (uint_to_fp (i32
3014 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3015 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3016 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3017 def : Pat <(f64 (uint_to_fp (i32
3018 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3019 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3020 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3021 // 16-bits -> double.
3022 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3023 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3024 def : Pat <(f64 (uint_to_fp (i32
3025 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3026 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3027 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3028 def : Pat <(f64 (uint_to_fp (i32
3029 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3030 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3031 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3032 // 32-bits -> double.
3033 defm : UIntToFPROLoadPat<f64, i32, load,
3034 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3035 def : Pat <(f64 (uint_to_fp (i32
3036 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3037 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3038 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3039 def : Pat <(f64 (uint_to_fp (i32
3040 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3041 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3042 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3043 // 64-bits -> double are handled in target specific dag combine:
3044 // performIntToFpCombine.
3046 //===----------------------------------------------------------------------===//
3047 // Advanced SIMD three different-sized vector instructions.
3048 //===----------------------------------------------------------------------===//
3050 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_arm64_neon_addhn>;
3051 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_arm64_neon_subhn>;
3052 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_arm64_neon_raddhn>;
3053 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_arm64_neon_rsubhn>;
3054 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_arm64_neon_pmull>;
3055 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3056 int_arm64_neon_sabd>;
3057 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3058 int_arm64_neon_sabd>;
3059 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3060 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3061 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3062 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3063 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3064 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3065 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3066 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3067 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_arm64_neon_smull>;
3068 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3069 int_arm64_neon_sqadd>;
3070 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3071 int_arm64_neon_sqsub>;
3072 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3073 int_arm64_neon_sqdmull>;
3074 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3075 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3076 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3077 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3078 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3079 int_arm64_neon_uabd>;
3080 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3081 int_arm64_neon_uabd>;
3082 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3083 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3084 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3085 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3086 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3087 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3088 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3089 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3090 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_arm64_neon_umull>;
3091 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3092 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3093 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3094 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3096 // Patterns for 64-bit pmull
3097 def : Pat<(int_arm64_neon_pmull64 V64:$Rn, V64:$Rm),
3098 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3099 def : Pat<(int_arm64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3100 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3101 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3103 // CodeGen patterns for addhn and subhn instructions, which can actually be
3104 // written in LLVM IR without too much difficulty.
3107 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3108 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3109 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
3111 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3112 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
3114 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3115 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3116 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm),
3118 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3119 V128:$Rn, V128:$Rm)>;
3120 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3121 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
3123 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3124 V128:$Rn, V128:$Rm)>;
3125 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3126 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
3128 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3129 V128:$Rn, V128:$Rm)>;
3132 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3133 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3134 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
3136 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3137 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
3139 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3140 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3141 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
3143 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3144 V128:$Rn, V128:$Rm)>;
3145 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3146 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
3148 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3149 V128:$Rn, V128:$Rm)>;
3150 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3151 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
3153 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3154 V128:$Rn, V128:$Rm)>;
3156 //----------------------------------------------------------------------------
3157 // AdvSIMD bitwise extract from vector instruction.
3158 //----------------------------------------------------------------------------
3160 defm EXT : SIMDBitwiseExtract<"ext">;
3162 def : Pat<(v4i16 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3163 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3164 def : Pat<(v8i16 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3165 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3166 def : Pat<(v2i32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3167 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3168 def : Pat<(v2f32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3169 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3170 def : Pat<(v4i32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3171 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3172 def : Pat<(v4f32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3173 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3174 def : Pat<(v2i64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3175 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3176 def : Pat<(v2f64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3177 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3179 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3181 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3182 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3183 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3184 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3185 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3186 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3187 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3188 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3189 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3190 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3191 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3192 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3195 //----------------------------------------------------------------------------
3196 // AdvSIMD zip vector
3197 //----------------------------------------------------------------------------
3199 defm TRN1 : SIMDZipVector<0b010, "trn1", ARM64trn1>;
3200 defm TRN2 : SIMDZipVector<0b110, "trn2", ARM64trn2>;
3201 defm UZP1 : SIMDZipVector<0b001, "uzp1", ARM64uzp1>;
3202 defm UZP2 : SIMDZipVector<0b101, "uzp2", ARM64uzp2>;
3203 defm ZIP1 : SIMDZipVector<0b011, "zip1", ARM64zip1>;
3204 defm ZIP2 : SIMDZipVector<0b111, "zip2", ARM64zip2>;
3206 //----------------------------------------------------------------------------
3207 // AdvSIMD TBL/TBX instructions
3208 //----------------------------------------------------------------------------
3210 defm TBL : SIMDTableLookup< 0, "tbl">;
3211 defm TBX : SIMDTableLookupTied<1, "tbx">;
3213 def : Pat<(v8i8 (int_arm64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3214 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3215 def : Pat<(v16i8 (int_arm64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3216 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3218 def : Pat<(v8i8 (int_arm64_neon_tbx1 (v8i8 V64:$Rd),
3219 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3220 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3221 def : Pat<(v16i8 (int_arm64_neon_tbx1 (v16i8 V128:$Rd),
3222 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3223 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3226 //----------------------------------------------------------------------------
3227 // AdvSIMD scalar CPY instruction
3228 //----------------------------------------------------------------------------
3230 defm CPY : SIMDScalarCPY<"cpy">;
3232 //----------------------------------------------------------------------------
3233 // AdvSIMD scalar pairwise instructions
3234 //----------------------------------------------------------------------------
3236 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3237 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
3238 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
3239 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
3240 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
3241 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
3242 def : Pat<(i64 (int_arm64_neon_saddv (v2i64 V128:$Rn))),
3243 (ADDPv2i64p V128:$Rn)>;
3244 def : Pat<(i64 (int_arm64_neon_uaddv (v2i64 V128:$Rn))),
3245 (ADDPv2i64p V128:$Rn)>;
3246 def : Pat<(f32 (int_arm64_neon_faddv (v2f32 V64:$Rn))),
3247 (FADDPv2i32p V64:$Rn)>;
3248 def : Pat<(f32 (int_arm64_neon_faddv (v4f32 V128:$Rn))),
3249 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3250 def : Pat<(f64 (int_arm64_neon_faddv (v2f64 V128:$Rn))),
3251 (FADDPv2i64p V128:$Rn)>;
3252 def : Pat<(f32 (int_arm64_neon_fmaxnmv (v2f32 V64:$Rn))),
3253 (FMAXNMPv2i32p V64:$Rn)>;
3254 def : Pat<(f64 (int_arm64_neon_fmaxnmv (v2f64 V128:$Rn))),
3255 (FMAXNMPv2i64p V128:$Rn)>;
3256 def : Pat<(f32 (int_arm64_neon_fmaxv (v2f32 V64:$Rn))),
3257 (FMAXPv2i32p V64:$Rn)>;
3258 def : Pat<(f64 (int_arm64_neon_fmaxv (v2f64 V128:$Rn))),
3259 (FMAXPv2i64p V128:$Rn)>;
3260 def : Pat<(f32 (int_arm64_neon_fminnmv (v2f32 V64:$Rn))),
3261 (FMINNMPv2i32p V64:$Rn)>;
3262 def : Pat<(f64 (int_arm64_neon_fminnmv (v2f64 V128:$Rn))),
3263 (FMINNMPv2i64p V128:$Rn)>;
3264 def : Pat<(f32 (int_arm64_neon_fminv (v2f32 V64:$Rn))),
3265 (FMINPv2i32p V64:$Rn)>;
3266 def : Pat<(f64 (int_arm64_neon_fminv (v2f64 V128:$Rn))),
3267 (FMINPv2i64p V128:$Rn)>;
3269 //----------------------------------------------------------------------------
3270 // AdvSIMD INS/DUP instructions
3271 //----------------------------------------------------------------------------
3273 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
3274 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
3275 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
3276 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
3277 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
3278 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
3279 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
3281 def DUPv2i64lane : SIMDDup64FromElement;
3282 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3283 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3284 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3285 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3286 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3287 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3289 def : Pat<(v2f32 (ARM64dup (f32 FPR32:$Rn))),
3290 (v2f32 (DUPv2i32lane
3291 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3293 def : Pat<(v4f32 (ARM64dup (f32 FPR32:$Rn))),
3294 (v4f32 (DUPv4i32lane
3295 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3297 def : Pat<(v2f64 (ARM64dup (f64 FPR64:$Rn))),
3298 (v2f64 (DUPv2i64lane
3299 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3302 def : Pat<(v2f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3303 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3304 def : Pat<(v4f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3305 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3306 def : Pat<(v2f64 (ARM64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3307 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3309 // If there's an (ARM64dup (vector_extract ...) ...), we can use a duplane
3310 // instruction even if the types don't match: we just have to remap the lane
3311 // carefully. N.b. this trick only applies to truncations.
3312 def VecIndex_x2 : SDNodeXForm<imm, [{
3313 return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
3315 def VecIndex_x4 : SDNodeXForm<imm, [{
3316 return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
3318 def VecIndex_x8 : SDNodeXForm<imm, [{
3319 return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
3322 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3323 ValueType Src128VT, ValueType ScalVT,
3324 Instruction DUP, SDNodeXForm IdxXFORM> {
3325 def : Pat<(ResVT (ARM64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3327 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3329 def : Pat<(ResVT (ARM64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3331 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3334 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3335 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3336 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3338 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3339 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3340 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3342 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3343 SDNodeXForm IdxXFORM> {
3344 def : Pat<(ResVT (ARM64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3346 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3348 def : Pat<(ResVT (ARM64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3350 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3353 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3354 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3355 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3357 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3358 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3359 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3361 // SMOV and UMOV definitions, with some extra patterns for convenience
3365 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3366 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3367 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3368 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3369 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3370 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3371 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3372 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3373 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3374 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3375 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3376 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3378 // Extracting i8 or i16 elements will have the zero-extend transformed to
3379 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3380 // for ARM64. Match these patterns here since UMOV already zeroes out the high
3381 // bits of the destination register.
3382 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3384 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3385 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3387 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3391 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3392 (SUBREG_TO_REG (i32 0),
3393 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3394 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3395 (SUBREG_TO_REG (i32 0),
3396 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3398 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3399 (SUBREG_TO_REG (i32 0),
3400 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3401 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3402 (SUBREG_TO_REG (i32 0),
3403 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3405 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3406 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3407 (i32 FPR32:$Rn), ssub))>;
3408 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3409 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3410 (i32 FPR32:$Rn), ssub))>;
3411 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3412 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3413 (i64 FPR64:$Rn), dsub))>;
3415 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3416 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3417 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3418 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3419 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3420 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3422 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3423 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3426 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3428 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3431 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3432 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3434 V128:$Rn, VectorIndexS:$imm,
3435 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3437 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3438 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3440 V128:$Rn, VectorIndexD:$imm,
3441 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3444 // Copy an element at a constant index in one vector into a constant indexed
3445 // element of another.
3446 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3447 // index type and INS extension
3448 def : Pat<(v16i8 (int_arm64_neon_vcopy_lane
3449 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3450 VectorIndexB:$idx2)),
3452 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3454 def : Pat<(v8i16 (int_arm64_neon_vcopy_lane
3455 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3456 VectorIndexH:$idx2)),
3458 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3460 def : Pat<(v4i32 (int_arm64_neon_vcopy_lane
3461 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3462 VectorIndexS:$idx2)),
3464 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3466 def : Pat<(v2i64 (int_arm64_neon_vcopy_lane
3467 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3468 VectorIndexD:$idx2)),
3470 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3473 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3474 ValueType VTScal, Instruction INS> {
3475 def : Pat<(VT128 (vector_insert V128:$src,
3476 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3478 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3480 def : Pat<(VT128 (vector_insert V128:$src,
3481 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3483 (INS V128:$src, imm:$Immd,
3484 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3486 def : Pat<(VT64 (vector_insert V64:$src,
3487 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3489 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3490 imm:$Immd, V128:$Rn, imm:$Immn),
3493 def : Pat<(VT64 (vector_insert V64:$src,
3494 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3497 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3498 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3502 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3503 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3504 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, INSvi8lane>;
3505 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
3506 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
3507 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi32lane>;
3510 // Floating point vector extractions are codegen'd as either a sequence of
3511 // subregister extractions, possibly fed by an INS if the lane number is
3512 // anything other than zero.
3513 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3514 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3515 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3516 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3517 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3518 (f64 (EXTRACT_SUBREG
3519 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3520 V128:$Rn, VectorIndexD:$idx),
3522 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3523 (f32 (EXTRACT_SUBREG
3524 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3525 V128:$Rn, VectorIndexS:$idx),
3528 // All concat_vectors operations are canonicalised to act on i64 vectors for
3529 // ARM64. In the general case we need an instruction, which had just as well be
3531 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3532 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3533 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3534 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3536 def : ConcatPat<v2i64, v1i64>;
3537 def : ConcatPat<v2f64, v1f64>;
3538 def : ConcatPat<v4i32, v2i32>;
3539 def : ConcatPat<v4f32, v2f32>;
3540 def : ConcatPat<v8i16, v4i16>;
3541 def : ConcatPat<v16i8, v8i8>;
3543 // If the high lanes are undef, though, we can just ignore them:
3544 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3545 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3546 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3548 def : ConcatUndefPat<v2i64, v1i64>;
3549 def : ConcatUndefPat<v2f64, v1f64>;
3550 def : ConcatUndefPat<v4i32, v2i32>;
3551 def : ConcatUndefPat<v4f32, v2f32>;
3552 def : ConcatUndefPat<v8i16, v4i16>;
3553 def : ConcatUndefPat<v16i8, v8i8>;
3555 //----------------------------------------------------------------------------
3556 // AdvSIMD across lanes instructions
3557 //----------------------------------------------------------------------------
3559 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3560 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3561 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3562 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3563 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3564 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3565 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3566 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_arm64_neon_fmaxnmv>;
3567 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_arm64_neon_fmaxv>;
3568 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_arm64_neon_fminnmv>;
3569 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_arm64_neon_fminv>;
3571 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3572 // If there is a sign extension after this intrinsic, consume it as smov already
3574 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3576 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3577 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3579 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3581 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3582 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3584 // If there is a sign extension after this intrinsic, consume it as smov already
3586 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3588 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3589 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3591 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3593 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3594 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3596 // If there is a sign extension after this intrinsic, consume it as smov already
3598 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3600 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3601 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3603 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3605 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3606 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3608 // If there is a sign extension after this intrinsic, consume it as smov already
3610 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3612 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3613 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3615 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3617 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3618 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3621 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3622 (i32 (EXTRACT_SUBREG
3623 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3624 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3628 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3629 // If there is a masking operation keeping only what has been actually
3630 // generated, consume it.
3631 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3632 (i32 (EXTRACT_SUBREG
3633 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3634 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3636 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3637 (i32 (EXTRACT_SUBREG
3638 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3639 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3641 // If there is a masking operation keeping only what has been actually
3642 // generated, consume it.
3643 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3644 (i32 (EXTRACT_SUBREG
3645 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3646 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3648 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3649 (i32 (EXTRACT_SUBREG
3650 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3651 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3654 // If there is a masking operation keeping only what has been actually
3655 // generated, consume it.
3656 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3657 (i32 (EXTRACT_SUBREG
3658 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3659 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3661 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3662 (i32 (EXTRACT_SUBREG
3663 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3664 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3666 // If there is a masking operation keeping only what has been actually
3667 // generated, consume it.
3668 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3669 (i32 (EXTRACT_SUBREG
3670 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3671 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3673 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3674 (i32 (EXTRACT_SUBREG
3675 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3676 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3679 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3680 (i32 (EXTRACT_SUBREG
3681 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3682 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3687 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3688 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3690 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3691 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3693 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3695 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3696 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3699 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3700 (i32 (EXTRACT_SUBREG
3701 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3702 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3704 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3705 (i32 (EXTRACT_SUBREG
3706 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3707 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3710 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3711 (i64 (EXTRACT_SUBREG
3712 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3713 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3717 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3719 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3720 (i32 (EXTRACT_SUBREG
3721 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3722 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3724 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3725 (i32 (EXTRACT_SUBREG
3726 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3727 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3730 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3731 (i32 (EXTRACT_SUBREG
3732 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3733 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3735 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3736 (i32 (EXTRACT_SUBREG
3737 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3738 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3741 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3742 (i64 (EXTRACT_SUBREG
3743 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3744 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3748 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_arm64_neon_saddv>;
3749 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3750 def : Pat<(i32 (int_arm64_neon_saddv (v2i32 V64:$Rn))),
3751 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3753 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_arm64_neon_uaddv>;
3754 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3755 def : Pat<(i32 (int_arm64_neon_uaddv (v2i32 V64:$Rn))),
3756 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3758 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_arm64_neon_smaxv>;
3759 def : Pat<(i32 (int_arm64_neon_smaxv (v2i32 V64:$Rn))),
3760 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3762 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_arm64_neon_sminv>;
3763 def : Pat<(i32 (int_arm64_neon_sminv (v2i32 V64:$Rn))),
3764 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3766 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_arm64_neon_umaxv>;
3767 def : Pat<(i32 (int_arm64_neon_umaxv (v2i32 V64:$Rn))),
3768 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3770 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_arm64_neon_uminv>;
3771 def : Pat<(i32 (int_arm64_neon_uminv (v2i32 V64:$Rn))),
3772 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3774 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_arm64_neon_saddlv>;
3775 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_arm64_neon_uaddlv>;
3777 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3778 def : Pat<(i64 (int_arm64_neon_saddlv (v2i32 V64:$Rn))),
3779 (i64 (EXTRACT_SUBREG
3780 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3781 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3783 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
3784 def : Pat<(i64 (int_arm64_neon_uaddlv (v2i32 V64:$Rn))),
3785 (i64 (EXTRACT_SUBREG
3786 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3787 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
3790 //------------------------------------------------------------------------------
3791 // AdvSIMD modified immediate instructions
3792 //------------------------------------------------------------------------------
3795 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", ARM64bici>;
3797 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", ARM64orri>;
3799 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3800 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3801 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3802 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3804 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3805 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3806 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3807 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3809 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3810 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3811 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3812 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3814 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3815 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3816 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3817 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3820 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
3822 [(set (v2f64 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3823 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
3825 [(set (v2f32 V64:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3826 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
3828 [(set (v4f32 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3832 // EDIT byte mask: scalar
3833 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3834 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
3835 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
3836 // The movi_edit node has the immediate value already encoded, so we use
3837 // a plain imm0_255 here.
3838 def : Pat<(f64 (ARM64movi_edit imm0_255:$shift)),
3839 (MOVID imm0_255:$shift)>;
3841 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
3842 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
3843 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
3844 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
3846 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
3847 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
3848 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
3849 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
3851 // EDIT byte mask: 2d
3853 // The movi_edit node has the immediate value already encoded, so we use
3854 // a plain imm0_255 in the pattern
3855 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3856 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
3859 [(set (v2i64 V128:$Rd), (ARM64movi_edit imm0_255:$imm8))]>;
3862 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
3863 // Complexity is added to break a tie with a plain MOVI.
3864 let AddedComplexity = 1 in {
3865 def : Pat<(f32 fpimm0),
3866 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
3868 def : Pat<(f64 fpimm0),
3869 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
3873 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3874 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3875 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3876 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3878 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3879 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3880 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3881 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3883 def : Pat<(v2f64 (ARM64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
3884 def : Pat<(v4f32 (ARM64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
3886 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3887 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
3889 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3890 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3891 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3892 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3894 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3895 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3896 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3897 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3899 def : Pat<(v2i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3900 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
3901 def : Pat<(v4i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3902 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
3903 def : Pat<(v4i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3904 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
3905 def : Pat<(v8i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3906 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
3908 // EDIT per word: 2s & 4s with MSL shifter
3909 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
3910 [(set (v2i32 V64:$Rd),
3911 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3912 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
3913 [(set (v4i32 V128:$Rd),
3914 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3916 // Per byte: 8b & 16b
3917 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
3919 [(set (v8i8 V64:$Rd), (ARM64movi imm0_255:$imm8))]>;
3920 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
3922 [(set (v16i8 V128:$Rd), (ARM64movi imm0_255:$imm8))]>;
3926 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3927 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
3929 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3930 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3931 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3932 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3934 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3935 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3936 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3937 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3939 def : Pat<(v2i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3940 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
3941 def : Pat<(v4i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3942 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
3943 def : Pat<(v4i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3944 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
3945 def : Pat<(v8i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3946 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
3948 // EDIT per word: 2s & 4s with MSL shifter
3949 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
3950 [(set (v2i32 V64:$Rd),
3951 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3952 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
3953 [(set (v4i32 V128:$Rd),
3954 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3956 //----------------------------------------------------------------------------
3957 // AdvSIMD indexed element
3958 //----------------------------------------------------------------------------
3960 let neverHasSideEffects = 1 in {
3961 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
3962 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
3965 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
3966 // instruction expects the addend first, while the intrinsic expects it last.
3968 // On the other hand, there are quite a few valid combinatorial options due to
3969 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
3970 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3971 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
3972 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3973 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
3975 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3976 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
3977 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3978 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
3979 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3980 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
3981 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3982 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
3984 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
3985 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3987 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3988 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3989 VectorIndexS:$idx))),
3990 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3991 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3992 (v2f32 (ARM64duplane32
3993 (v4f32 (insert_subvector undef,
3994 (v2f32 (fneg V64:$Rm)),
3996 VectorIndexS:$idx)))),
3997 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3998 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3999 VectorIndexS:$idx)>;
4000 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4001 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
4002 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4003 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4005 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4007 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4008 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
4009 VectorIndexS:$idx))),
4010 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4011 VectorIndexS:$idx)>;
4012 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4013 (v4f32 (ARM64duplane32
4014 (v4f32 (insert_subvector undef,
4015 (v2f32 (fneg V64:$Rm)),
4017 VectorIndexS:$idx)))),
4018 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4019 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4020 VectorIndexS:$idx)>;
4021 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4022 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
4023 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4024 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4026 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4027 // (DUPLANE from 64-bit would be trivial).
4028 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4029 (ARM64duplane64 (v2f64 (fneg V128:$Rm)),
4030 VectorIndexD:$idx))),
4032 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4033 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4034 (ARM64dup (f64 (fneg FPR64Op:$Rm))))),
4035 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4036 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4038 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4039 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4040 (vector_extract (v4f32 (fneg V128:$Rm)),
4041 VectorIndexS:$idx))),
4042 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4043 V128:$Rm, VectorIndexS:$idx)>;
4044 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4045 (vector_extract (v2f32 (fneg V64:$Rm)),
4046 VectorIndexS:$idx))),
4047 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4048 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4050 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4051 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4052 (vector_extract (v2f64 (fneg V128:$Rm)),
4053 VectorIndexS:$idx))),
4054 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4055 V128:$Rm, VectorIndexS:$idx)>;
4058 defm : FMLSIndexedAfterNegPatterns<
4059 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4060 defm : FMLSIndexedAfterNegPatterns<
4061 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4063 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_arm64_neon_fmulx>;
4064 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
4066 def : Pat<(v2f32 (fmul V64:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
4067 (FMULv2i32_indexed V64:$Rn,
4068 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4070 def : Pat<(v4f32 (fmul V128:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
4071 (FMULv4i32_indexed V128:$Rn,
4072 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4074 def : Pat<(v2f64 (fmul V128:$Rn, (ARM64dup (f64 FPR64:$Rm)))),
4075 (FMULv2i64_indexed V128:$Rn,
4076 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4079 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_arm64_neon_sqdmulh>;
4080 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_arm64_neon_sqrdmulh>;
4081 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4082 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4083 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4084 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4085 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4086 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4087 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
4088 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4089 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
4090 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4091 int_arm64_neon_smull>;
4092 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4093 int_arm64_neon_sqadd>;
4094 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4095 int_arm64_neon_sqsub>;
4096 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_arm64_neon_sqdmull>;
4097 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4098 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
4099 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4100 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
4101 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4102 int_arm64_neon_umull>;
4104 // A scalar sqdmull with the second operand being a vector lane can be
4105 // handled directly with the indexed instruction encoding.
4106 def : Pat<(int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4107 (vector_extract (v4i32 V128:$Vm),
4108 VectorIndexS:$idx)),
4109 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4111 //----------------------------------------------------------------------------
4112 // AdvSIMD scalar shift instructions
4113 //----------------------------------------------------------------------------
4114 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4115 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4116 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4117 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4118 // Codegen patterns for the above. We don't put these directly on the
4119 // instructions because TableGen's type inference can't handle the truth.
4120 // Having the same base pattern for fp <--> int totally freaks it out.
4121 def : Pat<(int_arm64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4122 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4123 def : Pat<(int_arm64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4124 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4125 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4126 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4127 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4128 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4129 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4131 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4132 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4134 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4135 def : Pat<(int_arm64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4136 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4137 def : Pat<(int_arm64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4138 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4139 def : Pat<(f64 (int_arm64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4140 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4141 def : Pat<(f64 (int_arm64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4142 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4143 def : Pat<(v1f64 (int_arm64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4145 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4146 def : Pat<(v1f64 (int_arm64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4148 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4150 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", ARM64vshl>;
4151 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4152 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4153 int_arm64_neon_sqrshrn>;
4154 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4155 int_arm64_neon_sqrshrun>;
4156 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
4157 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
4158 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4159 int_arm64_neon_sqshrn>;
4160 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4161 int_arm64_neon_sqshrun>;
4162 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4163 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", ARM64srshri>;
4164 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4165 TriOpFrag<(add node:$LHS,
4166 (ARM64srshri node:$MHS, node:$RHS))>>;
4167 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", ARM64vashr>;
4168 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4169 TriOpFrag<(add node:$LHS,
4170 (ARM64vashr node:$MHS, node:$RHS))>>;
4171 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4172 int_arm64_neon_uqrshrn>;
4173 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
4174 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4175 int_arm64_neon_uqshrn>;
4176 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", ARM64urshri>;
4177 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4178 TriOpFrag<(add node:$LHS,
4179 (ARM64urshri node:$MHS, node:$RHS))>>;
4180 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", ARM64vlshr>;
4181 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4182 TriOpFrag<(add node:$LHS,
4183 (ARM64vlshr node:$MHS, node:$RHS))>>;
4185 //----------------------------------------------------------------------------
4186 // AdvSIMD vector shift instructions
4187 //----------------------------------------------------------------------------
4188 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_arm64_neon_vcvtfp2fxs>;
4189 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_arm64_neon_vcvtfp2fxu>;
4190 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4191 int_arm64_neon_vcvtfxs2fp>;
4192 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4193 int_arm64_neon_rshrn>;
4194 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", ARM64vshl>;
4195 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4196 BinOpFrag<(trunc (ARM64vashr node:$LHS, node:$RHS))>>;
4197 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_arm64_neon_vsli>;
4198 def : Pat<(v1i64 (int_arm64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4199 (i32 vecshiftL64:$imm))),
4200 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4201 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4202 int_arm64_neon_sqrshrn>;
4203 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4204 int_arm64_neon_sqrshrun>;
4205 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
4206 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
4207 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4208 int_arm64_neon_sqshrn>;
4209 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4210 int_arm64_neon_sqshrun>;
4211 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_arm64_neon_vsri>;
4212 def : Pat<(v1i64 (int_arm64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4213 (i32 vecshiftR64:$imm))),
4214 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4215 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", ARM64srshri>;
4216 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4217 TriOpFrag<(add node:$LHS,
4218 (ARM64srshri node:$MHS, node:$RHS))> >;
4219 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4220 BinOpFrag<(ARM64vshl (sext node:$LHS), node:$RHS)>>;
4222 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", ARM64vashr>;
4223 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4224 TriOpFrag<(add node:$LHS, (ARM64vashr node:$MHS, node:$RHS))>>;
4225 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4226 int_arm64_neon_vcvtfxu2fp>;
4227 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4228 int_arm64_neon_uqrshrn>;
4229 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
4230 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4231 int_arm64_neon_uqshrn>;
4232 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", ARM64urshri>;
4233 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4234 TriOpFrag<(add node:$LHS,
4235 (ARM64urshri node:$MHS, node:$RHS))> >;
4236 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4237 BinOpFrag<(ARM64vshl (zext node:$LHS), node:$RHS)>>;
4238 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", ARM64vlshr>;
4239 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4240 TriOpFrag<(add node:$LHS, (ARM64vlshr node:$MHS, node:$RHS))> >;
4242 // SHRN patterns for when a logical right shift was used instead of arithmetic
4243 // (the immediate guarantees no sign bits actually end up in the result so it
4245 def : Pat<(v8i8 (trunc (ARM64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4246 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4247 def : Pat<(v4i16 (trunc (ARM64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4248 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4249 def : Pat<(v2i32 (trunc (ARM64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4250 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4252 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4253 (trunc (ARM64vlshr (v8i16 V128:$Rn),
4254 vecshiftR16Narrow:$imm)))),
4255 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4256 V128:$Rn, vecshiftR16Narrow:$imm)>;
4257 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4258 (trunc (ARM64vlshr (v4i32 V128:$Rn),
4259 vecshiftR32Narrow:$imm)))),
4260 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4261 V128:$Rn, vecshiftR32Narrow:$imm)>;
4262 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4263 (trunc (ARM64vlshr (v2i64 V128:$Rn),
4264 vecshiftR64Narrow:$imm)))),
4265 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4266 V128:$Rn, vecshiftR32Narrow:$imm)>;
4268 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4269 // Anyexts are implemented as zexts.
4270 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4271 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4272 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4273 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4274 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4275 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4276 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4277 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4278 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4279 // Also match an extend from the upper half of a 128 bit source register.
4280 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4281 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4282 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4283 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4284 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4285 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4286 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4287 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4288 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4289 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4290 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4291 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4292 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4293 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4294 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4295 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4296 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4297 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4299 // Vector shift sxtl aliases
4300 def : InstAlias<"sxtl.8h $dst, $src1",
4301 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4302 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4303 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4304 def : InstAlias<"sxtl.4s $dst, $src1",
4305 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4306 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4307 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4308 def : InstAlias<"sxtl.2d $dst, $src1",
4309 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4310 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4311 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4313 // Vector shift sxtl2 aliases
4314 def : InstAlias<"sxtl2.8h $dst, $src1",
4315 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4316 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4317 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4318 def : InstAlias<"sxtl2.4s $dst, $src1",
4319 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4320 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4321 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4322 def : InstAlias<"sxtl2.2d $dst, $src1",
4323 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4324 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4325 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4327 // Vector shift uxtl aliases
4328 def : InstAlias<"uxtl.8h $dst, $src1",
4329 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4330 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4331 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4332 def : InstAlias<"uxtl.4s $dst, $src1",
4333 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4334 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4335 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4336 def : InstAlias<"uxtl.2d $dst, $src1",
4337 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4338 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4339 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4341 // Vector shift uxtl2 aliases
4342 def : InstAlias<"uxtl2.8h $dst, $src1",
4343 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4344 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4345 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4346 def : InstAlias<"uxtl2.4s $dst, $src1",
4347 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4348 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4349 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4350 def : InstAlias<"uxtl2.2d $dst, $src1",
4351 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4352 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4353 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4355 // If an integer is about to be converted to a floating point value,
4356 // just load it on the floating point unit.
4357 // These patterns are more complex because floating point loads do not
4358 // support sign extension.
4359 // The sign extension has to be explicitly added and is only supported for
4360 // one step: byte-to-half, half-to-word, word-to-doubleword.
4361 // SCVTF GPR -> FPR is 9 cycles.
4362 // SCVTF FPR -> FPR is 4 cyclces.
4363 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4364 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4365 // and still being faster.
4366 // However, this is not good for code size.
4367 // 8-bits -> float. 2 sizes step-up.
4368 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4369 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4370 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4375 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4381 ssub)))>, Requires<[NotForCodeSize]>;
4383 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4384 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4385 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4386 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4387 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4388 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4389 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4390 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4392 // 16-bits -> float. 1 size step-up.
4393 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4394 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4395 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4397 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4401 ssub)))>, Requires<[NotForCodeSize]>;
4403 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4404 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4405 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4406 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4407 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4408 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4409 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4410 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4412 // 32-bits to 32-bits are handled in target specific dag combine:
4413 // performIntToFpCombine.
4414 // 64-bits integer to 32-bits floating point, not possible with
4415 // SCVTF on floating point registers (both source and destination
4416 // must have the same size).
4418 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4419 // 8-bits -> double. 3 size step-up: give up.
4420 // 16-bits -> double. 2 size step.
4421 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4422 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4423 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4428 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4434 dsub)))>, Requires<[NotForCodeSize]>;
4436 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4437 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4438 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4439 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4440 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4441 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4442 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4443 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4444 // 32-bits -> double. 1 size step-up.
4445 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4446 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4447 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4449 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4453 dsub)))>, Requires<[NotForCodeSize]>;
4455 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4456 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4457 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4458 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4459 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4460 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4461 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4462 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4464 // 64-bits -> double are handled in target specific dag combine:
4465 // performIntToFpCombine.
4468 //----------------------------------------------------------------------------
4469 // AdvSIMD Load-Store Structure
4470 //----------------------------------------------------------------------------
4471 defm LD1 : SIMDLd1Multiple<"ld1">;
4472 defm LD2 : SIMDLd2Multiple<"ld2">;
4473 defm LD3 : SIMDLd3Multiple<"ld3">;
4474 defm LD4 : SIMDLd4Multiple<"ld4">;
4476 defm ST1 : SIMDSt1Multiple<"st1">;
4477 defm ST2 : SIMDSt2Multiple<"st2">;
4478 defm ST3 : SIMDSt3Multiple<"st3">;
4479 defm ST4 : SIMDSt4Multiple<"st4">;
4481 class Ld1Pat<ValueType ty, Instruction INST>
4482 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4484 def : Ld1Pat<v16i8, LD1Onev16b>;
4485 def : Ld1Pat<v8i16, LD1Onev8h>;
4486 def : Ld1Pat<v4i32, LD1Onev4s>;
4487 def : Ld1Pat<v2i64, LD1Onev2d>;
4488 def : Ld1Pat<v8i8, LD1Onev8b>;
4489 def : Ld1Pat<v4i16, LD1Onev4h>;
4490 def : Ld1Pat<v2i32, LD1Onev2s>;
4491 def : Ld1Pat<v1i64, LD1Onev1d>;
4493 class St1Pat<ValueType ty, Instruction INST>
4494 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4495 (INST ty:$Vt, GPR64sp:$Rn)>;
4497 def : St1Pat<v16i8, ST1Onev16b>;
4498 def : St1Pat<v8i16, ST1Onev8h>;
4499 def : St1Pat<v4i32, ST1Onev4s>;
4500 def : St1Pat<v2i64, ST1Onev2d>;
4501 def : St1Pat<v8i8, ST1Onev8b>;
4502 def : St1Pat<v4i16, ST1Onev4h>;
4503 def : St1Pat<v2i32, ST1Onev2s>;
4504 def : St1Pat<v1i64, ST1Onev1d>;
4510 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4511 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4512 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4513 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4514 let mayLoad = 1, neverHasSideEffects = 1 in {
4515 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4516 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4517 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4518 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4519 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4520 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4521 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4522 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4523 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4524 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4525 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4526 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4527 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4528 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4529 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4530 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4533 def : Pat<(v8i8 (ARM64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4534 (LD1Rv8b GPR64sp:$Rn)>;
4535 def : Pat<(v16i8 (ARM64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4536 (LD1Rv16b GPR64sp:$Rn)>;
4537 def : Pat<(v4i16 (ARM64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4538 (LD1Rv4h GPR64sp:$Rn)>;
4539 def : Pat<(v8i16 (ARM64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4540 (LD1Rv8h GPR64sp:$Rn)>;
4541 def : Pat<(v2i32 (ARM64dup (i32 (load GPR64sp:$Rn)))),
4542 (LD1Rv2s GPR64sp:$Rn)>;
4543 def : Pat<(v4i32 (ARM64dup (i32 (load GPR64sp:$Rn)))),
4544 (LD1Rv4s GPR64sp:$Rn)>;
4545 def : Pat<(v2i64 (ARM64dup (i64 (load GPR64sp:$Rn)))),
4546 (LD1Rv2d GPR64sp:$Rn)>;
4547 def : Pat<(v1i64 (ARM64dup (i64 (load GPR64sp:$Rn)))),
4548 (LD1Rv1d GPR64sp:$Rn)>;
4549 // Grab the floating point version too
4550 def : Pat<(v2f32 (ARM64dup (f32 (load GPR64sp:$Rn)))),
4551 (LD1Rv2s GPR64sp:$Rn)>;
4552 def : Pat<(v4f32 (ARM64dup (f32 (load GPR64sp:$Rn)))),
4553 (LD1Rv4s GPR64sp:$Rn)>;
4554 def : Pat<(v2f64 (ARM64dup (f64 (load GPR64sp:$Rn)))),
4555 (LD1Rv2d GPR64sp:$Rn)>;
4556 def : Pat<(v1f64 (ARM64dup (f64 (load GPR64sp:$Rn)))),
4557 (LD1Rv1d GPR64sp:$Rn)>;
4559 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4560 ValueType VTy, ValueType STy, Instruction LD1>
4561 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4562 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4563 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4565 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4566 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4567 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4568 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4569 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4570 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4572 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4573 ValueType VTy, ValueType STy, Instruction LD1>
4574 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4575 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4577 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4578 VecIndex:$idx, GPR64sp:$Rn),
4581 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4582 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4583 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4584 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4587 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4588 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4589 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4590 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4593 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4594 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4595 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4596 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4598 let AddedComplexity = 15 in
4599 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4600 ValueType VTy, ValueType STy, Instruction ST1>
4602 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4604 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
4606 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4607 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4608 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4609 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4610 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4611 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4613 let AddedComplexity = 15 in
4614 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4615 ValueType VTy, ValueType STy, Instruction ST1>
4617 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4619 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4620 VecIndex:$idx, GPR64sp:$Rn)>;
4622 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4623 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4624 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4625 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4627 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4628 ValueType VTy, ValueType STy, Instruction ST1,
4630 def : Pat<(scalar_store
4631 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4632 GPR64sp:$Rn, offset),
4633 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4634 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4636 def : Pat<(scalar_store
4637 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4638 GPR64sp:$Rn, GPR64:$Rm),
4639 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4640 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4643 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
4644 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
4646 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
4647 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
4648 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
4649 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
4651 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4652 ValueType VTy, ValueType STy, Instruction ST1,
4654 def : Pat<(scalar_store
4655 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4656 GPR64sp:$Rn, offset),
4657 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4659 def : Pat<(scalar_store
4660 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4661 GPR64sp:$Rn, GPR64:$Rm),
4662 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4665 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
4667 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
4669 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
4670 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
4671 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
4672 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
4674 let mayStore = 1, neverHasSideEffects = 1 in {
4675 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4676 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4677 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4678 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4679 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4680 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4681 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4682 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4683 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4684 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4685 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4686 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4689 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4690 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4691 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4692 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4694 //----------------------------------------------------------------------------
4695 // Crypto extensions
4696 //----------------------------------------------------------------------------
4698 def AESErr : AESTiedInst<0b0100, "aese", int_arm64_crypto_aese>;
4699 def AESDrr : AESTiedInst<0b0101, "aesd", int_arm64_crypto_aesd>;
4700 def AESMCrr : AESInst< 0b0110, "aesmc", int_arm64_crypto_aesmc>;
4701 def AESIMCrr : AESInst< 0b0111, "aesimc", int_arm64_crypto_aesimc>;
4703 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_arm64_crypto_sha1c>;
4704 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_arm64_crypto_sha1p>;
4705 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_arm64_crypto_sha1m>;
4706 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_arm64_crypto_sha1su0>;
4707 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_arm64_crypto_sha256h>;
4708 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_arm64_crypto_sha256h2>;
4709 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_arm64_crypto_sha256su1>;
4711 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_arm64_crypto_sha1h>;
4712 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_arm64_crypto_sha1su1>;
4713 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_arm64_crypto_sha256su0>;
4715 //----------------------------------------------------------------------------
4717 //----------------------------------------------------------------------------
4718 // FIXME: Like for X86, these should go in their own separate .td file.
4720 // Any instruction that defines a 32-bit result leaves the high half of the
4721 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4722 // be copying from a truncate. But any other 32-bit operation will zero-extend
4724 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4725 def def32 : PatLeaf<(i32 GPR32:$src), [{
4726 return N->getOpcode() != ISD::TRUNCATE &&
4727 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4728 N->getOpcode() != ISD::CopyFromReg;
4731 // In the case of a 32-bit def that is known to implicitly zero-extend,
4732 // we can use a SUBREG_TO_REG.
4733 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4735 // For an anyext, we don't care what the high bits are, so we can perform an
4736 // INSERT_SUBREF into an IMPLICIT_DEF.
4737 def : Pat<(i64 (anyext GPR32:$src)),
4738 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4740 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4741 // instruction (UBFM) on the enclosing super-reg.
4742 def : Pat<(i64 (zext GPR32:$src)),
4743 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4745 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4746 // containing super-reg.
4747 def : Pat<(i64 (sext GPR32:$src)),
4748 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4749 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4750 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4751 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4752 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4753 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4754 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4755 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4757 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4758 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4759 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4760 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4761 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4762 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4764 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
4765 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4766 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
4767 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4768 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4769 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4771 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4772 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4773 (i64 (i64shift_a imm0_63:$imm)),
4774 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
4776 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
4777 // AddedComplexity for the following patterns since we want to match sext + sra
4778 // patterns before we attempt to match a single sra node.
4779 let AddedComplexity = 20 in {
4780 // We support all sext + sra combinations which preserve at least one bit of the
4781 // original value which is to be sign extended. E.g. we support shifts up to
4783 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
4784 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
4785 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
4786 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
4788 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
4789 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
4790 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
4791 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
4793 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
4794 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4795 (i64 imm0_31:$imm), 31)>;
4796 } // AddedComplexity = 20
4798 // To truncate, we can simply extract from a subregister.
4799 def : Pat<(i32 (trunc GPR64sp:$src)),
4800 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
4802 // __builtin_trap() uses the BRK instruction on ARM64.
4803 def : Pat<(trap), (BRK 1)>;
4805 // Conversions within AdvSIMD types in the same register size are free.
4806 // But because we need a consistent lane ordering, in big endian many
4807 // conversions require one or more REV instructions.
4809 // Consider a simple memory load followed by a bitconvert then a store.
4811 // v1 = BITCAST v2i32 v0 to v4i16
4814 // In big endian mode every memory access has an implicit byte swap. LDR and
4815 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
4816 // is, they treat the vector as a sequence of elements to be byte-swapped.
4817 // The two pairs of instructions are fundamentally incompatible. We've decided
4818 // to use LD1/ST1 only to simplify compiler implementation.
4820 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
4821 // the original code sequence:
4823 // v1 = REV v2i32 (implicit)
4824 // v2 = BITCAST v2i32 v1 to v4i16
4825 // v3 = REV v4i16 v2 (implicit)
4828 // But this is now broken - the value stored is different to the value loaded
4829 // due to lane reordering. To fix this, on every BITCAST we must perform two
4832 // v1 = REV v2i32 (implicit)
4834 // v3 = BITCAST v2i32 v2 to v4i16
4836 // v5 = REV v4i16 v4 (implicit)
4839 // This means an extra two instructions, but actually in most cases the two REV
4840 // instructions can be combined into one. For example:
4841 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
4843 // There is also no 128-bit REV instruction. This must be synthesized with an
4846 // Most bitconverts require some sort of conversion. The only exceptions are:
4847 // a) Identity conversions - vNfX <-> vNiX
4848 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
4851 let Predicates = [IsLE] in {
4852 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4853 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4854 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4855 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4857 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
4858 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4859 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
4860 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4861 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
4862 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4863 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
4864 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4865 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
4866 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4868 let Predicates = [IsBE] in {
4869 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
4870 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4871 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
4872 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4873 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
4874 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4875 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
4876 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4878 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
4879 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4880 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
4881 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4882 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
4883 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4884 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
4885 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4887 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4888 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4889 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
4890 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4891 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
4892 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4893 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
4894 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4895 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
4897 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
4898 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
4899 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
4900 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
4901 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
4902 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4903 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
4904 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
4905 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
4906 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4908 let Predicates = [IsLE] in {
4909 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
4910 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
4911 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
4912 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
4914 let Predicates = [IsBE] in {
4915 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
4916 (v1i64 (REV64v2i32 FPR64:$src))>;
4917 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
4918 (v1i64 (REV64v4i16 FPR64:$src))>;
4919 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
4920 (v1i64 (REV64v8i8 FPR64:$src))>;
4921 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
4922 (v1i64 (REV64v2i32 FPR64:$src))>;
4924 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4925 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4927 let Predicates = [IsLE] in {
4928 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
4929 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
4930 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
4931 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4932 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4934 let Predicates = [IsBE] in {
4935 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
4936 (v2i32 (REV64v2i32 FPR64:$src))>;
4937 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
4938 (v2i32 (REV32v4i16 FPR64:$src))>;
4939 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
4940 (v2i32 (REV32v8i8 FPR64:$src))>;
4941 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
4942 (v2i32 (REV64v2i32 FPR64:$src))>;
4943 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
4944 (v2i32 (REV64v2i32 FPR64:$src))>;
4946 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
4948 let Predicates = [IsLE] in {
4949 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
4950 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
4951 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
4952 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4953 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
4954 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4956 let Predicates = [IsBE] in {
4957 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
4958 (v4i16 (REV64v4i16 FPR64:$src))>;
4959 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
4960 (v4i16 (REV32v4i16 FPR64:$src))>;
4961 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
4962 (v4i16 (REV16v8i8 FPR64:$src))>;
4963 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
4964 (v4i16 (REV64v4i16 FPR64:$src))>;
4965 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
4966 (v4i16 (REV32v4i16 FPR64:$src))>;
4967 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
4968 (v4i16 (REV64v4i16 FPR64:$src))>;
4971 let Predicates = [IsLE] in {
4972 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
4973 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
4974 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
4975 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4976 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
4977 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4979 let Predicates = [IsBE] in {
4980 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
4981 (v8i8 (REV64v8i8 FPR64:$src))>;
4982 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
4983 (v8i8 (REV32v8i8 FPR64:$src))>;
4984 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
4985 (v8i8 (REV16v8i8 FPR64:$src))>;
4986 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
4987 (v8i8 (REV64v8i8 FPR64:$src))>;
4988 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
4989 (v8i8 (REV32v8i8 FPR64:$src))>;
4990 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
4991 (v8i8 (REV64v8i8 FPR64:$src))>;
4994 let Predicates = [IsLE] in {
4995 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
4996 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
4997 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
4998 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5000 let Predicates = [IsBE] in {
5001 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5002 (f64 (REV64v2i32 FPR64:$src))>;
5003 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5004 (f64 (REV64v4i16 FPR64:$src))>;
5005 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5006 (f64 (REV64v2i32 FPR64:$src))>;
5007 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5008 (f64 (REV64v8i8 FPR64:$src))>;
5010 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5011 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5013 let Predicates = [IsLE] in {
5014 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5015 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5016 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5017 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5019 let Predicates = [IsBE] in {
5020 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5021 (v1f64 (REV64v2i32 FPR64:$src))>;
5022 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5023 (v1f64 (REV64v4i16 FPR64:$src))>;
5024 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5025 (v1f64 (REV64v8i8 FPR64:$src))>;
5026 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5027 (v1f64 (REV64v2i32 FPR64:$src))>;
5029 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5030 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5032 let Predicates = [IsLE] in {
5033 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5034 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5035 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5036 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5037 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5039 let Predicates = [IsBE] in {
5040 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5041 (v2f32 (REV64v2i32 FPR64:$src))>;
5042 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5043 (v2f32 (REV32v4i16 FPR64:$src))>;
5044 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5045 (v2f32 (REV32v8i8 FPR64:$src))>;
5046 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5047 (v2f32 (REV64v2i32 FPR64:$src))>;
5048 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5049 (v2f32 (REV64v2i32 FPR64:$src))>;
5051 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5053 let Predicates = [IsLE] in {
5054 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5055 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5056 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5057 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5058 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5059 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5061 let Predicates = [IsBE] in {
5062 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5063 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5064 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5065 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5066 (REV64v4i32 FPR128:$src), (i32 8)))>;
5067 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5068 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5069 (REV64v8i16 FPR128:$src), (i32 8)))>;
5070 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5071 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5072 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5073 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5074 (REV64v4i32 FPR128:$src), (i32 8)))>;
5075 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5076 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5077 (REV64v16i8 FPR128:$src), (i32 8)))>;
5080 let Predicates = [IsLE] in {
5081 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5082 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5083 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5084 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5085 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5087 let Predicates = [IsBE] in {
5088 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5089 (v2f64 (EXTv16i8 FPR128:$src,
5090 FPR128:$src, (i32 8)))>;
5091 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5092 (v2f64 (REV64v4i32 FPR128:$src))>;
5093 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5094 (v2f64 (REV64v8i16 FPR128:$src))>;
5095 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5096 (v2f64 (REV64v16i8 FPR128:$src))>;
5097 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5098 (v2f64 (REV64v4i32 FPR128:$src))>;
5100 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5102 let Predicates = [IsLE] in {
5103 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5104 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5105 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5106 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5107 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5109 let Predicates = [IsBE] in {
5110 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5111 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5112 (REV64v4i32 FPR128:$src), (i32 8)))>;
5113 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5114 (v4f32 (REV32v8i16 FPR128:$src))>;
5115 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5116 (v4f32 (REV32v16i8 FPR128:$src))>;
5117 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5118 (v4f32 (REV64v4i32 FPR128:$src))>;
5119 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5120 (v4f32 (REV64v4i32 FPR128:$src))>;
5122 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5124 let Predicates = [IsLE] in {
5125 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5126 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5127 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5128 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5129 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5131 let Predicates = [IsBE] in {
5132 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5133 (v2i64 (EXTv16i8 FPR128:$src,
5134 FPR128:$src, (i32 8)))>;
5135 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5136 (v2i64 (REV64v4i32 FPR128:$src))>;
5137 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5138 (v2i64 (REV64v8i16 FPR128:$src))>;
5139 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5140 (v2i64 (REV64v16i8 FPR128:$src))>;
5141 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5142 (v2i64 (REV64v4i32 FPR128:$src))>;
5144 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5146 let Predicates = [IsLE] in {
5147 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5148 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5149 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5150 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5151 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5153 let Predicates = [IsBE] in {
5154 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5155 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5156 (REV64v4i32 FPR128:$src),
5158 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5159 (v4i32 (REV64v4i32 FPR128:$src))>;
5160 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5161 (v4i32 (REV32v8i16 FPR128:$src))>;
5162 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5163 (v4i32 (REV32v16i8 FPR128:$src))>;
5164 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5165 (v4i32 (REV64v4i32 FPR128:$src))>;
5167 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5169 let Predicates = [IsLE] in {
5170 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5171 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5172 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5173 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5174 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5175 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5177 let Predicates = [IsBE] in {
5178 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5179 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5180 (REV64v8i16 FPR128:$src),
5182 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5183 (v8i16 (REV64v8i16 FPR128:$src))>;
5184 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5185 (v8i16 (REV32v8i16 FPR128:$src))>;
5186 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5187 (v8i16 (REV16v16i8 FPR128:$src))>;
5188 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5189 (v8i16 (REV64v8i16 FPR128:$src))>;
5190 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5191 (v8i16 (REV32v8i16 FPR128:$src))>;
5194 let Predicates = [IsLE] in {
5195 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5196 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5197 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5198 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5199 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5200 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5202 let Predicates = [IsBE] in {
5203 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5204 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5205 (REV64v16i8 FPR128:$src),
5207 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5208 (v16i8 (REV64v16i8 FPR128:$src))>;
5209 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5210 (v16i8 (REV32v16i8 FPR128:$src))>;
5211 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5212 (v16i8 (REV16v16i8 FPR128:$src))>;
5213 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5214 (v16i8 (REV64v16i8 FPR128:$src))>;
5215 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5216 (v16i8 (REV32v16i8 FPR128:$src))>;
5219 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5220 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5221 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5222 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5223 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5224 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5225 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5226 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5228 // A 64-bit subvector insert to the first 128-bit vector position
5229 // is a subregister copy that needs no instruction.
5230 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5231 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5232 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5233 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5234 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5235 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5236 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5237 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5238 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5239 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5240 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5241 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5243 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5245 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5246 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5247 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5248 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5249 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5250 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5251 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5252 // so we match on v4f32 here, not v2f32. This will also catch adding
5253 // the low two lanes of a true v4f32 vector.
5254 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5255 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5256 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5258 // Scalar 64-bit shifts in FPR64 registers.
5259 def : Pat<(i64 (int_arm64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5260 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5261 def : Pat<(i64 (int_arm64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5262 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5263 def : Pat<(i64 (int_arm64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5264 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5265 def : Pat<(i64 (int_arm64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5266 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5268 // Tail call return handling. These are all compiler pseudo-instructions,
5269 // so no encoding information or anything like that.
5270 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5271 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5272 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5275 def : Pat<(ARM64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5276 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5277 def : Pat<(ARM64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5278 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5279 def : Pat<(ARM64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5280 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5282 include "ARM64InstrAtomics.td"