1 //===- ARM64InstrInfo.td - Describe the ARM64 Instructions -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // ARM64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM64-specific DAG Nodes.
18 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
19 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
22 SDTCisInt<0>, SDTCisVT<1, i32>]>;
24 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
25 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
31 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
32 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
39 def SDT_ARM64Brcond : SDTypeProfile<0, 3,
40 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
42 def SDT_ARM64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
43 def SDT_ARM64tbz : SDTypeProfile<0, 3, [SDTCisVT<0, i64>, SDTCisVT<1, i64>,
44 SDTCisVT<2, OtherVT>]>;
47 def SDT_ARM64CSel : SDTypeProfile<1, 4,
52 def SDT_ARM64FCmp : SDTypeProfile<0, 2,
55 def SDT_ARM64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
56 def SDT_ARM64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
57 def SDT_ARM64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
60 def SDT_ARM64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
61 def SDT_ARM64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
62 def SDT_ARM64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
63 SDTCisInt<2>, SDTCisInt<3>]>;
64 def SDT_ARM64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
65 def SDT_ARM64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
66 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
67 def SDT_ARM64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
69 def SDT_ARM64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
70 def SDT_ARM64fcmpz : SDTypeProfile<1, 1, []>;
71 def SDT_ARM64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
72 def SDT_ARM64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
74 def SDT_ARM64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
77 def SDT_ARM64TCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
78 def SDT_ARM64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
80 def SDT_ARM64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
82 def SDT_ARM64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
84 def SDT_ARM64WrapperLarge : SDTypeProfile<1, 4,
85 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
86 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
91 def ARM64adrp : SDNode<"ARM64ISD::ADRP", SDTIntUnaryOp, []>;
92 def ARM64addlow : SDNode<"ARM64ISD::ADDlow", SDTIntBinOp, []>;
93 def ARM64LOADgot : SDNode<"ARM64ISD::LOADgot", SDTIntUnaryOp>;
94 def ARM64callseq_start : SDNode<"ISD::CALLSEQ_START",
95 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
96 [SDNPHasChain, SDNPOutGlue]>;
97 def ARM64callseq_end : SDNode<"ISD::CALLSEQ_END",
98 SDCallSeqEnd<[ SDTCisVT<0, i32>,
100 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
101 def ARM64call : SDNode<"ARM64ISD::CALL",
102 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
103 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
105 def ARM64brcond : SDNode<"ARM64ISD::BRCOND", SDT_ARM64Brcond,
107 def ARM64cbz : SDNode<"ARM64ISD::CBZ", SDT_ARM64cbz,
109 def ARM64cbnz : SDNode<"ARM64ISD::CBNZ", SDT_ARM64cbz,
111 def ARM64tbz : SDNode<"ARM64ISD::TBZ", SDT_ARM64tbz,
113 def ARM64tbnz : SDNode<"ARM64ISD::TBNZ", SDT_ARM64tbz,
117 def ARM64csel : SDNode<"ARM64ISD::CSEL", SDT_ARM64CSel>;
118 def ARM64csinv : SDNode<"ARM64ISD::CSINV", SDT_ARM64CSel>;
119 def ARM64csneg : SDNode<"ARM64ISD::CSNEG", SDT_ARM64CSel>;
120 def ARM64csinc : SDNode<"ARM64ISD::CSINC", SDT_ARM64CSel>;
121 def ARM64retflag : SDNode<"ARM64ISD::RET_FLAG", SDTNone,
122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
123 def ARM64adc : SDNode<"ARM64ISD::ADC", SDTBinaryArithWithFlagsIn >;
124 def ARM64sbc : SDNode<"ARM64ISD::SBC", SDTBinaryArithWithFlagsIn>;
125 def ARM64add_flag : SDNode<"ARM64ISD::ADDS", SDTBinaryArithWithFlagsOut,
127 def ARM64sub_flag : SDNode<"ARM64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
128 def ARM64and_flag : SDNode<"ARM64ISD::ANDS", SDTBinaryArithWithFlagsOut>;
129 def ARM64adc_flag : SDNode<"ARM64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
130 def ARM64sbc_flag : SDNode<"ARM64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
132 def ARM64threadpointer : SDNode<"ARM64ISD::THREAD_POINTER", SDTPtrLeaf>;
134 def ARM64fcmp : SDNode<"ARM64ISD::FCMP", SDT_ARM64FCmp>;
136 def ARM64fmax : SDNode<"ARM64ISD::FMAX", SDTFPBinOp>;
137 def ARM64fmin : SDNode<"ARM64ISD::FMIN", SDTFPBinOp>;
139 def ARM64dup : SDNode<"ARM64ISD::DUP", SDT_ARM64Dup>;
140 def ARM64duplane8 : SDNode<"ARM64ISD::DUPLANE8", SDT_ARM64DupLane>;
141 def ARM64duplane16 : SDNode<"ARM64ISD::DUPLANE16", SDT_ARM64DupLane>;
142 def ARM64duplane32 : SDNode<"ARM64ISD::DUPLANE32", SDT_ARM64DupLane>;
143 def ARM64duplane64 : SDNode<"ARM64ISD::DUPLANE64", SDT_ARM64DupLane>;
145 def ARM64zip1 : SDNode<"ARM64ISD::ZIP1", SDT_ARM64Zip>;
146 def ARM64zip2 : SDNode<"ARM64ISD::ZIP2", SDT_ARM64Zip>;
147 def ARM64uzp1 : SDNode<"ARM64ISD::UZP1", SDT_ARM64Zip>;
148 def ARM64uzp2 : SDNode<"ARM64ISD::UZP2", SDT_ARM64Zip>;
149 def ARM64trn1 : SDNode<"ARM64ISD::TRN1", SDT_ARM64Zip>;
150 def ARM64trn2 : SDNode<"ARM64ISD::TRN2", SDT_ARM64Zip>;
152 def ARM64movi_edit : SDNode<"ARM64ISD::MOVIedit", SDT_ARM64MOVIedit>;
153 def ARM64movi_shift : SDNode<"ARM64ISD::MOVIshift", SDT_ARM64MOVIshift>;
154 def ARM64movi_msl : SDNode<"ARM64ISD::MOVImsl", SDT_ARM64MOVIshift>;
155 def ARM64mvni_shift : SDNode<"ARM64ISD::MVNIshift", SDT_ARM64MOVIshift>;
156 def ARM64mvni_msl : SDNode<"ARM64ISD::MVNImsl", SDT_ARM64MOVIshift>;
157 def ARM64movi : SDNode<"ARM64ISD::MOVI", SDT_ARM64MOVIedit>;
158 def ARM64fmov : SDNode<"ARM64ISD::FMOV", SDT_ARM64MOVIedit>;
160 def ARM64rev16 : SDNode<"ARM64ISD::REV16", SDT_ARM64UnaryVec>;
161 def ARM64rev32 : SDNode<"ARM64ISD::REV32", SDT_ARM64UnaryVec>;
162 def ARM64rev64 : SDNode<"ARM64ISD::REV64", SDT_ARM64UnaryVec>;
163 def ARM64ext : SDNode<"ARM64ISD::EXT", SDT_ARM64ExtVec>;
165 def ARM64vashr : SDNode<"ARM64ISD::VASHR", SDT_ARM64vshift>;
166 def ARM64vlshr : SDNode<"ARM64ISD::VLSHR", SDT_ARM64vshift>;
167 def ARM64vshl : SDNode<"ARM64ISD::VSHL", SDT_ARM64vshift>;
168 def ARM64sqshli : SDNode<"ARM64ISD::SQSHL_I", SDT_ARM64vshift>;
169 def ARM64uqshli : SDNode<"ARM64ISD::UQSHL_I", SDT_ARM64vshift>;
170 def ARM64sqshlui : SDNode<"ARM64ISD::SQSHLU_I", SDT_ARM64vshift>;
171 def ARM64srshri : SDNode<"ARM64ISD::SRSHR_I", SDT_ARM64vshift>;
172 def ARM64urshri : SDNode<"ARM64ISD::URSHR_I", SDT_ARM64vshift>;
174 def ARM64not: SDNode<"ARM64ISD::NOT", SDT_ARM64unvec>;
175 def ARM64bit: SDNode<"ARM64ISD::BIT", SDT_ARM64trivec>;
177 def ARM64cmeq: SDNode<"ARM64ISD::CMEQ", SDT_ARM64binvec>;
178 def ARM64cmge: SDNode<"ARM64ISD::CMGE", SDT_ARM64binvec>;
179 def ARM64cmgt: SDNode<"ARM64ISD::CMGT", SDT_ARM64binvec>;
180 def ARM64cmhi: SDNode<"ARM64ISD::CMHI", SDT_ARM64binvec>;
181 def ARM64cmhs: SDNode<"ARM64ISD::CMHS", SDT_ARM64binvec>;
183 def ARM64fcmeq: SDNode<"ARM64ISD::FCMEQ", SDT_ARM64fcmp>;
184 def ARM64fcmge: SDNode<"ARM64ISD::FCMGE", SDT_ARM64fcmp>;
185 def ARM64fcmgt: SDNode<"ARM64ISD::FCMGT", SDT_ARM64fcmp>;
187 def ARM64cmeqz: SDNode<"ARM64ISD::CMEQz", SDT_ARM64unvec>;
188 def ARM64cmgez: SDNode<"ARM64ISD::CMGEz", SDT_ARM64unvec>;
189 def ARM64cmgtz: SDNode<"ARM64ISD::CMGTz", SDT_ARM64unvec>;
190 def ARM64cmlez: SDNode<"ARM64ISD::CMLEz", SDT_ARM64unvec>;
191 def ARM64cmltz: SDNode<"ARM64ISD::CMLTz", SDT_ARM64unvec>;
192 def ARM64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
193 (ARM64not (ARM64cmeqz (and node:$LHS, node:$RHS)))>;
195 def ARM64fcmeqz: SDNode<"ARM64ISD::FCMEQz", SDT_ARM64fcmpz>;
196 def ARM64fcmgez: SDNode<"ARM64ISD::FCMGEz", SDT_ARM64fcmpz>;
197 def ARM64fcmgtz: SDNode<"ARM64ISD::FCMGTz", SDT_ARM64fcmpz>;
198 def ARM64fcmlez: SDNode<"ARM64ISD::FCMLEz", SDT_ARM64fcmpz>;
199 def ARM64fcmltz: SDNode<"ARM64ISD::FCMLTz", SDT_ARM64fcmpz>;
201 def ARM64bici: SDNode<"ARM64ISD::BICi", SDT_ARM64vecimm>;
202 def ARM64orri: SDNode<"ARM64ISD::ORRi", SDT_ARM64vecimm>;
204 def ARM64neg : SDNode<"ARM64ISD::NEG", SDT_ARM64unvec>;
206 def ARM64tcret: SDNode<"ARM64ISD::TC_RETURN", SDT_ARM64TCRET,
207 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
209 def ARM64Prefetch : SDNode<"ARM64ISD::PREFETCH", SDT_ARM64PREFETCH,
210 [SDNPHasChain, SDNPSideEffect]>;
212 def ARM64sitof: SDNode<"ARM64ISD::SITOF", SDT_ARM64ITOF>;
213 def ARM64uitof: SDNode<"ARM64ISD::UITOF", SDT_ARM64ITOF>;
215 def ARM64tlsdesc_call : SDNode<"ARM64ISD::TLSDESC_CALL", SDT_ARM64TLSDescCall,
216 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
219 def ARM64WrapperLarge : SDNode<"ARM64ISD::WrapperLarge", SDT_ARM64WrapperLarge>;
222 //===----------------------------------------------------------------------===//
224 //===----------------------------------------------------------------------===//
226 // ARM64 Instruction Predicate Definitions.
228 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
229 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
230 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
231 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
232 def ForCodeSize : Predicate<"ForCodeSize">;
233 def NotForCodeSize : Predicate<"!ForCodeSize">;
235 include "ARM64InstrFormats.td"
237 //===----------------------------------------------------------------------===//
239 //===----------------------------------------------------------------------===//
240 // Miscellaneous instructions.
241 //===----------------------------------------------------------------------===//
243 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
244 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
245 [(ARM64callseq_start timm:$amt)]>;
246 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
247 [(ARM64callseq_end timm:$amt1, timm:$amt2)]>;
248 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
250 let isReMaterializable = 1, isCodeGenOnly = 1 in {
251 // FIXME: The following pseudo instructions are only needed because remat
252 // cannot handle multiple instructions. When that changes, they can be
253 // removed, along with the ARM64Wrapper node.
255 let AddedComplexity = 10 in
256 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
257 [(set GPR64:$dst, (ARM64LOADgot tglobaladdr:$addr))]>,
260 // The MOVaddr instruction should match only when the add is not folded
261 // into a load or store address.
263 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
264 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaladdr:$hi),
265 tglobaladdr:$low))]>,
266 Sched<[WriteAdrAdr]>;
268 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
269 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tjumptable:$hi),
271 Sched<[WriteAdrAdr]>;
273 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
274 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tconstpool:$hi),
276 Sched<[WriteAdrAdr]>;
278 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
279 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tblockaddress:$hi),
280 tblockaddress:$low))]>,
281 Sched<[WriteAdrAdr]>;
283 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
284 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaltlsaddr:$hi),
285 tglobaltlsaddr:$low))]>,
286 Sched<[WriteAdrAdr]>;
288 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
289 [(set GPR64:$dst, (ARM64addlow (ARM64adrp texternalsym:$hi),
290 texternalsym:$low))]>,
291 Sched<[WriteAdrAdr]>;
293 } // isReMaterializable, isCodeGenOnly
295 def : Pat<(ARM64LOADgot tglobaltlsaddr:$addr),
296 (LOADgot tglobaltlsaddr:$addr)>;
298 def : Pat<(ARM64LOADgot texternalsym:$addr),
299 (LOADgot texternalsym:$addr)>;
301 def : Pat<(ARM64LOADgot tconstpool:$addr),
302 (LOADgot tconstpool:$addr)>;
304 //===----------------------------------------------------------------------===//
305 // System instructions.
306 //===----------------------------------------------------------------------===//
308 def HINT : HintI<"hint">;
309 def : InstAlias<"nop", (HINT 0b000)>;
310 def : InstAlias<"yield",(HINT 0b001)>;
311 def : InstAlias<"wfe", (HINT 0b010)>;
312 def : InstAlias<"wfi", (HINT 0b011)>;
313 def : InstAlias<"sev", (HINT 0b100)>;
314 def : InstAlias<"sevl", (HINT 0b101)>;
316 // As far as LLVM is concerned this writes to the system's exclusive monitors.
317 let mayLoad = 1, mayStore = 1 in
318 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
320 def DMB : CRmSystemI<barrier_op, 0b101, "dmb">;
321 def DSB : CRmSystemI<barrier_op, 0b100, "dsb">;
322 def ISB : CRmSystemI<barrier_op, 0b110, "isb">;
323 def : InstAlias<"clrex", (CLREX 0xf)>;
324 def : InstAlias<"isb", (ISB 0xf)>;
328 def MSRcpsr: MSRcpsrI;
330 // The thread pointer (on Linux, at least, where this has been implemented) is
332 def : Pat<(ARM64threadpointer), (MRS 0xde82)>;
334 // Generic system instructions
335 def SYSxt : SystemXtI<0, "sys">;
336 def SYSLxt : SystemLXtI<1, "sysl">;
338 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
339 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
340 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
342 //===----------------------------------------------------------------------===//
343 // Move immediate instructions.
344 //===----------------------------------------------------------------------===//
346 defm MOVK : InsertImmediate<0b11, "movk">;
347 defm MOVN : MoveImmediate<0b00, "movn">;
349 let PostEncoderMethod = "fixMOVZ" in
350 defm MOVZ : MoveImmediate<0b10, "movz">;
352 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
353 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
354 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
355 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
356 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
357 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
359 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
360 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
361 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
362 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
364 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
365 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
366 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
367 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
369 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g3:$sym, 48)>;
370 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g2:$sym, 32)>;
371 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
372 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
374 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
375 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
376 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
378 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g2:$sym, 32)>;
379 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
380 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
382 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
383 isAsCheapAsAMove = 1 in {
384 // FIXME: The following pseudo instructions are only needed because remat
385 // cannot handle multiple instructions. When that changes, we can select
386 // directly to the real instructions and get rid of these pseudos.
389 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
390 [(set GPR32:$dst, imm:$src)]>,
393 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
394 [(set GPR64:$dst, imm:$src)]>,
396 } // isReMaterializable, isCodeGenOnly
398 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
399 // eventual expansion code fewer bits to worry about getting right. Marshalling
400 // the types is a little tricky though:
401 def i64imm_32bit : ImmLeaf<i64, [{
402 return (Imm & 0xffffffffULL) == Imm;
405 def trunc_imm : SDNodeXForm<imm, [{
406 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
409 def : Pat<(i64 i64imm_32bit:$src),
410 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
412 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
414 def : Pat<(ARM64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
415 tglobaladdr:$g1, tglobaladdr:$g0),
416 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
417 tglobaladdr:$g2, 32),
418 tglobaladdr:$g1, 16),
419 tglobaladdr:$g0, 0)>;
421 def : Pat<(ARM64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
422 tblockaddress:$g1, tblockaddress:$g0),
423 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
424 tblockaddress:$g2, 32),
425 tblockaddress:$g1, 16),
426 tblockaddress:$g0, 0)>;
428 def : Pat<(ARM64WrapperLarge tconstpool:$g3, tconstpool:$g2,
429 tconstpool:$g1, tconstpool:$g0),
430 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
435 def : Pat<(ARM64WrapperLarge tjumptable:$g3, tjumptable:$g2,
436 tjumptable:$g1, tjumptable:$g0),
437 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
443 //===----------------------------------------------------------------------===//
444 // Arithmetic instructions.
445 //===----------------------------------------------------------------------===//
447 // Add/subtract with carry.
448 defm ADC : AddSubCarry<0, "adc", "adcs", ARM64adc, ARM64adc_flag>;
449 defm SBC : AddSubCarry<1, "sbc", "sbcs", ARM64sbc, ARM64sbc_flag>;
451 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
452 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
453 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
454 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
457 defm ADD : AddSub<0, "add", add>;
458 defm SUB : AddSub<1, "sub">;
460 defm ADDS : AddSubS<0, "adds", ARM64add_flag>;
461 defm SUBS : AddSubS<1, "subs", ARM64sub_flag>;
463 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
464 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
465 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
466 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
467 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
468 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
469 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
470 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
471 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
472 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
473 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
474 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
475 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
476 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
477 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
478 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
479 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
481 // Because of the immediate format for add/sub-imm instructions, the
482 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
483 // These patterns capture that transformation.
484 let AddedComplexity = 1 in {
485 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
486 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
487 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
488 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
489 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
490 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
491 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
492 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
495 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
496 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
497 def : InstAlias<"neg $dst, $src, $shift",
498 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift:$shift)>;
499 def : InstAlias<"neg $dst, $src, $shift",
500 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift:$shift)>;
502 // Because of the immediate format for add/sub-imm instructions, the
503 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
504 // These patterns capture that transformation.
505 let AddedComplexity = 1 in {
506 def : Pat<(ARM64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
507 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
508 def : Pat<(ARM64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
509 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
510 def : Pat<(ARM64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
511 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
512 def : Pat<(ARM64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
513 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
516 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
517 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
518 def : InstAlias<"negs $dst, $src, $shift",
519 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift:$shift)>;
520 def : InstAlias<"negs $dst, $src, $shift",
521 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift:$shift)>;
523 // Unsigned/Signed divide
524 defm UDIV : Div<0, "udiv", udiv>;
525 defm SDIV : Div<1, "sdiv", sdiv>;
526 let isCodeGenOnly = 1 in {
527 defm UDIV_Int : Div<0, "udiv", int_arm64_udiv>;
528 defm SDIV_Int : Div<1, "sdiv", int_arm64_sdiv>;
532 defm ASRV : Shift<0b10, "asrv", sra>;
533 defm LSLV : Shift<0b00, "lslv", shl>;
534 defm LSRV : Shift<0b01, "lsrv", srl>;
535 defm RORV : Shift<0b11, "rorv", rotr>;
537 def : ShiftAlias<"asr", ASRVWr, GPR32>;
538 def : ShiftAlias<"asr", ASRVXr, GPR64>;
539 def : ShiftAlias<"lsl", LSLVWr, GPR32>;
540 def : ShiftAlias<"lsl", LSLVXr, GPR64>;
541 def : ShiftAlias<"lsr", LSRVWr, GPR32>;
542 def : ShiftAlias<"lsr", LSRVXr, GPR64>;
543 def : ShiftAlias<"ror", RORVWr, GPR32>;
544 def : ShiftAlias<"ror", RORVXr, GPR64>;
547 let AddedComplexity = 7 in {
548 defm MADD : MulAccum<0, "madd", add>;
549 defm MSUB : MulAccum<1, "msub", sub>;
551 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
552 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
553 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
554 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
556 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
557 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
558 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
559 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
560 } // AddedComplexity = 7
562 let AddedComplexity = 5 in {
563 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
564 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
565 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
566 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
568 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
569 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
570 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
571 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
573 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
574 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
575 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
576 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
577 } // AddedComplexity = 5
579 def : MulAccumWAlias<"mul", MADDWrrr>;
580 def : MulAccumXAlias<"mul", MADDXrrr>;
581 def : MulAccumWAlias<"mneg", MSUBWrrr>;
582 def : MulAccumXAlias<"mneg", MSUBXrrr>;
583 def : WideMulAccumAlias<"smull", SMADDLrrr>;
584 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
585 def : WideMulAccumAlias<"umull", UMADDLrrr>;
586 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
589 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
590 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
593 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_arm64_crc32b, "crc32b">;
594 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_arm64_crc32h, "crc32h">;
595 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_arm64_crc32w, "crc32w">;
596 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_arm64_crc32x, "crc32x">;
598 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_arm64_crc32cb, "crc32cb">;
599 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_arm64_crc32ch, "crc32ch">;
600 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_arm64_crc32cw, "crc32cw">;
601 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_arm64_crc32cx, "crc32cx">;
604 //===----------------------------------------------------------------------===//
605 // Logical instructions.
606 //===----------------------------------------------------------------------===//
609 defm ANDS : LogicalImmS<0b11, "ands", ARM64and_flag>;
610 defm AND : LogicalImm<0b00, "and", and>;
611 defm EOR : LogicalImm<0b10, "eor", xor>;
612 defm ORR : LogicalImm<0b01, "orr", or>;
614 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
615 logical_imm32:$imm)>;
616 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
617 logical_imm64:$imm)>;
621 defm ANDS : LogicalRegS<0b11, 0, "ands">;
622 defm BICS : LogicalRegS<0b11, 1, "bics">;
623 defm AND : LogicalReg<0b00, 0, "and", and>;
624 defm BIC : LogicalReg<0b00, 1, "bic",
625 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
626 defm EON : LogicalReg<0b10, 1, "eon",
627 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
628 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
629 defm ORN : LogicalReg<0b01, 1, "orn",
630 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
631 defm ORR : LogicalReg<0b01, 0, "orr", or>;
633 def : InstAlias<"tst $src1, $src2",
634 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)>;
635 def : InstAlias<"tst $src1, $src2",
636 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2)>;
638 def : InstAlias<"tst $src1, $src2",
639 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)>;
640 def : InstAlias<"tst $src1, $src2",
641 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)>;
643 def : InstAlias<"tst $src1, $src2, $sh",
644 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift:$sh)>;
645 def : InstAlias<"tst $src1, $src2, $sh",
646 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift:$sh)>;
648 def : InstAlias<"mvn $Wd, $Wm",
649 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0)>;
650 def : InstAlias<"mvn $Xd, $Xm",
651 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0)>;
653 def : InstAlias<"mvn $Wd, $Wm, $sh",
654 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift:$sh)>;
655 def : InstAlias<"mvn $Xd, $Xm, $sh",
656 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift:$sh)>;
658 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
659 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
662 //===----------------------------------------------------------------------===//
663 // One operand data processing instructions.
664 //===----------------------------------------------------------------------===//
666 defm CLS : OneOperandData<0b101, "cls">;
667 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
668 defm RBIT : OneOperandData<0b000, "rbit">;
669 def REV16Wr : OneWRegData<0b001, "rev16",
670 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
671 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
673 def : Pat<(cttz GPR32:$Rn),
674 (CLZWr (RBITWr GPR32:$Rn))>;
675 def : Pat<(cttz GPR64:$Rn),
676 (CLZXr (RBITXr GPR64:$Rn))>;
677 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
680 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
684 // Unlike the other one operand instructions, the instructions with the "rev"
685 // mnemonic do *not* just different in the size bit, but actually use different
686 // opcode bits for the different sizes.
687 def REVWr : OneWRegData<0b010, "rev", bswap>;
688 def REVXr : OneXRegData<0b011, "rev", bswap>;
689 def REV32Xr : OneXRegData<0b010, "rev32",
690 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
692 // The bswap commutes with the rotr so we want a pattern for both possible
694 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
695 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
697 //===----------------------------------------------------------------------===//
698 // Bitfield immediate extraction instruction.
699 //===----------------------------------------------------------------------===//
700 let neverHasSideEffects = 1 in
701 defm EXTR : ExtractImm<"extr">;
702 def : InstAlias<"ror $dst, $src, $shift",
703 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
704 def : InstAlias<"ror $dst, $src, $shift",
705 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
707 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
708 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
709 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
710 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
712 //===----------------------------------------------------------------------===//
713 // Other bitfield immediate instructions.
714 //===----------------------------------------------------------------------===//
715 let neverHasSideEffects = 1 in {
716 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
717 defm SBFM : BitfieldImm<0b00, "sbfm">;
718 defm UBFM : BitfieldImm<0b10, "ubfm">;
721 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
722 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
723 return CurDAG->getTargetConstant(enc, MVT::i64);
726 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
727 uint64_t enc = 31 - N->getZExtValue();
728 return CurDAG->getTargetConstant(enc, MVT::i64);
731 // min(7, 31 - shift_amt)
732 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
733 uint64_t enc = 31 - N->getZExtValue();
734 enc = enc > 7 ? 7 : enc;
735 return CurDAG->getTargetConstant(enc, MVT::i64);
738 // min(15, 31 - shift_amt)
739 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
740 uint64_t enc = 31 - N->getZExtValue();
741 enc = enc > 15 ? 15 : enc;
742 return CurDAG->getTargetConstant(enc, MVT::i64);
745 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
746 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
747 return CurDAG->getTargetConstant(enc, MVT::i64);
750 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
751 uint64_t enc = 63 - N->getZExtValue();
752 return CurDAG->getTargetConstant(enc, MVT::i64);
755 // min(7, 63 - shift_amt)
756 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
757 uint64_t enc = 63 - N->getZExtValue();
758 enc = enc > 7 ? 7 : enc;
759 return CurDAG->getTargetConstant(enc, MVT::i64);
762 // min(15, 63 - shift_amt)
763 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
764 uint64_t enc = 63 - N->getZExtValue();
765 enc = enc > 15 ? 15 : enc;
766 return CurDAG->getTargetConstant(enc, MVT::i64);
769 // min(31, 63 - shift_amt)
770 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
771 uint64_t enc = 63 - N->getZExtValue();
772 enc = enc > 31 ? 31 : enc;
773 return CurDAG->getTargetConstant(enc, MVT::i64);
776 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
777 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
778 (i64 (i32shift_b imm0_31:$imm)))>;
779 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
780 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
781 (i64 (i64shift_b imm0_63:$imm)))>;
783 let AddedComplexity = 10 in {
784 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
785 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
786 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
787 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
790 def : InstAlias<"asr $dst, $src, $shift",
791 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
792 def : InstAlias<"asr $dst, $src, $shift",
793 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
794 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
795 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
796 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
797 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
798 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
800 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
801 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
802 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
803 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
805 def : InstAlias<"lsr $dst, $src, $shift",
806 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
807 def : InstAlias<"lsr $dst, $src, $shift",
808 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
809 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
810 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
811 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
812 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
813 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
815 //===----------------------------------------------------------------------===//
816 // Conditionally set flags instructions.
817 //===----------------------------------------------------------------------===//
818 defm CCMN : CondSetFlagsImm<0, "ccmn">;
819 defm CCMP : CondSetFlagsImm<1, "ccmp">;
821 defm CCMN : CondSetFlagsReg<0, "ccmn">;
822 defm CCMP : CondSetFlagsReg<1, "ccmp">;
824 //===----------------------------------------------------------------------===//
825 // Conditional select instructions.
826 //===----------------------------------------------------------------------===//
827 defm CSEL : CondSelect<0, 0b00, "csel">;
829 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
830 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
831 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
832 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
834 def : Pat<(ARM64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
835 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
836 def : Pat<(ARM64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
837 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
838 def : Pat<(ARM64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
839 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
840 def : Pat<(ARM64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
841 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
842 def : Pat<(ARM64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
843 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
844 def : Pat<(ARM64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
845 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
847 def : Pat<(ARM64csel (i32 0), (i32 1), (i32 imm:$cc), CPSR),
848 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
849 def : Pat<(ARM64csel (i64 0), (i64 1), (i32 imm:$cc), CPSR),
850 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
851 def : Pat<(ARM64csel (i32 0), (i32 -1), (i32 imm:$cc), CPSR),
852 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
853 def : Pat<(ARM64csel (i64 0), (i64 -1), (i32 imm:$cc), CPSR),
854 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
856 // The inverse of the condition code from the alias instruction is what is used
857 // in the aliased instruction. The parser all ready inverts the condition code
858 // for these aliases.
859 // FIXME: Is this the correct way to handle these aliases?
860 def : InstAlias<"cset $dst, $cc", (CSINCWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
861 def : InstAlias<"cset $dst, $cc", (CSINCXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
863 def : InstAlias<"csetm $dst, $cc", (CSINVWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
864 def : InstAlias<"csetm $dst, $cc", (CSINVXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
866 def : InstAlias<"cinc $dst, $src, $cc",
867 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
868 def : InstAlias<"cinc $dst, $src, $cc",
869 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
871 def : InstAlias<"cinv $dst, $src, $cc",
872 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
873 def : InstAlias<"cinv $dst, $src, $cc",
874 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
876 def : InstAlias<"cneg $dst, $src, $cc",
877 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
878 def : InstAlias<"cneg $dst, $src, $cc",
879 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
881 //===----------------------------------------------------------------------===//
882 // PC-relative instructions.
883 //===----------------------------------------------------------------------===//
884 let isReMaterializable = 1 in {
885 let neverHasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
886 def ADR : ADRI<0, "adr", adrlabel, []>;
887 } // neverHasSideEffects = 1
889 def ADRP : ADRI<1, "adrp", adrplabel,
890 [(set GPR64:$Xd, (ARM64adrp tglobaladdr:$label))]>;
891 } // isReMaterializable = 1
893 // page address of a constant pool entry, block address
894 def : Pat<(ARM64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
895 def : Pat<(ARM64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
897 //===----------------------------------------------------------------------===//
898 // Unconditional branch (register) instructions.
899 //===----------------------------------------------------------------------===//
901 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
902 def RET : BranchReg<0b0010, "ret", []>;
903 def DRPS : SpecialReturn<0b0101, "drps">;
904 def ERET : SpecialReturn<0b0100, "eret">;
905 } // isReturn = 1, isTerminator = 1, isBarrier = 1
907 // Default to the LR register.
908 def : InstAlias<"ret", (RET LR)>;
910 let isCall = 1, Defs = [LR], Uses = [SP] in {
911 def BLR : BranchReg<0b0001, "blr", [(ARM64call GPR64:$Rn)]>;
914 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
915 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
916 } // isBranch, isTerminator, isBarrier, isIndirectBranch
918 // Create a separate pseudo-instruction for codegen to use so that we don't
919 // flag lr as used in every function. It'll be restored before the RET by the
920 // epilogue if it's legitimately used.
921 def RET_ReallyLR : Pseudo<(outs), (ins), [(ARM64retflag)]> {
922 let isTerminator = 1;
927 // This is a directive-like pseudo-instruction. The purpose is to insert an
928 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
929 // (which in the usual case is a BLR).
930 let hasSideEffects = 1 in
931 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
932 let AsmString = ".tlsdesccall $sym";
935 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
936 // gets expanded to two MCInsts during lowering.
937 let isCall = 1, Defs = [LR] in
939 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
940 [(ARM64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
942 def : Pat<(ARM64tlsdesc_call GPR64:$dest, texternalsym:$sym),
943 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
944 //===----------------------------------------------------------------------===//
945 // Conditional branch (immediate) instruction.
946 //===----------------------------------------------------------------------===//
947 def Bcc : BranchCond;
949 //===----------------------------------------------------------------------===//
950 // Compare-and-branch instructions.
951 //===----------------------------------------------------------------------===//
952 defm CBZ : CmpBranch<0, "cbz", ARM64cbz>;
953 defm CBNZ : CmpBranch<1, "cbnz", ARM64cbnz>;
955 //===----------------------------------------------------------------------===//
956 // Test-bit-and-branch instructions.
957 //===----------------------------------------------------------------------===//
958 def TBZ : TestBranch<0, "tbz", ARM64tbz>;
959 def TBNZ : TestBranch<1, "tbnz", ARM64tbnz>;
961 //===----------------------------------------------------------------------===//
962 // Unconditional branch (immediate) instructions.
963 //===----------------------------------------------------------------------===//
964 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
965 def B : BranchImm<0, "b", [(br bb:$addr)]>;
966 } // isBranch, isTerminator, isBarrier
968 let isCall = 1, Defs = [LR], Uses = [SP] in {
969 def BL : CallImm<1, "bl", [(ARM64call tglobaladdr:$addr)]>;
971 def : Pat<(ARM64call texternalsym:$func), (BL texternalsym:$func)>;
973 //===----------------------------------------------------------------------===//
974 // Exception generation instructions.
975 //===----------------------------------------------------------------------===//
976 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
977 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
978 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
979 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
980 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
981 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
982 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
983 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
985 // DCPSn defaults to an immediate operand of zero if unspecified.
986 def : InstAlias<"dcps1", (DCPS1 0)>;
987 def : InstAlias<"dcps2", (DCPS2 0)>;
988 def : InstAlias<"dcps3", (DCPS3 0)>;
990 //===----------------------------------------------------------------------===//
991 // Load instructions.
992 //===----------------------------------------------------------------------===//
994 // Pair (indexed, offset)
995 def LDPWi : LoadPairOffset<0b00, 0, GPR32, am_indexed32simm7, "ldp">;
996 def LDPXi : LoadPairOffset<0b10, 0, GPR64, am_indexed64simm7, "ldp">;
997 def LDPSi : LoadPairOffset<0b00, 1, FPR32, am_indexed32simm7, "ldp">;
998 def LDPDi : LoadPairOffset<0b01, 1, FPR64, am_indexed64simm7, "ldp">;
999 def LDPQi : LoadPairOffset<0b10, 1, FPR128, am_indexed128simm7, "ldp">;
1001 def LDPSWi : LoadPairOffset<0b01, 0, GPR64, am_indexed32simm7, "ldpsw">;
1003 // Pair (pre-indexed)
1004 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "ldp">;
1005 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "ldp">;
1006 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "ldp">;
1007 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "ldp">;
1008 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "ldp">;
1010 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, am_indexed32simm7_wb, "ldpsw">;
1012 // Pair (post-indexed)
1013 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1014 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1015 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1016 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1017 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1019 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1022 // Pair (no allocate)
1023 def LDNPWi : LoadPairNoAlloc<0b00, 0, GPR32, am_indexed32simm7, "ldnp">;
1024 def LDNPXi : LoadPairNoAlloc<0b10, 0, GPR64, am_indexed64simm7, "ldnp">;
1025 def LDNPSi : LoadPairNoAlloc<0b00, 1, FPR32, am_indexed32simm7, "ldnp">;
1026 def LDNPDi : LoadPairNoAlloc<0b01, 1, FPR64, am_indexed64simm7, "ldnp">;
1027 def LDNPQi : LoadPairNoAlloc<0b10, 1, FPR128, am_indexed128simm7, "ldnp">;
1030 // (register offset)
1033 let AddedComplexity = 10 in {
1035 def LDRBBro : Load8RO<0b00, 0, 0b01, GPR32, "ldrb",
1036 [(set GPR32:$Rt, (zextloadi8 ro_indexed8:$addr))]>;
1037 def LDRHHro : Load16RO<0b01, 0, 0b01, GPR32, "ldrh",
1038 [(set GPR32:$Rt, (zextloadi16 ro_indexed16:$addr))]>;
1039 def LDRWro : Load32RO<0b10, 0, 0b01, GPR32, "ldr",
1040 [(set GPR32:$Rt, (load ro_indexed32:$addr))]>;
1041 def LDRXro : Load64RO<0b11, 0, 0b01, GPR64, "ldr",
1042 [(set GPR64:$Rt, (load ro_indexed64:$addr))]>;
1045 def LDRBro : Load8RO<0b00, 1, 0b01, FPR8, "ldr",
1046 [(set FPR8:$Rt, (load ro_indexed8:$addr))]>;
1047 def LDRHro : Load16RO<0b01, 1, 0b01, FPR16, "ldr",
1048 [(set (f16 FPR16:$Rt), (load ro_indexed16:$addr))]>;
1049 def LDRSro : Load32RO<0b10, 1, 0b01, FPR32, "ldr",
1050 [(set (f32 FPR32:$Rt), (load ro_indexed32:$addr))]>;
1051 def LDRDro : Load64RO<0b11, 1, 0b01, FPR64, "ldr",
1052 [(set (f64 FPR64:$Rt), (load ro_indexed64:$addr))]>;
1053 def LDRQro : Load128RO<0b00, 1, 0b11, FPR128, "ldr", []> {
1057 // For regular load, we do not have any alignment requirement.
1058 // Thus, it is safe to directly map the vector loads with interesting
1059 // addressing modes.
1060 // FIXME: We could do the same for bitconvert to floating point vectors.
1061 def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 ro_indexed8:$addr)))),
1062 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1063 (LDRBro ro_indexed8:$addr), bsub)>;
1064 def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 ro_indexed8:$addr)))),
1065 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1066 (LDRBro ro_indexed8:$addr), bsub)>;
1067 def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 ro_indexed16:$addr)))),
1068 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1069 (LDRHro ro_indexed16:$addr), hsub)>;
1070 def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 ro_indexed16:$addr)))),
1071 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1072 (LDRHro ro_indexed16:$addr), hsub)>;
1073 def : Pat <(v2i32 (scalar_to_vector (i32 (load ro_indexed32:$addr)))),
1074 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1075 (LDRSro ro_indexed32:$addr), ssub)>;
1076 def : Pat <(v4i32 (scalar_to_vector (i32 (load ro_indexed32:$addr)))),
1077 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1078 (LDRSro ro_indexed32:$addr), ssub)>;
1079 def : Pat <(v1i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
1080 (LDRDro ro_indexed64:$addr)>;
1081 def : Pat <(v2i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
1082 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1083 (LDRDro ro_indexed64:$addr), dsub)>;
1085 // Match all load 64 bits width whose type is compatible with FPR64
1086 def : Pat<(v2f32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1087 def : Pat<(v1f64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1088 def : Pat<(v8i8 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1089 def : Pat<(v4i16 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1090 def : Pat<(v2i32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1091 def : Pat<(v1i64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1093 // Match all load 128 bits width whose type is compatible with FPR128
1094 def : Pat<(v4f32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1095 def : Pat<(v2f64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1096 def : Pat<(v16i8 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1097 def : Pat<(v8i16 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1098 def : Pat<(v4i32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1099 def : Pat<(v2i64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1100 def : Pat<(f128 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1102 // Load sign-extended half-word
1103 def LDRSHWro : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh",
1104 [(set GPR32:$Rt, (sextloadi16 ro_indexed16:$addr))]>;
1105 def LDRSHXro : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh",
1106 [(set GPR64:$Rt, (sextloadi16 ro_indexed16:$addr))]>;
1108 // Load sign-extended byte
1109 def LDRSBWro : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb",
1110 [(set GPR32:$Rt, (sextloadi8 ro_indexed8:$addr))]>;
1111 def LDRSBXro : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb",
1112 [(set GPR64:$Rt, (sextloadi8 ro_indexed8:$addr))]>;
1114 // Load sign-extended word
1115 def LDRSWro : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw",
1116 [(set GPR64:$Rt, (sextloadi32 ro_indexed32:$addr))]>;
1119 def PRFMro : PrefetchRO<0b11, 0, 0b10, "prfm",
1120 [(ARM64Prefetch imm:$Rt, ro_indexed64:$addr)]>;
1123 def : Pat<(i64 (zextloadi8 ro_indexed8:$addr)),
1124 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1125 def : Pat<(i64 (zextloadi16 ro_indexed16:$addr)),
1126 (SUBREG_TO_REG (i64 0), (LDRHHro ro_indexed16:$addr), sub_32)>;
1127 def : Pat<(i64 (zextloadi32 ro_indexed32:$addr)),
1128 (SUBREG_TO_REG (i64 0), (LDRWro ro_indexed32:$addr), sub_32)>;
1130 // zextloadi1 -> zextloadi8
1131 def : Pat<(i32 (zextloadi1 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1132 def : Pat<(i64 (zextloadi1 ro_indexed8:$addr)),
1133 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1135 // extload -> zextload
1136 def : Pat<(i32 (extloadi16 ro_indexed16:$addr)), (LDRHHro ro_indexed16:$addr)>;
1137 def : Pat<(i32 (extloadi8 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1138 def : Pat<(i32 (extloadi1 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1139 def : Pat<(i64 (extloadi32 ro_indexed32:$addr)),
1140 (SUBREG_TO_REG (i64 0), (LDRWro ro_indexed32:$addr), sub_32)>;
1141 def : Pat<(i64 (extloadi16 ro_indexed16:$addr)),
1142 (SUBREG_TO_REG (i64 0), (LDRHHro ro_indexed16:$addr), sub_32)>;
1143 def : Pat<(i64 (extloadi8 ro_indexed8:$addr)),
1144 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1145 def : Pat<(i64 (extloadi1 ro_indexed8:$addr)),
1146 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1148 } // AddedComplexity = 10
1151 // (unsigned immediate)
1153 def LDRXui : LoadUI<0b11, 0, 0b01, GPR64, am_indexed64, "ldr",
1154 [(set GPR64:$Rt, (load am_indexed64:$addr))]>;
1155 def LDRWui : LoadUI<0b10, 0, 0b01, GPR32, am_indexed32, "ldr",
1156 [(set GPR32:$Rt, (load am_indexed32:$addr))]>;
1157 def LDRBui : LoadUI<0b00, 1, 0b01, FPR8, am_indexed8, "ldr",
1158 [(set FPR8:$Rt, (load am_indexed8:$addr))]>;
1159 def LDRHui : LoadUI<0b01, 1, 0b01, FPR16, am_indexed16, "ldr",
1160 [(set (f16 FPR16:$Rt), (load am_indexed16:$addr))]>;
1161 def LDRSui : LoadUI<0b10, 1, 0b01, FPR32, am_indexed32, "ldr",
1162 [(set (f32 FPR32:$Rt), (load am_indexed32:$addr))]>;
1163 def LDRDui : LoadUI<0b11, 1, 0b01, FPR64, am_indexed64, "ldr",
1164 [(set (f64 FPR64:$Rt), (load am_indexed64:$addr))]>;
1165 def LDRQui : LoadUI<0b00, 1, 0b11, FPR128, am_indexed128, "ldr",
1166 [(set (f128 FPR128:$Rt), (load am_indexed128:$addr))]>;
1168 // For regular load, we do not have any alignment requirement.
1169 // Thus, it is safe to directly map the vector loads with interesting
1170 // addressing modes.
1171 // FIXME: We could do the same for bitconvert to floating point vectors.
1172 def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 am_indexed8:$addr)))),
1173 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1174 (LDRBui am_indexed8:$addr), bsub)>;
1175 def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 am_indexed8:$addr)))),
1176 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1177 (LDRBui am_indexed8:$addr), bsub)>;
1178 def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 am_indexed16:$addr)))),
1179 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1180 (LDRHui am_indexed16:$addr), hsub)>;
1181 def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 am_indexed16:$addr)))),
1182 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1183 (LDRHui am_indexed16:$addr), hsub)>;
1184 def : Pat <(v2i32 (scalar_to_vector (i32 (load am_indexed32:$addr)))),
1185 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1186 (LDRSui am_indexed32:$addr), ssub)>;
1187 def : Pat <(v4i32 (scalar_to_vector (i32 (load am_indexed32:$addr)))),
1188 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1189 (LDRSui am_indexed32:$addr), ssub)>;
1190 def : Pat <(v1i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
1191 (LDRDui am_indexed64:$addr)>;
1192 def : Pat <(v2i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
1193 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1194 (LDRDui am_indexed64:$addr), dsub)>;
1196 // Match all load 64 bits width whose type is compatible with FPR64
1197 def : Pat<(v2f32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1198 def : Pat<(v1f64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1199 def : Pat<(v8i8 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1200 def : Pat<(v4i16 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1201 def : Pat<(v2i32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1202 def : Pat<(v1i64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1204 // Match all load 128 bits width whose type is compatible with FPR128
1205 def : Pat<(v4f32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1206 def : Pat<(v2f64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1207 def : Pat<(v16i8 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1208 def : Pat<(v8i16 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1209 def : Pat<(v4i32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1210 def : Pat<(v2i64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1211 def : Pat<(f128 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1213 def LDRHHui : LoadUI<0b01, 0, 0b01, GPR32, am_indexed16, "ldrh",
1214 [(set GPR32:$Rt, (zextloadi16 am_indexed16:$addr))]>;
1215 def LDRBBui : LoadUI<0b00, 0, 0b01, GPR32, am_indexed8, "ldrb",
1216 [(set GPR32:$Rt, (zextloadi8 am_indexed8:$addr))]>;
1218 def : Pat<(i64 (zextloadi8 am_indexed8:$addr)),
1219 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1220 def : Pat<(i64 (zextloadi16 am_indexed16:$addr)),
1221 (SUBREG_TO_REG (i64 0), (LDRHHui am_indexed16:$addr), sub_32)>;
1223 // zextloadi1 -> zextloadi8
1224 def : Pat<(i32 (zextloadi1 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1225 def : Pat<(i64 (zextloadi1 am_indexed8:$addr)),
1226 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1228 // extload -> zextload
1229 def : Pat<(i32 (extloadi16 am_indexed16:$addr)), (LDRHHui am_indexed16:$addr)>;
1230 def : Pat<(i32 (extloadi8 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1231 def : Pat<(i32 (extloadi1 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1232 def : Pat<(i64 (extloadi32 am_indexed32:$addr)),
1233 (SUBREG_TO_REG (i64 0), (LDRWui am_indexed32:$addr), sub_32)>;
1234 def : Pat<(i64 (extloadi16 am_indexed16:$addr)),
1235 (SUBREG_TO_REG (i64 0), (LDRHHui am_indexed16:$addr), sub_32)>;
1236 def : Pat<(i64 (extloadi8 am_indexed8:$addr)),
1237 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1238 def : Pat<(i64 (extloadi1 am_indexed8:$addr)),
1239 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1241 // load sign-extended half-word
1242 def LDRSHWui : LoadUI<0b01, 0, 0b11, GPR32, am_indexed16, "ldrsh",
1243 [(set GPR32:$Rt, (sextloadi16 am_indexed16:$addr))]>;
1244 def LDRSHXui : LoadUI<0b01, 0, 0b10, GPR64, am_indexed16, "ldrsh",
1245 [(set GPR64:$Rt, (sextloadi16 am_indexed16:$addr))]>;
1247 // load sign-extended byte
1248 def LDRSBWui : LoadUI<0b00, 0, 0b11, GPR32, am_indexed8, "ldrsb",
1249 [(set GPR32:$Rt, (sextloadi8 am_indexed8:$addr))]>;
1250 def LDRSBXui : LoadUI<0b00, 0, 0b10, GPR64, am_indexed8, "ldrsb",
1251 [(set GPR64:$Rt, (sextloadi8 am_indexed8:$addr))]>;
1253 // load sign-extended word
1254 def LDRSWui : LoadUI<0b10, 0, 0b10, GPR64, am_indexed32, "ldrsw",
1255 [(set GPR64:$Rt, (sextloadi32 am_indexed32:$addr))]>;
1257 // load zero-extended word
1258 def : Pat<(i64 (zextloadi32 am_indexed32:$addr)),
1259 (SUBREG_TO_REG (i64 0), (LDRWui am_indexed32:$addr), sub_32)>;
1262 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1263 [(ARM64Prefetch imm:$Rt, am_indexed64:$addr)]>;
1267 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1268 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1269 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1270 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1271 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1273 // load sign-extended word
1274 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1277 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1278 // [(ARM64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1281 // (unscaled immediate)
1282 def LDURXi : LoadUnscaled<0b11, 0, 0b01, GPR64, am_unscaled64, "ldur",
1283 [(set GPR64:$Rt, (load am_unscaled64:$addr))]>;
1284 def LDURWi : LoadUnscaled<0b10, 0, 0b01, GPR32, am_unscaled32, "ldur",
1285 [(set GPR32:$Rt, (load am_unscaled32:$addr))]>;
1286 def LDURBi : LoadUnscaled<0b00, 1, 0b01, FPR8, am_unscaled8, "ldur",
1287 [(set FPR8:$Rt, (load am_unscaled8:$addr))]>;
1288 def LDURHi : LoadUnscaled<0b01, 1, 0b01, FPR16, am_unscaled16, "ldur",
1289 [(set (f16 FPR16:$Rt), (load am_unscaled16:$addr))]>;
1290 def LDURSi : LoadUnscaled<0b10, 1, 0b01, FPR32, am_unscaled32, "ldur",
1291 [(set (f32 FPR32:$Rt), (load am_unscaled32:$addr))]>;
1292 def LDURDi : LoadUnscaled<0b11, 1, 0b01, FPR64, am_unscaled64, "ldur",
1293 [(set (f64 FPR64:$Rt), (load am_unscaled64:$addr))]>;
1294 def LDURQi : LoadUnscaled<0b00, 1, 0b11, FPR128, am_unscaled128, "ldur",
1295 [(set (v2f64 FPR128:$Rt), (load am_unscaled128:$addr))]>;
1298 : LoadUnscaled<0b01, 0, 0b01, GPR32, am_unscaled16, "ldurh",
1299 [(set GPR32:$Rt, (zextloadi16 am_unscaled16:$addr))]>;
1301 : LoadUnscaled<0b00, 0, 0b01, GPR32, am_unscaled8, "ldurb",
1302 [(set GPR32:$Rt, (zextloadi8 am_unscaled8:$addr))]>;
1304 // Match all load 64 bits width whose type is compatible with FPR64
1305 def : Pat<(v2f32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1306 def : Pat<(v1f64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1307 def : Pat<(v8i8 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1308 def : Pat<(v4i16 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1309 def : Pat<(v2i32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1310 def : Pat<(v1i64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1312 // Match all load 128 bits width whose type is compatible with FPR128
1313 def : Pat<(v4f32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1314 def : Pat<(v2f64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1315 def : Pat<(v16i8 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1316 def : Pat<(v8i16 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1317 def : Pat<(v4i32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1318 def : Pat<(v2i64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1319 def : Pat<(f128 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1322 def : Pat<(i32 (extloadi16 am_unscaled16:$addr)), (LDURHHi am_unscaled16:$addr)>;
1323 def : Pat<(i32 (extloadi8 am_unscaled8:$addr)), (LDURBBi am_unscaled8:$addr)>;
1324 def : Pat<(i32 (extloadi1 am_unscaled8:$addr)), (LDURBBi am_unscaled8:$addr)>;
1325 def : Pat<(i64 (extloadi32 am_unscaled32:$addr)),
1326 (SUBREG_TO_REG (i64 0), (LDURWi am_unscaled32:$addr), sub_32)>;
1327 def : Pat<(i64 (extloadi16 am_unscaled16:$addr)),
1328 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1329 def : Pat<(i64 (extloadi8 am_unscaled8:$addr)),
1330 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1331 def : Pat<(i64 (extloadi1 am_unscaled8:$addr)),
1332 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1334 def : Pat<(i32 (zextloadi16 am_unscaled16:$addr)),
1335 (LDURHHi am_unscaled16:$addr)>;
1336 def : Pat<(i32 (zextloadi8 am_unscaled8:$addr)),
1337 (LDURBBi am_unscaled8:$addr)>;
1338 def : Pat<(i32 (zextloadi1 am_unscaled8:$addr)),
1339 (LDURBBi am_unscaled8:$addr)>;
1340 def : Pat<(i64 (zextloadi32 am_unscaled32:$addr)),
1341 (SUBREG_TO_REG (i64 0), (LDURWi am_unscaled32:$addr), sub_32)>;
1342 def : Pat<(i64 (zextloadi16 am_unscaled16:$addr)),
1343 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1344 def : Pat<(i64 (zextloadi8 am_unscaled8:$addr)),
1345 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1346 def : Pat<(i64 (zextloadi1 am_unscaled8:$addr)),
1347 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1351 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1353 // Define new assembler match classes as we want to only match these when
1354 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1355 // associate a DiagnosticType either, as we want the diagnostic for the
1356 // canonical form (the scaled operand) to take precedence.
1357 def MemoryUnscaledFB8Operand : AsmOperandClass {
1358 let Name = "MemoryUnscaledFB8";
1359 let RenderMethod = "addMemoryUnscaledOperands";
1361 def MemoryUnscaledFB16Operand : AsmOperandClass {
1362 let Name = "MemoryUnscaledFB16";
1363 let RenderMethod = "addMemoryUnscaledOperands";
1365 def MemoryUnscaledFB32Operand : AsmOperandClass {
1366 let Name = "MemoryUnscaledFB32";
1367 let RenderMethod = "addMemoryUnscaledOperands";
1369 def MemoryUnscaledFB64Operand : AsmOperandClass {
1370 let Name = "MemoryUnscaledFB64";
1371 let RenderMethod = "addMemoryUnscaledOperands";
1373 def MemoryUnscaledFB128Operand : AsmOperandClass {
1374 let Name = "MemoryUnscaledFB128";
1375 let RenderMethod = "addMemoryUnscaledOperands";
1377 def am_unscaled_fb8 : Operand<i64> {
1378 let ParserMatchClass = MemoryUnscaledFB8Operand;
1379 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1381 def am_unscaled_fb16 : Operand<i64> {
1382 let ParserMatchClass = MemoryUnscaledFB16Operand;
1383 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1385 def am_unscaled_fb32 : Operand<i64> {
1386 let ParserMatchClass = MemoryUnscaledFB32Operand;
1387 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1389 def am_unscaled_fb64 : Operand<i64> {
1390 let ParserMatchClass = MemoryUnscaledFB64Operand;
1391 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1393 def am_unscaled_fb128 : Operand<i64> {
1394 let ParserMatchClass = MemoryUnscaledFB128Operand;
1395 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1397 def : InstAlias<"ldr $Rt, $addr", (LDURXi GPR64:$Rt, am_unscaled_fb64:$addr)>;
1398 def : InstAlias<"ldr $Rt, $addr", (LDURWi GPR32:$Rt, am_unscaled_fb32:$addr)>;
1399 def : InstAlias<"ldr $Rt, $addr", (LDURBi FPR8:$Rt, am_unscaled_fb8:$addr)>;
1400 def : InstAlias<"ldr $Rt, $addr", (LDURHi FPR16:$Rt, am_unscaled_fb16:$addr)>;
1401 def : InstAlias<"ldr $Rt, $addr", (LDURSi FPR32:$Rt, am_unscaled_fb32:$addr)>;
1402 def : InstAlias<"ldr $Rt, $addr", (LDURDi FPR64:$Rt, am_unscaled_fb64:$addr)>;
1403 def : InstAlias<"ldr $Rt, $addr", (LDURQi FPR128:$Rt, am_unscaled_fb128:$addr)>;
1406 def : Pat<(i64 (zextloadi8 am_unscaled8:$addr)),
1407 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1408 def : Pat<(i64 (zextloadi16 am_unscaled16:$addr)),
1409 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1411 // load sign-extended half-word
1413 : LoadUnscaled<0b01, 0, 0b11, GPR32, am_unscaled16, "ldursh",
1414 [(set GPR32:$Rt, (sextloadi16 am_unscaled16:$addr))]>;
1416 : LoadUnscaled<0b01, 0, 0b10, GPR64, am_unscaled16, "ldursh",
1417 [(set GPR64:$Rt, (sextloadi16 am_unscaled16:$addr))]>;
1419 // load sign-extended byte
1421 : LoadUnscaled<0b00, 0, 0b11, GPR32, am_unscaled8, "ldursb",
1422 [(set GPR32:$Rt, (sextloadi8 am_unscaled8:$addr))]>;
1424 : LoadUnscaled<0b00, 0, 0b10, GPR64, am_unscaled8, "ldursb",
1425 [(set GPR64:$Rt, (sextloadi8 am_unscaled8:$addr))]>;
1427 // load sign-extended word
1429 : LoadUnscaled<0b10, 0, 0b10, GPR64, am_unscaled32, "ldursw",
1430 [(set GPR64:$Rt, (sextloadi32 am_unscaled32:$addr))]>;
1432 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1433 def : InstAlias<"ldrb $Rt, $addr", (LDURBBi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1434 def : InstAlias<"ldrh $Rt, $addr", (LDURHHi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1435 def : InstAlias<"ldrsb $Rt, $addr", (LDURSBWi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1436 def : InstAlias<"ldrsb $Rt, $addr", (LDURSBXi GPR64:$Rt, am_unscaled_fb8:$addr)>;
1437 def : InstAlias<"ldrsh $Rt, $addr", (LDURSHWi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1438 def : InstAlias<"ldrsh $Rt, $addr", (LDURSHXi GPR64:$Rt, am_unscaled_fb16:$addr)>;
1439 def : InstAlias<"ldrsw $Rt, $addr", (LDURSWi GPR64:$Rt, am_unscaled_fb32:$addr)>;
1442 def PRFUMi : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1443 [(ARM64Prefetch imm:$Rt, am_unscaled64:$addr)]>;
1446 // (unscaled immediate, unprivileged)
1447 def LDTRXi : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1448 def LDTRWi : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1450 def LDTRHi : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1451 def LDTRBi : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1453 // load sign-extended half-word
1454 def LDTRSHWi : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1455 def LDTRSHXi : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1457 // load sign-extended byte
1458 def LDTRSBWi : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1459 def LDTRSBXi : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1461 // load sign-extended word
1462 def LDTRSWi : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1465 // (immediate pre-indexed)
1466 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1467 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1468 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1469 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1470 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1471 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1472 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1474 // load sign-extended half-word
1475 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1476 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1478 // load sign-extended byte
1479 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1480 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1482 // load zero-extended byte
1483 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1484 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1486 // load sign-extended word
1487 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1489 // ISel pseudos and patterns. See expanded comment on LoadPreIdxPseudo.
1490 def LDRDpre_isel : LoadPreIdxPseudo<FPR64>;
1491 def LDRSpre_isel : LoadPreIdxPseudo<FPR32>;
1492 def LDRXpre_isel : LoadPreIdxPseudo<GPR64>;
1493 def LDRWpre_isel : LoadPreIdxPseudo<GPR32>;
1494 def LDRHHpre_isel : LoadPreIdxPseudo<GPR32>;
1495 def LDRBBpre_isel : LoadPreIdxPseudo<GPR32>;
1497 def LDRSWpre_isel : LoadPreIdxPseudo<GPR64>;
1498 def LDRSHWpre_isel : LoadPreIdxPseudo<GPR32>;
1499 def LDRSHXpre_isel : LoadPreIdxPseudo<GPR64>;
1500 def LDRSBWpre_isel : LoadPreIdxPseudo<GPR32>;
1501 def LDRSBXpre_isel : LoadPreIdxPseudo<GPR64>;
1504 // (immediate post-indexed)
1505 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1506 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1507 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1508 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1509 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1510 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1511 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1513 // load sign-extended half-word
1514 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1515 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1517 // load sign-extended byte
1518 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1519 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1521 // load zero-extended byte
1522 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1523 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1525 // load sign-extended word
1526 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1528 // ISel pseudos and patterns. See expanded comment on LoadPostIdxPseudo.
1529 def LDRDpost_isel : LoadPostIdxPseudo<FPR64>;
1530 def LDRSpost_isel : LoadPostIdxPseudo<FPR32>;
1531 def LDRXpost_isel : LoadPostIdxPseudo<GPR64>;
1532 def LDRWpost_isel : LoadPostIdxPseudo<GPR32>;
1533 def LDRHHpost_isel : LoadPostIdxPseudo<GPR32>;
1534 def LDRBBpost_isel : LoadPostIdxPseudo<GPR32>;
1536 def LDRSWpost_isel : LoadPostIdxPseudo<GPR64>;
1537 def LDRSHWpost_isel : LoadPostIdxPseudo<GPR32>;
1538 def LDRSHXpost_isel : LoadPostIdxPseudo<GPR64>;
1539 def LDRSBWpost_isel : LoadPostIdxPseudo<GPR32>;
1540 def LDRSBXpost_isel : LoadPostIdxPseudo<GPR64>;
1542 //===----------------------------------------------------------------------===//
1543 // Store instructions.
1544 //===----------------------------------------------------------------------===//
1546 // Pair (indexed, offset)
1547 // FIXME: Use dedicated range-checked addressing mode operand here.
1548 def STPWi : StorePairOffset<0b00, 0, GPR32, am_indexed32simm7, "stp">;
1549 def STPXi : StorePairOffset<0b10, 0, GPR64, am_indexed64simm7, "stp">;
1550 def STPSi : StorePairOffset<0b00, 1, FPR32, am_indexed32simm7, "stp">;
1551 def STPDi : StorePairOffset<0b01, 1, FPR64, am_indexed64simm7, "stp">;
1552 def STPQi : StorePairOffset<0b10, 1, FPR128, am_indexed128simm7, "stp">;
1554 // Pair (pre-indexed)
1555 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "stp">;
1556 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "stp">;
1557 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "stp">;
1558 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "stp">;
1559 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "stp">;
1561 // Pair (pre-indexed)
1562 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1563 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1564 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1565 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1566 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1568 // Pair (no allocate)
1569 def STNPWi : StorePairNoAlloc<0b00, 0, GPR32, am_indexed32simm7, "stnp">;
1570 def STNPXi : StorePairNoAlloc<0b10, 0, GPR64, am_indexed64simm7, "stnp">;
1571 def STNPSi : StorePairNoAlloc<0b00, 1, FPR32, am_indexed32simm7, "stnp">;
1572 def STNPDi : StorePairNoAlloc<0b01, 1, FPR64, am_indexed64simm7, "stnp">;
1573 def STNPQi : StorePairNoAlloc<0b10, 1, FPR128, am_indexed128simm7, "stnp">;
1576 // (Register offset)
1578 let AddedComplexity = 10 in {
1581 def STRHHro : Store16RO<0b01, 0, 0b00, GPR32, "strh",
1582 [(truncstorei16 GPR32:$Rt, ro_indexed16:$addr)]>;
1583 def STRBBro : Store8RO<0b00, 0, 0b00, GPR32, "strb",
1584 [(truncstorei8 GPR32:$Rt, ro_indexed8:$addr)]>;
1585 def STRWro : Store32RO<0b10, 0, 0b00, GPR32, "str",
1586 [(store GPR32:$Rt, ro_indexed32:$addr)]>;
1587 def STRXro : Store64RO<0b11, 0, 0b00, GPR64, "str",
1588 [(store GPR64:$Rt, ro_indexed64:$addr)]>;
1591 def : Pat<(truncstorei8 GPR64:$Rt, ro_indexed8:$addr),
1592 (STRBBro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed8:$addr)>;
1593 def : Pat<(truncstorei16 GPR64:$Rt, ro_indexed16:$addr),
1594 (STRHHro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed16:$addr)>;
1595 def : Pat<(truncstorei32 GPR64:$Rt, ro_indexed32:$addr),
1596 (STRWro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed32:$addr)>;
1600 def STRBro : Store8RO<0b00, 1, 0b00, FPR8, "str",
1601 [(store FPR8:$Rt, ro_indexed8:$addr)]>;
1602 def STRHro : Store16RO<0b01, 1, 0b00, FPR16, "str",
1603 [(store (f16 FPR16:$Rt), ro_indexed16:$addr)]>;
1604 def STRSro : Store32RO<0b10, 1, 0b00, FPR32, "str",
1605 [(store (f32 FPR32:$Rt), ro_indexed32:$addr)]>;
1606 def STRDro : Store64RO<0b11, 1, 0b00, FPR64, "str",
1607 [(store (f64 FPR64:$Rt), ro_indexed64:$addr)]>;
1608 def STRQro : Store128RO<0b00, 1, 0b10, FPR128, "str", []> {
1612 // Match all store 64 bits width whose type is compatible with FPR64
1613 def : Pat<(store (v2f32 FPR64:$Rn), ro_indexed64:$addr),
1614 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1615 def : Pat<(store (v1f64 FPR64:$Rn), ro_indexed64:$addr),
1616 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1617 def : Pat<(store (v8i8 FPR64:$Rn), ro_indexed64:$addr),
1618 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1619 def : Pat<(store (v4i16 FPR64:$Rn), ro_indexed64:$addr),
1620 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1621 def : Pat<(store (v2i32 FPR64:$Rn), ro_indexed64:$addr),
1622 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1623 def : Pat<(store (v1i64 FPR64:$Rn), ro_indexed64:$addr),
1624 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1626 // Match all store 128 bits width whose type is compatible with FPR128
1627 def : Pat<(store (v4f32 FPR128:$Rn), ro_indexed128:$addr),
1628 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1629 def : Pat<(store (v2f64 FPR128:$Rn), ro_indexed128:$addr),
1630 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1631 def : Pat<(store (v16i8 FPR128:$Rn), ro_indexed128:$addr),
1632 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1633 def : Pat<(store (v8i16 FPR128:$Rn), ro_indexed128:$addr),
1634 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1635 def : Pat<(store (v4i32 FPR128:$Rn), ro_indexed128:$addr),
1636 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1637 def : Pat<(store (v2i64 FPR128:$Rn), ro_indexed128:$addr),
1638 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1639 def : Pat<(store (f128 FPR128:$Rn), ro_indexed128:$addr),
1640 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1643 // (unsigned immediate)
1644 def STRXui : StoreUI<0b11, 0, 0b00, GPR64, am_indexed64, "str",
1645 [(store GPR64:$Rt, am_indexed64:$addr)]>;
1646 def STRWui : StoreUI<0b10, 0, 0b00, GPR32, am_indexed32, "str",
1647 [(store GPR32:$Rt, am_indexed32:$addr)]>;
1648 def STRBui : StoreUI<0b00, 1, 0b00, FPR8, am_indexed8, "str",
1649 [(store FPR8:$Rt, am_indexed8:$addr)]>;
1650 def STRHui : StoreUI<0b01, 1, 0b00, FPR16, am_indexed16, "str",
1651 [(store (f16 FPR16:$Rt), am_indexed16:$addr)]>;
1652 def STRSui : StoreUI<0b10, 1, 0b00, FPR32, am_indexed32, "str",
1653 [(store (f32 FPR32:$Rt), am_indexed32:$addr)]>;
1654 def STRDui : StoreUI<0b11, 1, 0b00, FPR64, am_indexed64, "str",
1655 [(store (f64 FPR64:$Rt), am_indexed64:$addr)]>;
1656 def STRQui : StoreUI<0b00, 1, 0b10, FPR128, am_indexed128, "str", []> {
1660 // Match all store 64 bits width whose type is compatible with FPR64
1661 def : Pat<(store (v2f32 FPR64:$Rn), am_indexed64:$addr),
1662 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1663 def : Pat<(store (v1f64 FPR64:$Rn), am_indexed64:$addr),
1664 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1665 def : Pat<(store (v8i8 FPR64:$Rn), am_indexed64:$addr),
1666 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1667 def : Pat<(store (v4i16 FPR64:$Rn), am_indexed64:$addr),
1668 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1669 def : Pat<(store (v2i32 FPR64:$Rn), am_indexed64:$addr),
1670 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1671 def : Pat<(store (v1i64 FPR64:$Rn), am_indexed64:$addr),
1672 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1674 // Match all store 128 bits width whose type is compatible with FPR128
1675 def : Pat<(store (v4f32 FPR128:$Rn), am_indexed128:$addr),
1676 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1677 def : Pat<(store (v2f64 FPR128:$Rn), am_indexed128:$addr),
1678 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1679 def : Pat<(store (v16i8 FPR128:$Rn), am_indexed128:$addr),
1680 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1681 def : Pat<(store (v8i16 FPR128:$Rn), am_indexed128:$addr),
1682 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1683 def : Pat<(store (v4i32 FPR128:$Rn), am_indexed128:$addr),
1684 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1685 def : Pat<(store (v2i64 FPR128:$Rn), am_indexed128:$addr),
1686 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1687 def : Pat<(store (f128 FPR128:$Rn), am_indexed128:$addr),
1688 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1690 def STRHHui : StoreUI<0b01, 0, 0b00, GPR32, am_indexed16, "strh",
1691 [(truncstorei16 GPR32:$Rt, am_indexed16:$addr)]>;
1692 def STRBBui : StoreUI<0b00, 0, 0b00, GPR32, am_indexed8, "strb",
1693 [(truncstorei8 GPR32:$Rt, am_indexed8:$addr)]>;
1696 def : Pat<(truncstorei32 GPR64:$Rt, am_indexed32:$addr),
1697 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed32:$addr)>;
1698 def : Pat<(truncstorei16 GPR64:$Rt, am_indexed16:$addr),
1699 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed16:$addr)>;
1700 def : Pat<(truncstorei8 GPR64:$Rt, am_indexed8:$addr),
1701 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed8:$addr)>;
1703 } // AddedComplexity = 10
1706 // (unscaled immediate)
1707 def STURXi : StoreUnscaled<0b11, 0, 0b00, GPR64, am_unscaled64, "stur",
1708 [(store GPR64:$Rt, am_unscaled64:$addr)]>;
1709 def STURWi : StoreUnscaled<0b10, 0, 0b00, GPR32, am_unscaled32, "stur",
1710 [(store GPR32:$Rt, am_unscaled32:$addr)]>;
1711 def STURBi : StoreUnscaled<0b00, 1, 0b00, FPR8, am_unscaled8, "stur",
1712 [(store FPR8:$Rt, am_unscaled8:$addr)]>;
1713 def STURHi : StoreUnscaled<0b01, 1, 0b00, FPR16, am_unscaled16, "stur",
1714 [(store (f16 FPR16:$Rt), am_unscaled16:$addr)]>;
1715 def STURSi : StoreUnscaled<0b10, 1, 0b00, FPR32, am_unscaled32, "stur",
1716 [(store (f32 FPR32:$Rt), am_unscaled32:$addr)]>;
1717 def STURDi : StoreUnscaled<0b11, 1, 0b00, FPR64, am_unscaled64, "stur",
1718 [(store (f64 FPR64:$Rt), am_unscaled64:$addr)]>;
1719 def STURQi : StoreUnscaled<0b00, 1, 0b10, FPR128, am_unscaled128, "stur",
1720 [(store (v2f64 FPR128:$Rt), am_unscaled128:$addr)]>;
1721 def STURHHi : StoreUnscaled<0b01, 0, 0b00, GPR32, am_unscaled16, "sturh",
1722 [(truncstorei16 GPR32:$Rt, am_unscaled16:$addr)]>;
1723 def STURBBi : StoreUnscaled<0b00, 0, 0b00, GPR32, am_unscaled8, "sturb",
1724 [(truncstorei8 GPR32:$Rt, am_unscaled8:$addr)]>;
1726 // Match all store 64 bits width whose type is compatible with FPR64
1727 def : Pat<(store (v2f32 FPR64:$Rn), am_unscaled64:$addr),
1728 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1729 def : Pat<(store (v1f64 FPR64:$Rn), am_unscaled64:$addr),
1730 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1731 def : Pat<(store (v8i8 FPR64:$Rn), am_unscaled64:$addr),
1732 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1733 def : Pat<(store (v4i16 FPR64:$Rn), am_unscaled64:$addr),
1734 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1735 def : Pat<(store (v2i32 FPR64:$Rn), am_unscaled64:$addr),
1736 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1737 def : Pat<(store (v1i64 FPR64:$Rn), am_unscaled64:$addr),
1738 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1740 // Match all store 128 bits width whose type is compatible with FPR128
1741 def : Pat<(store (v4f32 FPR128:$Rn), am_unscaled128:$addr),
1742 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1743 def : Pat<(store (v2f64 FPR128:$Rn), am_unscaled128:$addr),
1744 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1745 def : Pat<(store (v16i8 FPR128:$Rn), am_unscaled128:$addr),
1746 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1747 def : Pat<(store (v8i16 FPR128:$Rn), am_unscaled128:$addr),
1748 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1749 def : Pat<(store (v4i32 FPR128:$Rn), am_unscaled128:$addr),
1750 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1751 def : Pat<(store (v2i64 FPR128:$Rn), am_unscaled128:$addr),
1752 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1753 def : Pat<(store (f128 FPR128:$Rn), am_unscaled128:$addr),
1754 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1756 // unscaled i64 truncating stores
1757 def : Pat<(truncstorei32 GPR64:$Rt, am_unscaled32:$addr),
1758 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled32:$addr)>;
1759 def : Pat<(truncstorei16 GPR64:$Rt, am_unscaled16:$addr),
1760 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled16:$addr)>;
1761 def : Pat<(truncstorei8 GPR64:$Rt, am_unscaled8:$addr),
1762 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled8:$addr)>;
1765 // STR mnemonics fall back to STUR for negative or unaligned offsets.
1766 def : InstAlias<"str $Rt, $addr", (STURXi GPR64:$Rt, am_unscaled_fb64:$addr)>;
1767 def : InstAlias<"str $Rt, $addr", (STURWi GPR32:$Rt, am_unscaled_fb32:$addr)>;
1768 def : InstAlias<"str $Rt, $addr", (STURBi FPR8:$Rt, am_unscaled_fb8:$addr)>;
1769 def : InstAlias<"str $Rt, $addr", (STURHi FPR16:$Rt, am_unscaled_fb16:$addr)>;
1770 def : InstAlias<"str $Rt, $addr", (STURSi FPR32:$Rt, am_unscaled_fb32:$addr)>;
1771 def : InstAlias<"str $Rt, $addr", (STURDi FPR64:$Rt, am_unscaled_fb64:$addr)>;
1772 def : InstAlias<"str $Rt, $addr", (STURQi FPR128:$Rt, am_unscaled_fb128:$addr)>;
1774 def : InstAlias<"strb $Rt, $addr", (STURBBi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1775 def : InstAlias<"strh $Rt, $addr", (STURHHi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1778 // (unscaled immediate, unprivileged)
1779 def STTRWi : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
1780 def STTRXi : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
1782 def STTRHi : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
1783 def STTRBi : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
1786 // (immediate pre-indexed)
1787 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str">;
1788 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str">;
1789 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str">;
1790 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str">;
1791 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str">;
1792 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str">;
1793 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str">;
1795 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb">;
1796 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh">;
1798 // ISel pseudos and patterns. See expanded comment on StorePreIdxPseudo.
1799 defm STRDpre : StorePreIdxPseudo<FPR64, f64, pre_store>;
1800 defm STRSpre : StorePreIdxPseudo<FPR32, f32, pre_store>;
1801 defm STRXpre : StorePreIdxPseudo<GPR64, i64, pre_store>;
1802 defm STRWpre : StorePreIdxPseudo<GPR32, i32, pre_store>;
1803 defm STRHHpre : StorePreIdxPseudo<GPR32, i32, pre_truncsti16>;
1804 defm STRBBpre : StorePreIdxPseudo<GPR32, i32, pre_truncsti8>;
1806 def : Pat<(pre_truncsti32 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1807 (STRWpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1809 def : Pat<(pre_truncsti16 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1810 (STRHHpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1812 def : Pat<(pre_truncsti8 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1813 (STRBBpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1817 // (immediate post-indexed)
1818 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str">;
1819 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str">;
1820 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str">;
1821 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str">;
1822 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str">;
1823 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str">;
1824 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str">;
1826 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb">;
1827 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh">;
1829 // ISel pseudos and patterns. See expanded comment on StorePostIdxPseudo.
1830 defm STRDpost : StorePostIdxPseudo<FPR64, f64, post_store, STRDpost>;
1831 defm STRSpost : StorePostIdxPseudo<FPR32, f32, post_store, STRSpost>;
1832 defm STRXpost : StorePostIdxPseudo<GPR64, i64, post_store, STRXpost>;
1833 defm STRWpost : StorePostIdxPseudo<GPR32, i32, post_store, STRWpost>;
1834 defm STRHHpost : StorePostIdxPseudo<GPR32, i32, post_truncsti16, STRHHpost>;
1835 defm STRBBpost : StorePostIdxPseudo<GPR32, i32, post_truncsti8, STRBBpost>;
1837 def : Pat<(post_truncsti32 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1838 (STRWpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1840 def : Pat<(post_truncsti16 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1841 (STRHHpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1843 def : Pat<(post_truncsti8 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1844 (STRBBpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1848 //===----------------------------------------------------------------------===//
1849 // Load/store exclusive instructions.
1850 //===----------------------------------------------------------------------===//
1852 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
1853 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
1854 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
1855 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
1857 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
1858 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
1859 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
1860 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
1862 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
1863 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
1864 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
1865 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
1867 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
1868 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
1869 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
1870 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
1872 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
1873 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
1874 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
1875 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
1877 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
1878 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
1879 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
1880 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
1882 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
1883 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
1885 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
1886 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
1888 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
1889 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
1891 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
1892 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
1894 //===----------------------------------------------------------------------===//
1895 // Scaled floating point to integer conversion instructions.
1896 //===----------------------------------------------------------------------===//
1898 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_arm64_neon_fcvtas>;
1899 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_arm64_neon_fcvtau>;
1900 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_arm64_neon_fcvtms>;
1901 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_arm64_neon_fcvtmu>;
1902 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_arm64_neon_fcvtns>;
1903 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_arm64_neon_fcvtnu>;
1904 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_arm64_neon_fcvtps>;
1905 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_arm64_neon_fcvtpu>;
1906 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
1907 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
1908 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
1909 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
1910 let isCodeGenOnly = 1 in {
1911 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
1912 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
1913 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
1914 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
1917 //===----------------------------------------------------------------------===//
1918 // Scaled integer to floating point conversion instructions.
1919 //===----------------------------------------------------------------------===//
1921 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
1922 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
1924 //===----------------------------------------------------------------------===//
1925 // Unscaled integer to floating point conversion instruction.
1926 //===----------------------------------------------------------------------===//
1928 defm FMOV : UnscaledConversion<"fmov">;
1930 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
1931 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
1933 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1934 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1935 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1936 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1937 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1938 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1939 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
1940 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1941 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
1942 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1943 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
1945 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
1946 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1947 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
1948 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1949 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
1950 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1951 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
1952 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1953 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
1954 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1955 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
1956 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1958 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
1959 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
1960 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
1961 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
1962 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
1963 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1964 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
1965 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
1967 //===----------------------------------------------------------------------===//
1968 // Floating point conversion instruction.
1969 //===----------------------------------------------------------------------===//
1971 defm FCVT : FPConversion<"fcvt">;
1973 def : Pat<(f32_to_f16 FPR32:$Rn),
1974 (i32 (COPY_TO_REGCLASS
1975 (f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
1978 def FCVTSHpseudo : Pseudo<(outs FPR32:$Rd), (ins FPR32:$Rn),
1979 [(set (f32 FPR32:$Rd), (f16_to_f32 i32:$Rn))]>;
1981 //===----------------------------------------------------------------------===//
1982 // Floating point single operand instructions.
1983 //===----------------------------------------------------------------------===//
1985 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
1986 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
1987 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
1988 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
1989 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
1990 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
1991 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_arm64_neon_frintn>;
1992 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
1994 def : Pat<(v1f64 (int_arm64_neon_frintn (v1f64 FPR64:$Rn))),
1995 (FRINTNDr FPR64:$Rn)>;
1997 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
1998 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
1999 // <rdar://problem/13715968>
2000 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2001 let hasSideEffects = 1 in {
2002 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2005 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2007 let SchedRW = [WriteFDiv] in {
2008 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2011 //===----------------------------------------------------------------------===//
2012 // Floating point two operand instructions.
2013 //===----------------------------------------------------------------------===//
2015 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2016 let SchedRW = [WriteFDiv] in {
2017 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2019 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_arm64_neon_fmaxnm>;
2020 defm FMAX : TwoOperandFPData<0b0100, "fmax", ARM64fmax>;
2021 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_arm64_neon_fminnm>;
2022 defm FMIN : TwoOperandFPData<0b0101, "fmin", ARM64fmin>;
2023 let SchedRW = [WriteFMul] in {
2024 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2025 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2027 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2029 def : Pat<(v1f64 (ARM64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2030 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2031 def : Pat<(v1f64 (ARM64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2032 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2033 def : Pat<(v1f64 (int_arm64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2034 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2035 def : Pat<(v1f64 (int_arm64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2036 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2038 //===----------------------------------------------------------------------===//
2039 // Floating point three operand instructions.
2040 //===----------------------------------------------------------------------===//
2042 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2043 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2044 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2045 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2046 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2047 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2048 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2050 // The following def pats catch the case where the LHS of an FMA is negated.
2051 // The TriOpFrag above catches the case where the middle operand is negated.
2053 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2054 // the NEON variant.
2055 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2056 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2058 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2059 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2061 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2063 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2064 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2066 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2067 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2069 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2070 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2072 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2073 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2075 //===----------------------------------------------------------------------===//
2076 // Floating point comparison instructions.
2077 //===----------------------------------------------------------------------===//
2079 defm FCMPE : FPComparison<1, "fcmpe">;
2080 defm FCMP : FPComparison<0, "fcmp", ARM64fcmp>;
2082 //===----------------------------------------------------------------------===//
2083 // Floating point conditional comparison instructions.
2084 //===----------------------------------------------------------------------===//
2086 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2087 defm FCCMP : FPCondComparison<0, "fccmp">;
2089 //===----------------------------------------------------------------------===//
2090 // Floating point conditional select instruction.
2091 //===----------------------------------------------------------------------===//
2093 defm FCSEL : FPCondSelect<"fcsel">;
2095 // CSEL instructions providing f128 types need to be handled by a
2096 // pseudo-instruction since the eventual code will need to introduce basic
2097 // blocks and control flow.
2098 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2099 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2100 [(set (f128 FPR128:$Rd),
2101 (ARM64csel FPR128:$Rn, FPR128:$Rm,
2102 (i32 imm:$cond), CPSR))]> {
2104 let usesCustomInserter = 1;
2108 //===----------------------------------------------------------------------===//
2109 // Floating point immediate move.
2110 //===----------------------------------------------------------------------===//
2112 let isReMaterializable = 1 in {
2113 defm FMOV : FPMoveImmediate<"fmov">;
2116 //===----------------------------------------------------------------------===//
2117 // Advanced SIMD two vector instructions.
2118 //===----------------------------------------------------------------------===//
2120 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_arm64_neon_abs>;
2121 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_arm64_neon_cls>;
2122 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2123 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", ARM64cmeqz>;
2124 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", ARM64cmgez>;
2125 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", ARM64cmgtz>;
2126 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", ARM64cmlez>;
2127 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", ARM64cmltz>;
2128 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2129 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2131 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2132 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2133 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2134 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2135 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2136 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_arm64_neon_fcvtas>;
2137 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_arm64_neon_fcvtau>;
2138 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2139 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2140 (FCVTLv4i16 V64:$Rn)>;
2141 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2143 (FCVTLv8i16 V128:$Rn)>;
2144 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2145 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2147 (FCVTLv4i32 V128:$Rn)>;
2149 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_arm64_neon_fcvtms>;
2150 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_arm64_neon_fcvtmu>;
2151 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_arm64_neon_fcvtns>;
2152 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_arm64_neon_fcvtnu>;
2153 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2154 def : Pat<(v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2155 (FCVTNv4i16 V128:$Rn)>;
2156 def : Pat<(concat_vectors V64:$Rd,
2157 (v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2158 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2159 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2160 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2161 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2162 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_arm64_neon_fcvtps>;
2163 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_arm64_neon_fcvtpu>;
2164 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2165 int_arm64_neon_fcvtxn>;
2166 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2167 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2168 let isCodeGenOnly = 1 in {
2169 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2170 int_arm64_neon_fcvtzs>;
2171 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2172 int_arm64_neon_fcvtzu>;
2174 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2175 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_arm64_neon_frecpe>;
2176 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2177 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2178 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2179 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_arm64_neon_frintn>;
2180 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2181 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2182 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2183 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_arm64_neon_frsqrte>;
2184 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2185 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2186 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2187 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2188 // Aliases for MVN -> NOT.
2189 def : InstAlias<"mvn.8b $Vd, $Vn", (NOTv8i8 V64:$Vd, V64:$Vn)>;
2190 def : InstAlias<"mvn.16b $Vd, $Vn", (NOTv16i8 V128:$Vd, V128:$Vn)>;
2191 def : InstAlias<"mvn $Vd.8b, $Vn.8b", (NOTv8i8 V64:$Vd, V64:$Vn)>;
2192 def : InstAlias<"mvn $Vd.16b, $Vn.16b", (NOTv16i8 V128:$Vd, V128:$Vn)>;
2194 def : Pat<(ARM64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2195 def : Pat<(ARM64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2196 def : Pat<(ARM64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2197 def : Pat<(ARM64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2198 def : Pat<(ARM64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2199 def : Pat<(ARM64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2200 def : Pat<(ARM64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2202 def : Pat<(ARM64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2203 def : Pat<(ARM64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2204 def : Pat<(ARM64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2205 def : Pat<(ARM64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2206 def : Pat<(ARM64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2207 def : Pat<(ARM64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2208 def : Pat<(ARM64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2209 def : Pat<(ARM64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2211 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2212 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2213 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2214 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2215 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2217 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_arm64_neon_rbit>;
2218 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", ARM64rev16>;
2219 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", ARM64rev32>;
2220 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", ARM64rev64>;
2221 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2222 BinOpFrag<(add node:$LHS, (int_arm64_neon_saddlp node:$RHS))> >;
2223 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_arm64_neon_saddlp>;
2224 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2225 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2226 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2227 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2228 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_arm64_neon_sqxtn>;
2229 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_arm64_neon_sqxtun>;
2230 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_arm64_neon_suqadd>;
2231 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2232 BinOpFrag<(add node:$LHS, (int_arm64_neon_uaddlp node:$RHS))> >;
2233 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2234 int_arm64_neon_uaddlp>;
2235 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2236 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_arm64_neon_uqxtn>;
2237 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_arm64_neon_urecpe>;
2238 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_arm64_neon_ursqrte>;
2239 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_arm64_neon_usqadd>;
2240 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2242 def : Pat<(v2f32 (ARM64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2243 def : Pat<(v4f32 (ARM64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2245 // Patterns for vector long shift (by element width). These need to match all
2246 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2248 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2249 def : Pat<(ARM64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2250 (SHLLv8i8 V64:$Rn)>;
2251 def : Pat<(ARM64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2252 (SHLLv16i8 V128:$Rn)>;
2253 def : Pat<(ARM64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2254 (SHLLv4i16 V64:$Rn)>;
2255 def : Pat<(ARM64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2256 (SHLLv8i16 V128:$Rn)>;
2257 def : Pat<(ARM64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2258 (SHLLv2i32 V64:$Rn)>;
2259 def : Pat<(ARM64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2260 (SHLLv4i32 V128:$Rn)>;
2263 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2264 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2265 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2267 //===----------------------------------------------------------------------===//
2268 // Advanced SIMD three vector instructions.
2269 //===----------------------------------------------------------------------===//
2271 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2272 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_arm64_neon_addp>;
2273 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", ARM64cmeq>;
2274 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", ARM64cmge>;
2275 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", ARM64cmgt>;
2276 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", ARM64cmhi>;
2277 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", ARM64cmhs>;
2278 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", ARM64cmtst>;
2279 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_arm64_neon_fabd>;
2280 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_arm64_neon_facge>;
2281 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_arm64_neon_facgt>;
2282 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_arm64_neon_addp>;
2283 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2284 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2285 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2286 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2287 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2288 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_arm64_neon_fmaxnmp>;
2289 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_arm64_neon_fmaxnm>;
2290 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_arm64_neon_fmaxp>;
2291 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", ARM64fmax>;
2292 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_arm64_neon_fminnmp>;
2293 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_arm64_neon_fminnm>;
2294 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_arm64_neon_fminp>;
2295 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", ARM64fmin>;
2297 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2298 // instruction expects the addend first, while the fma intrinsic puts it last.
2299 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2300 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2301 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2302 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2304 // The following def pats catch the case where the LHS of an FMA is negated.
2305 // The TriOpFrag above catches the case where the middle operand is negated.
2306 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2307 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2309 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2310 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2312 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2313 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2315 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_arm64_neon_fmulx>;
2316 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2317 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_arm64_neon_frecps>;
2318 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_arm64_neon_frsqrts>;
2319 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2320 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2321 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2322 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2323 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2324 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2325 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_arm64_neon_pmul>;
2326 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2327 TriOpFrag<(add node:$LHS, (int_arm64_neon_sabd node:$MHS, node:$RHS))> >;
2328 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_arm64_neon_sabd>;
2329 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_arm64_neon_shadd>;
2330 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_arm64_neon_shsub>;
2331 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_arm64_neon_smaxp>;
2332 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_arm64_neon_smax>;
2333 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_arm64_neon_sminp>;
2334 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_arm64_neon_smin>;
2335 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_arm64_neon_sqadd>;
2336 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_arm64_neon_sqdmulh>;
2337 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_arm64_neon_sqrdmulh>;
2338 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_arm64_neon_sqrshl>;
2339 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_arm64_neon_sqshl>;
2340 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_arm64_neon_sqsub>;
2341 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_arm64_neon_srhadd>;
2342 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_arm64_neon_srshl>;
2343 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_arm64_neon_sshl>;
2344 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2345 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2346 TriOpFrag<(add node:$LHS, (int_arm64_neon_uabd node:$MHS, node:$RHS))> >;
2347 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_arm64_neon_uabd>;
2348 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_arm64_neon_uhadd>;
2349 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_arm64_neon_uhsub>;
2350 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_arm64_neon_umaxp>;
2351 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_arm64_neon_umax>;
2352 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_arm64_neon_uminp>;
2353 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_arm64_neon_umin>;
2354 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_arm64_neon_uqadd>;
2355 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_arm64_neon_uqrshl>;
2356 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_arm64_neon_uqshl>;
2357 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_arm64_neon_uqsub>;
2358 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_arm64_neon_urhadd>;
2359 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_arm64_neon_urshl>;
2360 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_arm64_neon_ushl>;
2362 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2363 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2364 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2365 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2366 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", ARM64bit>;
2367 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2368 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2369 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2370 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2371 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2372 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2374 // FIXME: the .16b and .8b variantes should be emitted by the
2375 // AsmWriter. TableGen's AsmWriter-generator doesn't deal with variant syntaxes
2376 // in aliases yet though.
2377 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2378 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2379 def : InstAlias<"{mov\t$dst.8h, $src.8h|mov.8h\t$dst, $src}",
2380 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2381 def : InstAlias<"{mov\t$dst.4s, $src.4s|mov.4s\t$dst, $src}",
2382 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2383 def : InstAlias<"{mov\t$dst.2d, $src.2d|mov.2d\t$dst, $src}",
2384 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2386 def : InstAlias<"{mov\t$dst.8b, $src.8b|mov.8b\t$dst, $src}",
2387 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2388 def : InstAlias<"{mov\t$dst.4h, $src.4h|mov.4h\t$dst, $src}",
2389 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2390 def : InstAlias<"{mov\t$dst.2s, $src.2s|mov.2s\t$dst, $src}",
2391 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2392 def : InstAlias<"{mov\t$dst.1d, $src.1d|mov.1d\t$dst, $src}",
2393 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2395 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2396 "|cmls.8b\t$dst, $src1, $src2}",
2397 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2398 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2399 "|cmls.16b\t$dst, $src1, $src2}",
2400 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2401 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2402 "|cmls.4h\t$dst, $src1, $src2}",
2403 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2404 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2405 "|cmls.8h\t$dst, $src1, $src2}",
2406 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2407 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2408 "|cmls.2s\t$dst, $src1, $src2}",
2409 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2410 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2411 "|cmls.4s\t$dst, $src1, $src2}",
2412 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2413 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2414 "|cmls.2d\t$dst, $src1, $src2}",
2415 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2417 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2418 "|cmlo.8b\t$dst, $src1, $src2}",
2419 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2420 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2421 "|cmlo.16b\t$dst, $src1, $src2}",
2422 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2423 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2424 "|cmlo.4h\t$dst, $src1, $src2}",
2425 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2426 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2427 "|cmlo.8h\t$dst, $src1, $src2}",
2428 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2429 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2430 "|cmlo.2s\t$dst, $src1, $src2}",
2431 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2432 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2433 "|cmlo.4s\t$dst, $src1, $src2}",
2434 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2435 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2436 "|cmlo.2d\t$dst, $src1, $src2}",
2437 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2439 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2440 "|cmle.8b\t$dst, $src1, $src2}",
2441 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2442 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2443 "|cmle.16b\t$dst, $src1, $src2}",
2444 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2445 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2446 "|cmle.4h\t$dst, $src1, $src2}",
2447 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2448 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2449 "|cmle.8h\t$dst, $src1, $src2}",
2450 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2451 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2452 "|cmle.2s\t$dst, $src1, $src2}",
2453 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2454 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2455 "|cmle.4s\t$dst, $src1, $src2}",
2456 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2457 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2458 "|cmle.2d\t$dst, $src1, $src2}",
2459 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2461 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2462 "|cmlt.8b\t$dst, $src1, $src2}",
2463 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2464 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2465 "|cmlt.16b\t$dst, $src1, $src2}",
2466 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2467 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2468 "|cmlt.4h\t$dst, $src1, $src2}",
2469 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2470 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2471 "|cmlt.8h\t$dst, $src1, $src2}",
2472 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2473 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2474 "|cmlt.2s\t$dst, $src1, $src2}",
2475 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2476 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2477 "|cmlt.4s\t$dst, $src1, $src2}",
2478 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2479 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2480 "|cmlt.2d\t$dst, $src1, $src2}",
2481 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2483 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2484 "|fcmle.2s\t$dst, $src1, $src2}",
2485 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2486 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2487 "|fcmle.4s\t$dst, $src1, $src2}",
2488 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2489 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2490 "|fcmle.2d\t$dst, $src1, $src2}",
2491 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2493 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2494 "|fcmlt.2s\t$dst, $src1, $src2}",
2495 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2496 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2497 "|fcmlt.4s\t$dst, $src1, $src2}",
2498 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2499 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2500 "|fcmlt.2d\t$dst, $src1, $src2}",
2501 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2503 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2504 "|facle.2s\t$dst, $src1, $src2}",
2505 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2506 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2507 "|facle.4s\t$dst, $src1, $src2}",
2508 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2509 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2510 "|facle.2d\t$dst, $src1, $src2}",
2511 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2513 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2514 "|faclt.2s\t$dst, $src1, $src2}",
2515 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2516 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2517 "|faclt.4s\t$dst, $src1, $src2}",
2518 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2519 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2520 "|faclt.2d\t$dst, $src1, $src2}",
2521 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2523 //===----------------------------------------------------------------------===//
2524 // Advanced SIMD three scalar instructions.
2525 //===----------------------------------------------------------------------===//
2527 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2528 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", ARM64cmeq>;
2529 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", ARM64cmge>;
2530 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", ARM64cmgt>;
2531 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", ARM64cmhi>;
2532 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", ARM64cmhs>;
2533 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", ARM64cmtst>;
2534 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_arm64_sisd_fabd>;
2535 def : Pat<(v1f64 (int_arm64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2536 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2537 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2538 int_arm64_neon_facge>;
2539 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2540 int_arm64_neon_facgt>;
2541 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2542 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2543 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2544 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_arm64_neon_fmulx>;
2545 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_arm64_neon_frecps>;
2546 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_arm64_neon_frsqrts>;
2547 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_arm64_neon_sqadd>;
2548 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_arm64_neon_sqdmulh>;
2549 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_arm64_neon_sqrdmulh>;
2550 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_arm64_neon_sqrshl>;
2551 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_arm64_neon_sqshl>;
2552 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_arm64_neon_sqsub>;
2553 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_arm64_neon_srshl>;
2554 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_arm64_neon_sshl>;
2555 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2556 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_arm64_neon_uqadd>;
2557 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_arm64_neon_uqrshl>;
2558 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_arm64_neon_uqshl>;
2559 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_arm64_neon_uqsub>;
2560 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_arm64_neon_urshl>;
2561 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_arm64_neon_ushl>;
2563 def : InstAlias<"cmls $dst, $src1, $src2",
2564 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2565 def : InstAlias<"cmle $dst, $src1, $src2",
2566 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2567 def : InstAlias<"cmlo $dst, $src1, $src2",
2568 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2569 def : InstAlias<"cmlt $dst, $src1, $src2",
2570 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2571 def : InstAlias<"fcmle $dst, $src1, $src2",
2572 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2573 def : InstAlias<"fcmle $dst, $src1, $src2",
2574 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2575 def : InstAlias<"fcmlt $dst, $src1, $src2",
2576 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2577 def : InstAlias<"fcmlt $dst, $src1, $src2",
2578 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2579 def : InstAlias<"facle $dst, $src1, $src2",
2580 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2581 def : InstAlias<"facle $dst, $src1, $src2",
2582 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2583 def : InstAlias<"faclt $dst, $src1, $src2",
2584 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2585 def : InstAlias<"faclt $dst, $src1, $src2",
2586 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2588 //===----------------------------------------------------------------------===//
2589 // Advanced SIMD three scalar instructions (mixed operands).
2590 //===----------------------------------------------------------------------===//
2591 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2592 int_arm64_neon_sqdmulls_scalar>;
2593 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2594 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
2596 def : Pat<(i64 (int_arm64_neon_sqadd (i64 FPR64:$Rd),
2597 (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2598 (i32 FPR32:$Rm))))),
2599 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2600 def : Pat<(i64 (int_arm64_neon_sqsub (i64 FPR64:$Rd),
2601 (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2602 (i32 FPR32:$Rm))))),
2603 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2605 //===----------------------------------------------------------------------===//
2606 // Advanced SIMD two scalar instructions.
2607 //===----------------------------------------------------------------------===//
2609 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_arm64_neon_abs>;
2610 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", ARM64cmeqz>;
2611 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", ARM64cmgez>;
2612 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", ARM64cmgtz>;
2613 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", ARM64cmlez>;
2614 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", ARM64cmltz>;
2615 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2616 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2617 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2618 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2619 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2620 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
2621 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
2622 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
2623 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
2624 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
2625 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
2626 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
2627 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
2628 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
2629 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
2630 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
2631 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
2632 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
2633 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
2634 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
2635 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2636 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", ARM64sitof>;
2637 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2638 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2639 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_arm64_neon_scalar_sqxtn>;
2640 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_arm64_neon_scalar_sqxtun>;
2641 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
2642 int_arm64_neon_suqadd>;
2643 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", ARM64uitof>;
2644 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_arm64_neon_scalar_uqxtn>;
2645 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
2646 int_arm64_neon_usqadd>;
2648 def : Pat<(v1i64 (int_arm64_neon_fcvtas (v1f64 FPR64:$Rn))),
2649 (FCVTASv1i64 FPR64:$Rn)>;
2650 def : Pat<(v1i64 (int_arm64_neon_fcvtau (v1f64 FPR64:$Rn))),
2651 (FCVTAUv1i64 FPR64:$Rn)>;
2652 def : Pat<(v1i64 (int_arm64_neon_fcvtms (v1f64 FPR64:$Rn))),
2653 (FCVTMSv1i64 FPR64:$Rn)>;
2654 def : Pat<(v1i64 (int_arm64_neon_fcvtmu (v1f64 FPR64:$Rn))),
2655 (FCVTMUv1i64 FPR64:$Rn)>;
2656 def : Pat<(v1i64 (int_arm64_neon_fcvtns (v1f64 FPR64:$Rn))),
2657 (FCVTNSv1i64 FPR64:$Rn)>;
2658 def : Pat<(v1i64 (int_arm64_neon_fcvtnu (v1f64 FPR64:$Rn))),
2659 (FCVTNUv1i64 FPR64:$Rn)>;
2660 def : Pat<(v1i64 (int_arm64_neon_fcvtps (v1f64 FPR64:$Rn))),
2661 (FCVTPSv1i64 FPR64:$Rn)>;
2662 def : Pat<(v1i64 (int_arm64_neon_fcvtpu (v1f64 FPR64:$Rn))),
2663 (FCVTPUv1i64 FPR64:$Rn)>;
2665 def : Pat<(f32 (int_arm64_neon_frecpe (f32 FPR32:$Rn))),
2666 (FRECPEv1i32 FPR32:$Rn)>;
2667 def : Pat<(f64 (int_arm64_neon_frecpe (f64 FPR64:$Rn))),
2668 (FRECPEv1i64 FPR64:$Rn)>;
2669 def : Pat<(v1f64 (int_arm64_neon_frecpe (v1f64 FPR64:$Rn))),
2670 (FRECPEv1i64 FPR64:$Rn)>;
2672 def : Pat<(f32 (int_arm64_neon_frecpx (f32 FPR32:$Rn))),
2673 (FRECPXv1i32 FPR32:$Rn)>;
2674 def : Pat<(f64 (int_arm64_neon_frecpx (f64 FPR64:$Rn))),
2675 (FRECPXv1i64 FPR64:$Rn)>;
2677 def : Pat<(f32 (int_arm64_neon_frsqrte (f32 FPR32:$Rn))),
2678 (FRSQRTEv1i32 FPR32:$Rn)>;
2679 def : Pat<(f64 (int_arm64_neon_frsqrte (f64 FPR64:$Rn))),
2680 (FRSQRTEv1i64 FPR64:$Rn)>;
2681 def : Pat<(v1f64 (int_arm64_neon_frsqrte (v1f64 FPR64:$Rn))),
2682 (FRSQRTEv1i64 FPR64:$Rn)>;
2684 // If an integer is about to be converted to a floating point value,
2685 // just load it on the floating point unit.
2686 // Here are the patterns for 8 and 16-bits to float.
2688 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 ro_indexed8:$addr)))),
2689 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2690 (LDRBro ro_indexed8:$addr), bsub))>;
2691 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 am_indexed8:$addr)))),
2692 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2693 (LDRBui am_indexed8:$addr), bsub))>;
2694 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 am_unscaled8:$addr)))),
2695 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2696 (LDURBi am_unscaled8:$addr), bsub))>;
2697 // 16-bits -> float.
2698 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 ro_indexed16:$addr)))),
2699 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2700 (LDRHro ro_indexed16:$addr), hsub))>;
2701 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 am_indexed16:$addr)))),
2702 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2703 (LDRHui am_indexed16:$addr), hsub))>;
2704 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 am_unscaled16:$addr)))),
2705 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2706 (LDURHi am_unscaled16:$addr), hsub))>;
2707 // 32-bits are handled in target specific dag combine:
2708 // performIntToFpCombine.
2709 // 64-bits integer to 32-bits floating point, not possible with
2710 // UCVTF on floating point registers (both source and destination
2711 // must have the same size).
2713 // Here are the patterns for 8, 16, 32, and 64-bits to double.
2714 // 8-bits -> double.
2715 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 ro_indexed8:$addr)))),
2716 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2717 (LDRBro ro_indexed8:$addr), bsub))>;
2718 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 am_indexed8:$addr)))),
2719 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2720 (LDRBui am_indexed8:$addr), bsub))>;
2721 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 am_unscaled8:$addr)))),
2722 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2723 (LDURBi am_unscaled8:$addr), bsub))>;
2724 // 16-bits -> double.
2725 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 ro_indexed16:$addr)))),
2726 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2727 (LDRHro ro_indexed16:$addr), hsub))>;
2728 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 am_indexed16:$addr)))),
2729 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2730 (LDRHui am_indexed16:$addr), hsub))>;
2731 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 am_unscaled16:$addr)))),
2732 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2733 (LDURHi am_unscaled16:$addr), hsub))>;
2734 // 32-bits -> double.
2735 def : Pat <(f64 (uint_to_fp (i32 (load ro_indexed32:$addr)))),
2736 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2737 (LDRSro ro_indexed32:$addr), ssub))>;
2738 def : Pat <(f64 (uint_to_fp (i32 (load am_indexed32:$addr)))),
2739 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2740 (LDRSui am_indexed32:$addr), ssub))>;
2741 def : Pat <(f64 (uint_to_fp (i32 (load am_unscaled32:$addr)))),
2742 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2743 (LDURSi am_unscaled32:$addr), ssub))>;
2744 // 64-bits -> double are handled in target specific dag combine:
2745 // performIntToFpCombine.
2747 //===----------------------------------------------------------------------===//
2748 // Advanced SIMD three different-sized vector instructions.
2749 //===----------------------------------------------------------------------===//
2751 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_arm64_neon_addhn>;
2752 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_arm64_neon_subhn>;
2753 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_arm64_neon_raddhn>;
2754 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_arm64_neon_rsubhn>;
2755 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_arm64_neon_pmull>;
2756 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
2757 int_arm64_neon_sabd>;
2758 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
2759 int_arm64_neon_sabd>;
2760 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
2761 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
2762 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
2763 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
2764 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
2765 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
2766 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
2767 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
2768 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_arm64_neon_smull>;
2769 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
2770 int_arm64_neon_sqadd>;
2771 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
2772 int_arm64_neon_sqsub>;
2773 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
2774 int_arm64_neon_sqdmull>;
2775 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
2776 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
2777 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
2778 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
2779 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
2780 int_arm64_neon_uabd>;
2781 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
2782 int_arm64_neon_uabd>;
2783 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
2784 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
2785 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
2786 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
2787 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
2788 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
2789 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
2790 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
2791 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_arm64_neon_umull>;
2792 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
2793 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
2794 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
2795 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
2797 // Patterns for 64-bit pmull
2798 def : Pat<(int_arm64_neon_pmull64 V64:$Rn, V64:$Rm),
2799 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
2800 def : Pat<(int_arm64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
2801 (vector_extract (v2i64 V128:$Rm), (i64 1))),
2802 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
2804 // CodeGen patterns for addhn and subhn instructions, which can actually be
2805 // written in LLVM IR without too much difficulty.
2808 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
2809 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
2810 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2812 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
2813 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2815 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
2816 def : Pat<(concat_vectors (v8i8 V64:$Rd),
2817 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2819 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2820 V128:$Rn, V128:$Rm)>;
2821 def : Pat<(concat_vectors (v4i16 V64:$Rd),
2822 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2824 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2825 V128:$Rn, V128:$Rm)>;
2826 def : Pat<(concat_vectors (v2i32 V64:$Rd),
2827 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2829 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2830 V128:$Rn, V128:$Rm)>;
2833 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
2834 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
2835 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2837 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
2838 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2840 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
2841 def : Pat<(concat_vectors (v8i8 V64:$Rd),
2842 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2844 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2845 V128:$Rn, V128:$Rm)>;
2846 def : Pat<(concat_vectors (v4i16 V64:$Rd),
2847 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2849 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2850 V128:$Rn, V128:$Rm)>;
2851 def : Pat<(concat_vectors (v2i32 V64:$Rd),
2852 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2854 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2855 V128:$Rn, V128:$Rm)>;
2857 //----------------------------------------------------------------------------
2858 // AdvSIMD bitwise extract from vector instruction.
2859 //----------------------------------------------------------------------------
2861 defm EXT : SIMDBitwiseExtract<"ext">;
2863 def : Pat<(v4i16 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2864 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2865 def : Pat<(v8i16 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2866 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2867 def : Pat<(v2i32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2868 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2869 def : Pat<(v2f32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2870 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2871 def : Pat<(v4i32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2872 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2873 def : Pat<(v4f32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2874 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2875 def : Pat<(v2i64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2876 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2877 def : Pat<(v2f64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2878 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2880 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
2882 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
2883 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2884 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
2885 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2886 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
2887 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2888 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
2889 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2890 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
2891 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2892 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
2893 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2896 //----------------------------------------------------------------------------
2897 // AdvSIMD zip vector
2898 //----------------------------------------------------------------------------
2900 defm TRN1 : SIMDZipVector<0b010, "trn1", ARM64trn1>;
2901 defm TRN2 : SIMDZipVector<0b110, "trn2", ARM64trn2>;
2902 defm UZP1 : SIMDZipVector<0b001, "uzp1", ARM64uzp1>;
2903 defm UZP2 : SIMDZipVector<0b101, "uzp2", ARM64uzp2>;
2904 defm ZIP1 : SIMDZipVector<0b011, "zip1", ARM64zip1>;
2905 defm ZIP2 : SIMDZipVector<0b111, "zip2", ARM64zip2>;
2907 //----------------------------------------------------------------------------
2908 // AdvSIMD TBL/TBX instructions
2909 //----------------------------------------------------------------------------
2911 defm TBL : SIMDTableLookup< 0, "tbl">;
2912 defm TBX : SIMDTableLookupTied<1, "tbx">;
2914 def : Pat<(v8i8 (int_arm64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
2915 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
2916 def : Pat<(v16i8 (int_arm64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
2917 (TBLv16i8One V128:$Ri, V128:$Rn)>;
2919 def : Pat<(v8i8 (int_arm64_neon_tbx1 (v8i8 V64:$Rd),
2920 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
2921 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
2922 def : Pat<(v16i8 (int_arm64_neon_tbx1 (v16i8 V128:$Rd),
2923 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
2924 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
2927 //----------------------------------------------------------------------------
2928 // AdvSIMD scalar CPY instruction
2929 //----------------------------------------------------------------------------
2931 defm CPY : SIMDScalarCPY<"cpy">;
2933 //----------------------------------------------------------------------------
2934 // AdvSIMD scalar pairwise instructions
2935 //----------------------------------------------------------------------------
2937 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
2938 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
2939 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
2940 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
2941 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
2942 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
2943 def : Pat<(i64 (int_arm64_neon_saddv (v2i64 V128:$Rn))),
2944 (ADDPv2i64p V128:$Rn)>;
2945 def : Pat<(i64 (int_arm64_neon_uaddv (v2i64 V128:$Rn))),
2946 (ADDPv2i64p V128:$Rn)>;
2947 def : Pat<(f32 (int_arm64_neon_faddv (v2f32 V64:$Rn))),
2948 (FADDPv2i32p V64:$Rn)>;
2949 def : Pat<(f32 (int_arm64_neon_faddv (v4f32 V128:$Rn))),
2950 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
2951 def : Pat<(f64 (int_arm64_neon_faddv (v2f64 V128:$Rn))),
2952 (FADDPv2i64p V128:$Rn)>;
2953 def : Pat<(f32 (int_arm64_neon_fmaxnmv (v2f32 V64:$Rn))),
2954 (FMAXNMPv2i32p V64:$Rn)>;
2955 def : Pat<(f64 (int_arm64_neon_fmaxnmv (v2f64 V128:$Rn))),
2956 (FMAXNMPv2i64p V128:$Rn)>;
2957 def : Pat<(f32 (int_arm64_neon_fmaxv (v2f32 V64:$Rn))),
2958 (FMAXPv2i32p V64:$Rn)>;
2959 def : Pat<(f64 (int_arm64_neon_fmaxv (v2f64 V128:$Rn))),
2960 (FMAXPv2i64p V128:$Rn)>;
2961 def : Pat<(f32 (int_arm64_neon_fminnmv (v2f32 V64:$Rn))),
2962 (FMINNMPv2i32p V64:$Rn)>;
2963 def : Pat<(f64 (int_arm64_neon_fminnmv (v2f64 V128:$Rn))),
2964 (FMINNMPv2i64p V128:$Rn)>;
2965 def : Pat<(f32 (int_arm64_neon_fminv (v2f32 V64:$Rn))),
2966 (FMINPv2i32p V64:$Rn)>;
2967 def : Pat<(f64 (int_arm64_neon_fminv (v2f64 V128:$Rn))),
2968 (FMINPv2i64p V128:$Rn)>;
2970 //----------------------------------------------------------------------------
2971 // AdvSIMD INS/DUP instructions
2972 //----------------------------------------------------------------------------
2974 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
2975 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
2976 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
2977 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
2978 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
2979 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
2980 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
2982 def DUPv2i64lane : SIMDDup64FromElement;
2983 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
2984 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
2985 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
2986 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
2987 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
2988 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
2990 def : Pat<(v2f32 (ARM64dup (f32 FPR32:$Rn))),
2991 (v2f32 (DUPv2i32lane
2992 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
2994 def : Pat<(v4f32 (ARM64dup (f32 FPR32:$Rn))),
2995 (v4f32 (DUPv4i32lane
2996 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
2998 def : Pat<(v2f64 (ARM64dup (f64 FPR64:$Rn))),
2999 (v2f64 (DUPv2i64lane
3000 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3003 def : Pat<(v2f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3004 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3005 def : Pat<(v4f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3006 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3007 def : Pat<(v2f64 (ARM64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3008 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3013 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3014 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3015 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3016 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3017 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3018 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3019 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3020 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3021 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3022 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3023 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3024 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3026 // Extracting i8 or i16 elements will have the zero-extend transformed to
3027 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3028 // for ARM64. Match these patterns here since UMOV already zeroes out the high
3029 // bits of the destination register.
3030 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3032 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3033 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3035 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3039 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3040 (SUBREG_TO_REG (i32 0),
3041 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3042 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3043 (SUBREG_TO_REG (i32 0),
3044 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3046 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3047 (SUBREG_TO_REG (i32 0),
3048 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3049 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3050 (SUBREG_TO_REG (i32 0),
3051 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3053 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3054 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3055 (i32 FPR32:$Rn), ssub))>;
3056 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3057 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3058 (i32 FPR32:$Rn), ssub))>;
3059 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3060 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3061 (i64 FPR64:$Rn), dsub))>;
3063 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3064 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3065 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3066 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3067 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3068 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3070 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3071 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3074 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3076 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3079 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3080 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3082 V128:$Rn, VectorIndexS:$imm,
3083 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3085 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3086 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3088 V128:$Rn, VectorIndexD:$imm,
3089 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3092 // Copy an element at a constant index in one vector into a constant indexed
3093 // element of another.
3094 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3095 // index type and INS extension
3096 def : Pat<(v16i8 (int_arm64_neon_vcopy_lane
3097 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3098 VectorIndexB:$idx2)),
3100 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3102 def : Pat<(v8i16 (int_arm64_neon_vcopy_lane
3103 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3104 VectorIndexH:$idx2)),
3106 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3108 def : Pat<(v4i32 (int_arm64_neon_vcopy_lane
3109 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3110 VectorIndexS:$idx2)),
3112 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3114 def : Pat<(v2i64 (int_arm64_neon_vcopy_lane
3115 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3116 VectorIndexD:$idx2)),
3118 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3121 // Floating point vector extractions are codegen'd as either a sequence of
3122 // subregister extractions, possibly fed by an INS if the lane number is
3123 // anything other than zero.
3124 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3125 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3126 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3127 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3128 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3129 (f64 (EXTRACT_SUBREG
3130 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3131 V128:$Rn, VectorIndexD:$idx),
3133 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3134 (f32 (EXTRACT_SUBREG
3135 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3136 V128:$Rn, VectorIndexS:$idx),
3139 // All concat_vectors operations are canonicalised to act on i64 vectors for
3140 // ARM64. In the general case we need an instruction, which had just as well be
3142 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3143 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3144 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3145 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3147 def : ConcatPat<v2i64, v1i64>;
3148 def : ConcatPat<v2f64, v1f64>;
3149 def : ConcatPat<v4i32, v2i32>;
3150 def : ConcatPat<v4f32, v2f32>;
3151 def : ConcatPat<v8i16, v4i16>;
3152 def : ConcatPat<v16i8, v8i8>;
3154 // If the high lanes are undef, though, we can just ignore them:
3155 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3156 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3157 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3159 def : ConcatUndefPat<v2i64, v1i64>;
3160 def : ConcatUndefPat<v2f64, v1f64>;
3161 def : ConcatUndefPat<v4i32, v2i32>;
3162 def : ConcatUndefPat<v4f32, v2f32>;
3163 def : ConcatUndefPat<v8i16, v4i16>;
3164 def : ConcatUndefPat<v16i8, v8i8>;
3166 //----------------------------------------------------------------------------
3167 // AdvSIMD across lanes instructions
3168 //----------------------------------------------------------------------------
3170 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3171 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3172 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3173 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3174 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3175 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3176 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3177 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_arm64_neon_fmaxnmv>;
3178 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_arm64_neon_fmaxv>;
3179 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_arm64_neon_fminnmv>;
3180 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_arm64_neon_fminv>;
3182 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3183 // If there is a sign extension after this intrinsic, consume it as smov already
3185 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3187 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3188 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3190 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3192 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3193 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3195 // If there is a sign extension after this intrinsic, consume it as smov already
3197 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3199 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3200 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3202 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3204 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3205 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3207 // If there is a sign extension after this intrinsic, consume it as smov already
3209 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3211 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3212 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3214 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3216 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3217 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3219 // If there is a sign extension after this intrinsic, consume it as smov already
3221 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3223 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3224 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3226 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3228 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3229 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3232 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3233 (i32 (EXTRACT_SUBREG
3234 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3235 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3239 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3240 // If there is a masking operation keeping only what has been actually
3241 // generated, consume it.
3242 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3243 (i32 (EXTRACT_SUBREG
3244 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3245 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3247 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3248 (i32 (EXTRACT_SUBREG
3249 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3250 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3252 // If there is a masking operation keeping only what has been actually
3253 // generated, consume it.
3254 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3255 (i32 (EXTRACT_SUBREG
3256 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3257 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3259 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3260 (i32 (EXTRACT_SUBREG
3261 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3262 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3265 // If there is a masking operation keeping only what has been actually
3266 // generated, consume it.
3267 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3268 (i32 (EXTRACT_SUBREG
3269 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3270 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3272 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3273 (i32 (EXTRACT_SUBREG
3274 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3275 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3277 // If there is a masking operation keeping only what has been actually
3278 // generated, consume it.
3279 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3280 (i32 (EXTRACT_SUBREG
3281 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3282 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3284 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3285 (i32 (EXTRACT_SUBREG
3286 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3287 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3290 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3291 (i32 (EXTRACT_SUBREG
3292 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3293 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3298 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3299 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3301 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3302 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3304 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3306 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3307 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3310 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3311 (i32 (EXTRACT_SUBREG
3312 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3313 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3315 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3316 (i32 (EXTRACT_SUBREG
3317 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3318 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3321 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3322 (i64 (EXTRACT_SUBREG
3323 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3324 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3328 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3330 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3331 (i32 (EXTRACT_SUBREG
3332 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3333 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3335 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3336 (i32 (EXTRACT_SUBREG
3337 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3338 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3341 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3342 (i32 (EXTRACT_SUBREG
3343 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3344 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3346 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3347 (i32 (EXTRACT_SUBREG
3348 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3349 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3352 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3353 (i64 (EXTRACT_SUBREG
3354 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3355 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3359 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_arm64_neon_saddv>;
3360 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3361 def : Pat<(i32 (int_arm64_neon_saddv (v2i32 V64:$Rn))),
3362 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3364 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_arm64_neon_uaddv>;
3365 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3366 def : Pat<(i32 (int_arm64_neon_uaddv (v2i32 V64:$Rn))),
3367 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3369 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_arm64_neon_smaxv>;
3370 def : Pat<(i32 (int_arm64_neon_smaxv (v2i32 V64:$Rn))),
3371 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3373 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_arm64_neon_sminv>;
3374 def : Pat<(i32 (int_arm64_neon_sminv (v2i32 V64:$Rn))),
3375 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3377 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_arm64_neon_umaxv>;
3378 def : Pat<(i32 (int_arm64_neon_umaxv (v2i32 V64:$Rn))),
3379 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3381 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_arm64_neon_uminv>;
3382 def : Pat<(i32 (int_arm64_neon_uminv (v2i32 V64:$Rn))),
3383 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3385 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_arm64_neon_saddlv>;
3386 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_arm64_neon_uaddlv>;
3388 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3389 def : Pat<(i64 (int_arm64_neon_saddlv (v2i32 V64:$Rn))),
3390 (i64 (EXTRACT_SUBREG
3391 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3392 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3394 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
3395 def : Pat<(i64 (int_arm64_neon_uaddlv (v2i32 V64:$Rn))),
3396 (i64 (EXTRACT_SUBREG
3397 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3398 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
3401 //------------------------------------------------------------------------------
3402 // AdvSIMD modified immediate instructions
3403 //------------------------------------------------------------------------------
3406 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", ARM64bici>;
3408 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", ARM64orri>;
3412 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
3414 [(set (v2f64 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3415 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
3417 [(set (v2f32 V64:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3418 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
3420 [(set (v4f32 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3424 // EDIT byte mask: scalar
3425 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3426 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
3427 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
3428 // The movi_edit node has the immediate value already encoded, so we use
3429 // a plain imm0_255 here.
3430 def : Pat<(f64 (ARM64movi_edit imm0_255:$shift)),
3431 (MOVID imm0_255:$shift)>;
3433 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
3434 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
3435 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
3436 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
3438 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
3439 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
3440 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
3441 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
3443 // EDIT byte mask: 2d
3445 // The movi_edit node has the immediate value already encoded, so we use
3446 // a plain imm0_255 in the pattern
3447 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3448 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
3451 [(set (v2i64 V128:$Rd), (ARM64movi_edit imm0_255:$imm8))]>;
3454 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
3455 // Complexity is added to break a tie with a plain MOVI.
3456 let AddedComplexity = 1 in {
3457 def : Pat<(f32 fpimm0),
3458 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
3460 def : Pat<(f64 fpimm0),
3461 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
3465 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3466 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3467 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3468 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3470 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3471 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3472 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3473 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3475 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3476 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
3477 def : Pat<(v2i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3478 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
3479 def : Pat<(v4i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3480 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
3481 def : Pat<(v4i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3482 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
3483 def : Pat<(v8i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3484 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
3486 // EDIT per word: 2s & 4s with MSL shifter
3487 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
3488 [(set (v2i32 V64:$Rd),
3489 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3490 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
3491 [(set (v4i32 V128:$Rd),
3492 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3494 // Per byte: 8b & 16b
3495 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
3497 [(set (v8i8 V64:$Rd), (ARM64movi imm0_255:$imm8))]>;
3498 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
3500 [(set (v16i8 V128:$Rd), (ARM64movi imm0_255:$imm8))]>;
3504 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3505 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
3506 def : Pat<(v2i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3507 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
3508 def : Pat<(v4i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3509 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
3510 def : Pat<(v4i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3511 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
3512 def : Pat<(v8i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3513 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
3515 // EDIT per word: 2s & 4s with MSL shifter
3516 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
3517 [(set (v2i32 V64:$Rd),
3518 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3519 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
3520 [(set (v4i32 V128:$Rd),
3521 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3523 //----------------------------------------------------------------------------
3524 // AdvSIMD indexed element
3525 //----------------------------------------------------------------------------
3527 let neverHasSideEffects = 1 in {
3528 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
3529 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
3532 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
3533 // instruction expects the addend first, while the intrinsic expects it last.
3535 // On the other hand, there are quite a few valid combinatorial options due to
3536 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
3537 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3538 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
3539 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3540 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
3542 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3543 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
3544 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3545 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
3546 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3547 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
3548 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3549 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
3551 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
3552 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3554 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3555 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3556 VectorIndexS:$idx))),
3557 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3558 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3559 (v2f32 (ARM64duplane32
3560 (v4f32 (insert_subvector undef,
3561 (v2f32 (fneg V64:$Rm)),
3563 VectorIndexS:$idx)))),
3564 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3565 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3566 VectorIndexS:$idx)>;
3567 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3568 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
3569 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3570 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
3572 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3574 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3575 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3576 VectorIndexS:$idx))),
3577 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
3578 VectorIndexS:$idx)>;
3579 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3580 (v4f32 (ARM64duplane32
3581 (v4f32 (insert_subvector undef,
3582 (v2f32 (fneg V64:$Rm)),
3584 VectorIndexS:$idx)))),
3585 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
3586 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3587 VectorIndexS:$idx)>;
3588 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3589 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
3590 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
3591 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
3593 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
3594 // (DUPLANE from 64-bit would be trivial).
3595 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
3596 (ARM64duplane64 (v2f64 (fneg V128:$Rm)),
3597 VectorIndexD:$idx))),
3599 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3600 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
3601 (ARM64dup (f64 (fneg FPR64Op:$Rm))))),
3602 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
3603 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
3605 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
3606 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
3607 (vector_extract (v4f32 (fneg V128:$Rm)),
3608 VectorIndexS:$idx))),
3609 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
3610 V128:$Rm, VectorIndexS:$idx)>;
3611 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
3612 (vector_extract (v2f32 (fneg V64:$Rm)),
3613 VectorIndexS:$idx))),
3614 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
3615 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
3617 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
3618 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
3619 (vector_extract (v2f64 (fneg V128:$Rm)),
3620 VectorIndexS:$idx))),
3621 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
3622 V128:$Rm, VectorIndexS:$idx)>;
3625 defm : FMLSIndexedAfterNegPatterns<
3626 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
3627 defm : FMLSIndexedAfterNegPatterns<
3628 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
3630 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_arm64_neon_fmulx>;
3631 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
3633 def : Pat<(v2f32 (fmul V64:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
3634 (FMULv2i32_indexed V64:$Rn,
3635 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
3637 def : Pat<(v4f32 (fmul V128:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
3638 (FMULv4i32_indexed V128:$Rn,
3639 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
3641 def : Pat<(v2f64 (fmul V128:$Rn, (ARM64dup (f64 FPR64:$Rm)))),
3642 (FMULv2i64_indexed V128:$Rn,
3643 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
3646 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_arm64_neon_sqdmulh>;
3647 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_arm64_neon_sqrdmulh>;
3648 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
3649 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
3650 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
3651 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
3652 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
3653 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
3654 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3655 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
3656 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3657 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
3658 int_arm64_neon_smull>;
3659 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
3660 int_arm64_neon_sqadd>;
3661 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
3662 int_arm64_neon_sqsub>;
3663 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_arm64_neon_sqdmull>;
3664 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
3665 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3666 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
3667 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3668 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
3669 int_arm64_neon_umull>;
3671 // A scalar sqdmull with the second operand being a vector lane can be
3672 // handled directly with the indexed instruction encoding.
3673 def : Pat<(int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3674 (vector_extract (v4i32 V128:$Vm),
3675 VectorIndexS:$idx)),
3676 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
3678 //----------------------------------------------------------------------------
3679 // AdvSIMD scalar shift instructions
3680 //----------------------------------------------------------------------------
3681 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
3682 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
3683 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
3684 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
3685 // Codegen patterns for the above. We don't put these directly on the
3686 // instructions because TableGen's type inference can't handle the truth.
3687 // Having the same base pattern for fp <--> int totally freaks it out.
3688 def : Pat<(int_arm64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
3689 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
3690 def : Pat<(int_arm64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
3691 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
3692 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
3693 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
3694 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
3695 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
3696 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
3698 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
3699 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
3701 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
3702 def : Pat<(int_arm64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
3703 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
3704 def : Pat<(int_arm64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
3705 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
3706 def : Pat<(f64 (int_arm64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
3707 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3708 def : Pat<(f64 (int_arm64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
3709 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3710 def : Pat<(v1f64 (int_arm64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
3712 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3713 def : Pat<(v1f64 (int_arm64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
3715 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3717 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", ARM64vshl>;
3718 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
3719 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
3720 int_arm64_neon_sqrshrn>;
3721 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
3722 int_arm64_neon_sqrshrun>;
3723 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
3724 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
3725 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
3726 int_arm64_neon_sqshrn>;
3727 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
3728 int_arm64_neon_sqshrun>;
3729 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
3730 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", ARM64srshri>;
3731 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
3732 TriOpFrag<(add node:$LHS,
3733 (ARM64srshri node:$MHS, node:$RHS))>>;
3734 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", ARM64vashr>;
3735 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
3736 TriOpFrag<(add node:$LHS,
3737 (ARM64vashr node:$MHS, node:$RHS))>>;
3738 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
3739 int_arm64_neon_uqrshrn>;
3740 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
3741 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
3742 int_arm64_neon_uqshrn>;
3743 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", ARM64urshri>;
3744 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
3745 TriOpFrag<(add node:$LHS,
3746 (ARM64urshri node:$MHS, node:$RHS))>>;
3747 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", ARM64vlshr>;
3748 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
3749 TriOpFrag<(add node:$LHS,
3750 (ARM64vlshr node:$MHS, node:$RHS))>>;
3752 //----------------------------------------------------------------------------
3753 // AdvSIMD vector shift instructions
3754 //----------------------------------------------------------------------------
3755 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_arm64_neon_vcvtfp2fxs>;
3756 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_arm64_neon_vcvtfp2fxu>;
3757 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
3758 int_arm64_neon_vcvtfxs2fp>;
3759 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
3760 int_arm64_neon_rshrn>;
3761 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", ARM64vshl>;
3762 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
3763 BinOpFrag<(trunc (ARM64vashr node:$LHS, node:$RHS))>>;
3764 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_arm64_neon_vsli>;
3765 def : Pat<(v1i64 (int_arm64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
3766 (i32 vecshiftL64:$imm))),
3767 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
3768 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
3769 int_arm64_neon_sqrshrn>;
3770 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
3771 int_arm64_neon_sqrshrun>;
3772 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
3773 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
3774 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
3775 int_arm64_neon_sqshrn>;
3776 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
3777 int_arm64_neon_sqshrun>;
3778 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_arm64_neon_vsri>;
3779 def : Pat<(v1i64 (int_arm64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
3780 (i32 vecshiftR64:$imm))),
3781 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
3782 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", ARM64srshri>;
3783 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
3784 TriOpFrag<(add node:$LHS,
3785 (ARM64srshri node:$MHS, node:$RHS))> >;
3786 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
3787 BinOpFrag<(ARM64vshl (sext node:$LHS), node:$RHS)>>;
3789 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", ARM64vashr>;
3790 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
3791 TriOpFrag<(add node:$LHS, (ARM64vashr node:$MHS, node:$RHS))>>;
3792 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
3793 int_arm64_neon_vcvtfxu2fp>;
3794 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
3795 int_arm64_neon_uqrshrn>;
3796 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
3797 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
3798 int_arm64_neon_uqshrn>;
3799 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", ARM64urshri>;
3800 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
3801 TriOpFrag<(add node:$LHS,
3802 (ARM64urshri node:$MHS, node:$RHS))> >;
3803 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
3804 BinOpFrag<(ARM64vshl (zext node:$LHS), node:$RHS)>>;
3805 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", ARM64vlshr>;
3806 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
3807 TriOpFrag<(add node:$LHS, (ARM64vlshr node:$MHS, node:$RHS))> >;
3809 // SHRN patterns for when a logical right shift was used instead of arithmetic
3810 // (the immediate guarantees no sign bits actually end up in the result so it
3812 def : Pat<(v8i8 (trunc (ARM64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
3813 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
3814 def : Pat<(v4i16 (trunc (ARM64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
3815 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
3816 def : Pat<(v2i32 (trunc (ARM64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
3817 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
3819 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
3820 (trunc (ARM64vlshr (v8i16 V128:$Rn),
3821 vecshiftR16Narrow:$imm)))),
3822 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3823 V128:$Rn, vecshiftR16Narrow:$imm)>;
3824 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
3825 (trunc (ARM64vlshr (v4i32 V128:$Rn),
3826 vecshiftR32Narrow:$imm)))),
3827 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3828 V128:$Rn, vecshiftR32Narrow:$imm)>;
3829 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
3830 (trunc (ARM64vlshr (v2i64 V128:$Rn),
3831 vecshiftR64Narrow:$imm)))),
3832 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3833 V128:$Rn, vecshiftR32Narrow:$imm)>;
3835 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
3836 // Anyexts are implemented as zexts.
3837 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
3838 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
3839 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
3840 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
3841 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
3842 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
3843 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
3844 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
3845 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
3846 // Also match an extend from the upper half of a 128 bit source register.
3847 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3848 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
3849 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3850 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
3851 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3852 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
3853 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3854 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
3855 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3856 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
3857 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3858 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
3859 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3860 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
3861 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3862 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
3863 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3864 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
3866 // Vector shift sxtl aliases
3867 def : InstAlias<"sxtl.8h $dst, $src1",
3868 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3869 def : InstAlias<"sxtl $dst.8h, $src1.8b",
3870 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3871 def : InstAlias<"sxtl.4s $dst, $src1",
3872 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
3873 def : InstAlias<"sxtl $dst.4s, $src1.4h",
3874 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
3875 def : InstAlias<"sxtl.2d $dst, $src1",
3876 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
3877 def : InstAlias<"sxtl $dst.2d, $src1.2s",
3878 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
3880 // Vector shift sxtl2 aliases
3881 def : InstAlias<"sxtl2.8h $dst, $src1",
3882 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
3883 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
3884 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
3885 def : InstAlias<"sxtl2.4s $dst, $src1",
3886 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
3887 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
3888 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
3889 def : InstAlias<"sxtl2.2d $dst, $src1",
3890 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
3891 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
3892 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
3894 // Vector shift uxtl aliases
3895 def : InstAlias<"uxtl.8h $dst, $src1",
3896 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3897 def : InstAlias<"uxtl $dst.8h, $src1.8b",
3898 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3899 def : InstAlias<"uxtl.4s $dst, $src1",
3900 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
3901 def : InstAlias<"uxtl $dst.4s, $src1.4h",
3902 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
3903 def : InstAlias<"uxtl.2d $dst, $src1",
3904 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
3905 def : InstAlias<"uxtl $dst.2d, $src1.2s",
3906 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
3908 // Vector shift uxtl2 aliases
3909 def : InstAlias<"uxtl2.8h $dst, $src1",
3910 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
3911 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
3912 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
3913 def : InstAlias<"uxtl2.4s $dst, $src1",
3914 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
3915 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
3916 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
3917 def : InstAlias<"uxtl2.2d $dst, $src1",
3918 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
3919 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
3920 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
3922 // If an integer is about to be converted to a floating point value,
3923 // just load it on the floating point unit.
3924 // These patterns are more complex because floating point loads do not
3925 // support sign extension.
3926 // The sign extension has to be explicitly added and is only supported for
3927 // one step: byte-to-half, half-to-word, word-to-doubleword.
3928 // SCVTF GPR -> FPR is 9 cycles.
3929 // SCVTF FPR -> FPR is 4 cyclces.
3930 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
3931 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
3932 // and still being faster.
3933 // However, this is not good for code size.
3934 // 8-bits -> float. 2 sizes step-up.
3935 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 ro_indexed8:$addr)))),
3936 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3941 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3942 (LDRBro ro_indexed8:$addr),
3947 ssub)))>, Requires<[NotForCodeSize]>;
3948 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 am_indexed8:$addr)))),
3949 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3954 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3955 (LDRBui am_indexed8:$addr),
3960 ssub)))>, Requires<[NotForCodeSize]>;
3961 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 am_unscaled8:$addr)))),
3962 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3967 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3968 (LDURBi am_unscaled8:$addr),
3973 ssub)))>, Requires<[NotForCodeSize]>;
3974 // 16-bits -> float. 1 size step-up.
3975 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 ro_indexed16:$addr)))),
3976 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3978 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3979 (LDRHro ro_indexed16:$addr),
3982 ssub)))>, Requires<[NotForCodeSize]>;
3983 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 am_indexed16:$addr)))),
3984 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3986 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3987 (LDRHui am_indexed16:$addr),
3990 ssub)))>, Requires<[NotForCodeSize]>;
3991 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 am_unscaled16:$addr)))),
3992 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3994 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3995 (LDURHi am_unscaled16:$addr),
3998 ssub)))>, Requires<[NotForCodeSize]>;
3999 // 32-bits to 32-bits are handled in target specific dag combine:
4000 // performIntToFpCombine.
4001 // 64-bits integer to 32-bits floating point, not possible with
4002 // SCVTF on floating point registers (both source and destination
4003 // must have the same size).
4005 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4006 // 8-bits -> double. 3 size step-up: give up.
4007 // 16-bits -> double. 2 size step.
4008 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 ro_indexed16:$addr)))),
4009 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4014 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4015 (LDRHro ro_indexed16:$addr),
4020 dsub)))>, Requires<[NotForCodeSize]>;
4021 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 am_indexed16:$addr)))),
4022 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4027 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4028 (LDRHui am_indexed16:$addr),
4033 dsub)))>, Requires<[NotForCodeSize]>;
4034 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 am_unscaled16:$addr)))),
4035 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4040 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4041 (LDURHi am_unscaled16:$addr),
4046 dsub)))>, Requires<[NotForCodeSize]>;
4047 // 32-bits -> double. 1 size step-up.
4048 def : Pat <(f64 (sint_to_fp (i32 (load ro_indexed32:$addr)))),
4049 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4051 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4052 (LDRSro ro_indexed32:$addr),
4055 dsub)))>, Requires<[NotForCodeSize]>;
4056 def : Pat <(f64 (sint_to_fp (i32 (load am_indexed32:$addr)))),
4057 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4059 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4060 (LDRSui am_indexed32:$addr),
4063 dsub)))>, Requires<[NotForCodeSize]>;
4064 def : Pat <(f64 (sint_to_fp (i32 (load am_unscaled32:$addr)))),
4065 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4067 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4068 (LDURSi am_unscaled32:$addr),
4071 dsub)))>, Requires<[NotForCodeSize]>;
4072 // 64-bits -> double are handled in target specific dag combine:
4073 // performIntToFpCombine.
4076 //----------------------------------------------------------------------------
4077 // AdvSIMD Load-Store Structure
4078 //----------------------------------------------------------------------------
4079 defm LD1 : SIMDLd1Multiple<"ld1">;
4080 defm LD2 : SIMDLd2Multiple<"ld2">;
4081 defm LD3 : SIMDLd3Multiple<"ld3">;
4082 defm LD4 : SIMDLd4Multiple<"ld4">;
4084 defm ST1 : SIMDSt1Multiple<"st1">;
4085 defm ST2 : SIMDSt2Multiple<"st2">;
4086 defm ST3 : SIMDSt3Multiple<"st3">;
4087 defm ST4 : SIMDSt4Multiple<"st4">;
4089 class Ld1Pat<ValueType ty, Instruction INST>
4090 : Pat<(ty (load am_simdnoindex:$vaddr)), (INST am_simdnoindex:$vaddr)>;
4092 def : Ld1Pat<v16i8, LD1Onev16b>;
4093 def : Ld1Pat<v8i16, LD1Onev8h>;
4094 def : Ld1Pat<v4i32, LD1Onev4s>;
4095 def : Ld1Pat<v2i64, LD1Onev2d>;
4096 def : Ld1Pat<v8i8, LD1Onev8b>;
4097 def : Ld1Pat<v4i16, LD1Onev4h>;
4098 def : Ld1Pat<v2i32, LD1Onev2s>;
4099 def : Ld1Pat<v1i64, LD1Onev1d>;
4101 class St1Pat<ValueType ty, Instruction INST>
4102 : Pat<(store ty:$Vt, am_simdnoindex:$vaddr),
4103 (INST ty:$Vt, am_simdnoindex:$vaddr)>;
4105 def : St1Pat<v16i8, ST1Onev16b>;
4106 def : St1Pat<v8i16, ST1Onev8h>;
4107 def : St1Pat<v4i32, ST1Onev4s>;
4108 def : St1Pat<v2i64, ST1Onev2d>;
4109 def : St1Pat<v8i8, ST1Onev8b>;
4110 def : St1Pat<v4i16, ST1Onev4h>;
4111 def : St1Pat<v2i32, ST1Onev2s>;
4112 def : St1Pat<v1i64, ST1Onev1d>;
4118 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4119 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4120 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4121 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4122 let mayLoad = 1, neverHasSideEffects = 1 in {
4123 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4124 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4125 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4126 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4127 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4128 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4129 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4130 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4131 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4132 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4133 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4134 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4135 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4136 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4137 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4138 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4141 def : Pat<(v8i8 (ARM64dup (i32 (extloadi8 am_simdnoindex:$vaddr)))),
4142 (LD1Rv8b am_simdnoindex:$vaddr)>;
4143 def : Pat<(v16i8 (ARM64dup (i32 (extloadi8 am_simdnoindex:$vaddr)))),
4144 (LD1Rv16b am_simdnoindex:$vaddr)>;
4145 def : Pat<(v4i16 (ARM64dup (i32 (extloadi16 am_simdnoindex:$vaddr)))),
4146 (LD1Rv4h am_simdnoindex:$vaddr)>;
4147 def : Pat<(v8i16 (ARM64dup (i32 (extloadi16 am_simdnoindex:$vaddr)))),
4148 (LD1Rv8h am_simdnoindex:$vaddr)>;
4149 def : Pat<(v2i32 (ARM64dup (i32 (load am_simdnoindex:$vaddr)))),
4150 (LD1Rv2s am_simdnoindex:$vaddr)>;
4151 def : Pat<(v4i32 (ARM64dup (i32 (load am_simdnoindex:$vaddr)))),
4152 (LD1Rv4s am_simdnoindex:$vaddr)>;
4153 def : Pat<(v2i64 (ARM64dup (i64 (load am_simdnoindex:$vaddr)))),
4154 (LD1Rv2d am_simdnoindex:$vaddr)>;
4155 def : Pat<(v1i64 (ARM64dup (i64 (load am_simdnoindex:$vaddr)))),
4156 (LD1Rv1d am_simdnoindex:$vaddr)>;
4157 // Grab the floating point version too
4158 def : Pat<(v2f32 (ARM64dup (f32 (load am_simdnoindex:$vaddr)))),
4159 (LD1Rv2s am_simdnoindex:$vaddr)>;
4160 def : Pat<(v4f32 (ARM64dup (f32 (load am_simdnoindex:$vaddr)))),
4161 (LD1Rv4s am_simdnoindex:$vaddr)>;
4162 def : Pat<(v2f64 (ARM64dup (f64 (load am_simdnoindex:$vaddr)))),
4163 (LD1Rv2d am_simdnoindex:$vaddr)>;
4164 def : Pat<(v1f64 (ARM64dup (f64 (load am_simdnoindex:$vaddr)))),
4165 (LD1Rv1d am_simdnoindex:$vaddr)>;
4167 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4168 ValueType VTy, ValueType STy, Instruction LD1>
4169 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4170 (STy (scalar_load am_simdnoindex:$vaddr)), VecIndex:$idx),
4171 (LD1 VecListOne128:$Rd, VecIndex:$idx, am_simdnoindex:$vaddr)>;
4173 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4174 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4175 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4176 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4177 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4178 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4180 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4181 ValueType VTy, ValueType STy, Instruction LD1>
4182 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4183 (STy (scalar_load am_simdnoindex:$vaddr)), VecIndex:$idx),
4185 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4186 VecIndex:$idx, am_simdnoindex:$vaddr),
4189 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4190 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4191 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4192 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4195 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4196 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4197 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4198 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4201 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4202 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4203 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4204 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4206 let AddedComplexity = 8 in
4207 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4208 ValueType VTy, ValueType STy, Instruction ST1>
4210 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4211 am_simdnoindex:$vaddr),
4212 (ST1 VecListOne128:$Vt, VecIndex:$idx, am_simdnoindex:$vaddr)>;
4214 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4215 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4216 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4217 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4218 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4219 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4221 let AddedComplexity = 8 in
4222 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4223 ValueType VTy, ValueType STy, Instruction ST1>
4225 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4226 am_simdnoindex:$vaddr),
4227 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4228 VecIndex:$idx, am_simdnoindex:$vaddr)>;
4230 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4231 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4232 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4233 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4235 let mayStore = 1, neverHasSideEffects = 1 in {
4236 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4237 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4238 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4239 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4240 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4241 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4242 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4243 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4244 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4245 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4246 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4247 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4250 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4251 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4252 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4253 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4255 //----------------------------------------------------------------------------
4256 // Crypto extensions
4257 //----------------------------------------------------------------------------
4259 def AESErr : AESTiedInst<0b0100, "aese", int_arm64_crypto_aese>;
4260 def AESDrr : AESTiedInst<0b0101, "aesd", int_arm64_crypto_aesd>;
4261 def AESMCrr : AESInst< 0b0110, "aesmc", int_arm64_crypto_aesmc>;
4262 def AESIMCrr : AESInst< 0b0111, "aesimc", int_arm64_crypto_aesimc>;
4264 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_arm64_crypto_sha1c>;
4265 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_arm64_crypto_sha1p>;
4266 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_arm64_crypto_sha1m>;
4267 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_arm64_crypto_sha1su0>;
4268 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_arm64_crypto_sha256h>;
4269 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_arm64_crypto_sha256h2>;
4270 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_arm64_crypto_sha256su1>;
4272 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_arm64_crypto_sha1h>;
4273 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_arm64_crypto_sha1su1>;
4274 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_arm64_crypto_sha256su0>;
4276 //----------------------------------------------------------------------------
4278 //----------------------------------------------------------------------------
4279 // FIXME: Like for X86, these should go in their own separate .td file.
4281 // Any instruction that defines a 32-bit result leaves the high half of the
4282 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4283 // be copying from a truncate. But any other 32-bit operation will zero-extend
4285 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4286 def def32 : PatLeaf<(i32 GPR32:$src), [{
4287 return N->getOpcode() != ISD::TRUNCATE &&
4288 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4289 N->getOpcode() != ISD::CopyFromReg;
4292 // In the case of a 32-bit def that is known to implicitly zero-extend,
4293 // we can use a SUBREG_TO_REG.
4294 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4296 // For an anyext, we don't care what the high bits are, so we can perform an
4297 // INSERT_SUBREF into an IMPLICIT_DEF.
4298 def : Pat<(i64 (anyext GPR32:$src)),
4299 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4301 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4302 // instruction (UBFM) on the enclosing super-reg.
4303 def : Pat<(i64 (zext GPR32:$src)),
4304 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4306 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4307 // containing super-reg.
4308 def : Pat<(i64 (sext GPR32:$src)),
4309 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4310 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4311 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4312 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4313 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4314 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4315 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4316 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4318 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4319 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4320 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4321 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4322 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4323 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4325 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
4326 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4327 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
4328 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4329 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4330 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4332 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4333 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4334 (i64 (i64shift_a imm0_63:$imm)),
4335 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
4337 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
4338 // AddedComplexity for the following patterns since we want to match sext + sra
4339 // patterns before we attempt to match a single sra node.
4340 let AddedComplexity = 20 in {
4341 // We support all sext + sra combinations which preserve at least one bit of the
4342 // original value which is to be sign extended. E.g. we support shifts up to
4344 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
4345 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
4346 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
4347 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
4349 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
4350 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
4351 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
4352 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
4354 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
4355 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4356 (i64 imm0_31:$imm), 31)>;
4357 } // AddedComplexity = 20
4359 // To truncate, we can simply extract from a subregister.
4360 def : Pat<(i32 (trunc GPR64sp:$src)),
4361 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
4363 // __builtin_trap() uses the BRK instruction on ARM64.
4364 def : Pat<(trap), (BRK 1)>;
4366 // Conversions within AdvSIMD types in the same register size are free.
4368 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
4369 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
4370 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
4371 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4372 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
4373 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4375 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
4376 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
4377 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
4378 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4379 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
4380 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4382 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
4383 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
4384 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
4385 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4386 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
4387 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4389 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
4390 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
4391 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
4392 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4393 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
4394 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4396 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
4397 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
4398 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
4399 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
4400 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
4401 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
4403 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
4404 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
4405 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
4406 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
4407 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
4408 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
4410 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
4411 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
4412 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
4413 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
4414 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
4415 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
4418 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
4419 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
4420 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
4421 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
4422 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
4424 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
4425 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
4426 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
4427 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
4428 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
4429 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
4431 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
4432 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
4433 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
4434 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
4435 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
4436 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
4438 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
4439 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
4440 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
4441 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
4442 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
4443 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
4445 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
4446 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
4447 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
4448 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
4449 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
4450 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
4452 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
4453 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
4454 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
4455 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
4456 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
4457 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
4459 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
4460 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
4461 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
4462 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
4463 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
4464 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
4466 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
4467 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4468 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
4469 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4470 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
4471 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4472 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
4473 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4475 // A 64-bit subvector insert to the first 128-bit vector position
4476 // is a subregister copy that needs no instruction.
4477 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
4478 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4479 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
4480 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4481 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
4482 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4483 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
4484 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4485 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
4486 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4487 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
4488 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4490 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
4492 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
4493 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
4494 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
4495 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
4496 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
4497 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
4498 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
4499 // so we match on v4f32 here, not v2f32. This will also catch adding
4500 // the low two lanes of a true v4f32 vector.
4501 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
4502 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
4503 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
4505 // Scalar 64-bit shifts in FPR64 registers.
4506 def : Pat<(i64 (int_arm64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4507 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4508 def : Pat<(i64 (int_arm64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4509 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4510 def : Pat<(i64 (int_arm64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4511 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4512 def : Pat<(i64 (int_arm64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4513 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4515 // Tail call return handling. These are all compiler pseudo-instructions,
4516 // so no encoding information or anything like that.
4517 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
4518 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst), []>;
4519 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst), []>;
4522 def : Pat<(ARM64tcret tcGPR64:$dst), (TCRETURNri tcGPR64:$dst)>;
4523 def : Pat<(ARM64tcret (i64 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4524 def : Pat<(ARM64tcret (i64 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4526 include "ARM64InstrAtomics.td"