1 //===-- ARM64ISelLowering.cpp - ARM64 DAG Lowering Implementation --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "ARM64ISelLowering.h"
15 #include "ARM64PerfectShuffle.h"
16 #include "ARM64Subtarget.h"
17 #include "ARM64CallingConv.h"
18 #include "ARM64MachineFunctionInfo.h"
19 #include "ARM64TargetMachine.h"
20 #include "ARM64TargetObjectFile.h"
21 #include "MCTargetDesc/ARM64AddressingModes.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
37 #define DEBUG_TYPE "arm64-lower"
39 STATISTIC(NumTailCalls, "Number of tail calls");
40 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
47 static cl::opt<AlignMode>
48 Align(cl::desc("Load/store alignment support"),
49 cl::Hidden, cl::init(NoStrictAlign),
51 clEnumValN(StrictAlign, "arm64-strict-align",
52 "Disallow all unaligned memory accesses"),
53 clEnumValN(NoStrictAlign, "arm64-no-strict-align",
54 "Allow unaligned memory accesses"),
57 // Place holder until extr generation is tested fully.
59 EnableARM64ExtrGeneration("arm64-extr-generation", cl::Hidden,
60 cl::desc("Allow ARM64 (or (shift)(shift))->extract"),
64 EnableARM64SlrGeneration("arm64-shift-insert-generation", cl::Hidden,
65 cl::desc("Allow ARM64 SLI/SRI formation"),
68 //===----------------------------------------------------------------------===//
69 // ARM64 Lowering public interface.
70 //===----------------------------------------------------------------------===//
71 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
72 if (TM.getSubtarget<ARM64Subtarget>().isTargetDarwin())
73 return new ARM64_MachoTargetObjectFile();
75 return new ARM64_ELFTargetObjectFile();
78 ARM64TargetLowering::ARM64TargetLowering(ARM64TargetMachine &TM)
79 : TargetLowering(TM, createTLOF(TM)) {
80 Subtarget = &TM.getSubtarget<ARM64Subtarget>();
82 // ARM64 doesn't have comparisons which set GPRs or setcc instructions, so
83 // we have to make something up. Arbitrarily, choose ZeroOrOne.
84 setBooleanContents(ZeroOrOneBooleanContent);
85 // When comparing vectors the result sets the different elements in the
86 // vector to all-one or all-zero.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // Set up the register classes.
90 addRegisterClass(MVT::i32, &ARM64::GPR32allRegClass);
91 addRegisterClass(MVT::i64, &ARM64::GPR64allRegClass);
93 if (Subtarget->hasFPARMv8()) {
94 addRegisterClass(MVT::f16, &ARM64::FPR16RegClass);
95 addRegisterClass(MVT::f32, &ARM64::FPR32RegClass);
96 addRegisterClass(MVT::f64, &ARM64::FPR64RegClass);
97 addRegisterClass(MVT::f128, &ARM64::FPR128RegClass);
100 if (Subtarget->hasNEON()) {
101 addRegisterClass(MVT::v16i8, &ARM64::FPR8RegClass);
102 addRegisterClass(MVT::v8i16, &ARM64::FPR16RegClass);
103 // Someone set us up the NEON.
104 addDRTypeForNEON(MVT::v2f32);
105 addDRTypeForNEON(MVT::v8i8);
106 addDRTypeForNEON(MVT::v4i16);
107 addDRTypeForNEON(MVT::v2i32);
108 addDRTypeForNEON(MVT::v1i64);
109 addDRTypeForNEON(MVT::v1f64);
111 addQRTypeForNEON(MVT::v4f32);
112 addQRTypeForNEON(MVT::v2f64);
113 addQRTypeForNEON(MVT::v16i8);
114 addQRTypeForNEON(MVT::v8i16);
115 addQRTypeForNEON(MVT::v4i32);
116 addQRTypeForNEON(MVT::v2i64);
119 // Compute derived properties from the register classes
120 computeRegisterProperties();
122 // Provide all sorts of operation actions
123 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
124 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
125 setOperationAction(ISD::SETCC, MVT::i32, Custom);
126 setOperationAction(ISD::SETCC, MVT::i64, Custom);
127 setOperationAction(ISD::SETCC, MVT::f32, Custom);
128 setOperationAction(ISD::SETCC, MVT::f64, Custom);
129 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
130 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
131 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
132 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
133 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
134 setOperationAction(ISD::SELECT, MVT::i32, Custom);
135 setOperationAction(ISD::SELECT, MVT::i64, Custom);
136 setOperationAction(ISD::SELECT, MVT::f32, Custom);
137 setOperationAction(ISD::SELECT, MVT::f64, Custom);
138 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
139 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
140 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
141 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
142 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
143 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
145 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
146 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
147 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
149 setOperationAction(ISD::FREM, MVT::f32, Expand);
150 setOperationAction(ISD::FREM, MVT::f64, Expand);
151 setOperationAction(ISD::FREM, MVT::f80, Expand);
153 // Custom lowering hooks are needed for XOR
154 // to fold it into CSINC/CSINV.
155 setOperationAction(ISD::XOR, MVT::i32, Custom);
156 setOperationAction(ISD::XOR, MVT::i64, Custom);
158 // Virtually no operation on f128 is legal, but LLVM can't expand them when
159 // there's a valid register class, so we need custom operations in most cases.
160 setOperationAction(ISD::FABS, MVT::f128, Expand);
161 setOperationAction(ISD::FADD, MVT::f128, Custom);
162 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
163 setOperationAction(ISD::FCOS, MVT::f128, Expand);
164 setOperationAction(ISD::FDIV, MVT::f128, Custom);
165 setOperationAction(ISD::FMA, MVT::f128, Expand);
166 setOperationAction(ISD::FMUL, MVT::f128, Custom);
167 setOperationAction(ISD::FNEG, MVT::f128, Expand);
168 setOperationAction(ISD::FPOW, MVT::f128, Expand);
169 setOperationAction(ISD::FREM, MVT::f128, Expand);
170 setOperationAction(ISD::FRINT, MVT::f128, Expand);
171 setOperationAction(ISD::FSIN, MVT::f128, Expand);
172 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
173 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
174 setOperationAction(ISD::FSUB, MVT::f128, Custom);
175 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
176 setOperationAction(ISD::SETCC, MVT::f128, Custom);
177 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
178 setOperationAction(ISD::SELECT, MVT::f128, Custom);
179 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
180 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
182 // Lowering for many of the conversions is actually specified by the non-f128
183 // type. The LowerXXX function will be trivial when f128 isn't involved.
184 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
185 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
186 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
187 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
188 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
189 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
190 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
191 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
192 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
193 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
194 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
195 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
196 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
197 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
199 // Variable arguments.
200 setOperationAction(ISD::VASTART, MVT::Other, Custom);
201 setOperationAction(ISD::VAARG, MVT::Other, Custom);
202 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
203 setOperationAction(ISD::VAEND, MVT::Other, Expand);
205 // Variable-sized objects.
206 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
207 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
208 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
210 // Exception handling.
211 // FIXME: These are guesses. Has this been defined yet?
212 setExceptionPointerRegister(ARM64::X0);
213 setExceptionSelectorRegister(ARM64::X1);
215 // Constant pool entries
216 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
219 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
221 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
222 setOperationAction(ISD::ADDC, MVT::i32, Custom);
223 setOperationAction(ISD::ADDE, MVT::i32, Custom);
224 setOperationAction(ISD::SUBC, MVT::i32, Custom);
225 setOperationAction(ISD::SUBE, MVT::i32, Custom);
226 setOperationAction(ISD::ADDC, MVT::i64, Custom);
227 setOperationAction(ISD::ADDE, MVT::i64, Custom);
228 setOperationAction(ISD::SUBC, MVT::i64, Custom);
229 setOperationAction(ISD::SUBE, MVT::i64, Custom);
231 // ARM64 lacks both left-rotate and popcount instructions.
232 setOperationAction(ISD::ROTL, MVT::i32, Expand);
233 setOperationAction(ISD::ROTL, MVT::i64, Expand);
235 // ARM64 doesn't have {U|S}MUL_LOHI.
236 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
237 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
240 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
241 // counterparts, which ARM64 supports directly.
242 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
243 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
244 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
245 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
247 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
248 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
250 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
251 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
252 setOperationAction(ISD::SREM, MVT::i32, Expand);
253 setOperationAction(ISD::SREM, MVT::i64, Expand);
254 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
255 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
256 setOperationAction(ISD::UREM, MVT::i32, Expand);
257 setOperationAction(ISD::UREM, MVT::i64, Expand);
259 // Custom lower Add/Sub/Mul with overflow.
260 setOperationAction(ISD::SADDO, MVT::i32, Custom);
261 setOperationAction(ISD::SADDO, MVT::i64, Custom);
262 setOperationAction(ISD::UADDO, MVT::i32, Custom);
263 setOperationAction(ISD::UADDO, MVT::i64, Custom);
264 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
265 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
266 setOperationAction(ISD::USUBO, MVT::i32, Custom);
267 setOperationAction(ISD::USUBO, MVT::i64, Custom);
268 setOperationAction(ISD::SMULO, MVT::i32, Custom);
269 setOperationAction(ISD::SMULO, MVT::i64, Custom);
270 setOperationAction(ISD::UMULO, MVT::i32, Custom);
271 setOperationAction(ISD::UMULO, MVT::i64, Custom);
273 setOperationAction(ISD::FSIN, MVT::f32, Expand);
274 setOperationAction(ISD::FSIN, MVT::f64, Expand);
275 setOperationAction(ISD::FCOS, MVT::f32, Expand);
276 setOperationAction(ISD::FCOS, MVT::f64, Expand);
277 setOperationAction(ISD::FPOW, MVT::f32, Expand);
278 setOperationAction(ISD::FPOW, MVT::f64, Expand);
279 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
280 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
282 // ARM64 has implementations of a lot of rounding-like FP operations.
283 static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
284 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
285 MVT Ty = RoundingTypes[I];
286 setOperationAction(ISD::FFLOOR, Ty, Legal);
287 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
288 setOperationAction(ISD::FCEIL, Ty, Legal);
289 setOperationAction(ISD::FRINT, Ty, Legal);
290 setOperationAction(ISD::FTRUNC, Ty, Legal);
291 setOperationAction(ISD::FROUND, Ty, Legal);
294 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
296 if (Subtarget->isTargetMachO()) {
297 // For iOS, we don't want to the normal expansion of a libcall to
298 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
300 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
301 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
303 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
304 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
307 // ARM64 does not have floating-point extending loads, i1 sign-extending load,
308 // floating-point truncating stores, or v2i32->v2i16 truncating store.
309 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
310 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
311 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
312 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
313 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
314 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
315 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
316 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
317 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
318 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
319 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
320 // Indexed loads and stores are supported.
321 for (unsigned im = (unsigned)ISD::PRE_INC;
322 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
323 setIndexedLoadAction(im, MVT::i8, Legal);
324 setIndexedLoadAction(im, MVT::i16, Legal);
325 setIndexedLoadAction(im, MVT::i32, Legal);
326 setIndexedLoadAction(im, MVT::i64, Legal);
327 setIndexedLoadAction(im, MVT::f64, Legal);
328 setIndexedLoadAction(im, MVT::f32, Legal);
329 setIndexedStoreAction(im, MVT::i8, Legal);
330 setIndexedStoreAction(im, MVT::i16, Legal);
331 setIndexedStoreAction(im, MVT::i32, Legal);
332 setIndexedStoreAction(im, MVT::i64, Legal);
333 setIndexedStoreAction(im, MVT::f64, Legal);
334 setIndexedStoreAction(im, MVT::f32, Legal);
338 setOperationAction(ISD::TRAP, MVT::Other, Legal);
340 // We combine OR nodes for bitfield operations.
341 setTargetDAGCombine(ISD::OR);
343 // Vector add and sub nodes may conceal a high-half opportunity.
344 // Also, try to fold ADD into CSINC/CSINV..
345 setTargetDAGCombine(ISD::ADD);
346 setTargetDAGCombine(ISD::SUB);
348 setTargetDAGCombine(ISD::XOR);
349 setTargetDAGCombine(ISD::SINT_TO_FP);
350 setTargetDAGCombine(ISD::UINT_TO_FP);
352 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
354 setTargetDAGCombine(ISD::ANY_EXTEND);
355 setTargetDAGCombine(ISD::ZERO_EXTEND);
356 setTargetDAGCombine(ISD::SIGN_EXTEND);
357 setTargetDAGCombine(ISD::BITCAST);
358 setTargetDAGCombine(ISD::CONCAT_VECTORS);
359 setTargetDAGCombine(ISD::STORE);
361 setTargetDAGCombine(ISD::MUL);
363 setTargetDAGCombine(ISD::SELECT);
364 setTargetDAGCombine(ISD::VSELECT);
366 setTargetDAGCombine(ISD::INTRINSIC_VOID);
367 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
368 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
370 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
371 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
372 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
374 setStackPointerRegisterToSaveRestore(ARM64::SP);
376 setSchedulingPreference(Sched::Hybrid);
379 MaskAndBranchFoldingIsLegal = true;
381 setMinFunctionAlignment(2);
383 RequireStrictAlign = (Align == StrictAlign);
385 setHasExtractBitsInsn(true);
387 if (Subtarget->hasNEON()) {
388 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
389 // silliness like this:
390 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
391 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
392 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
393 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
394 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
395 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
396 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
397 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
398 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
399 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
400 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
401 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
402 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
403 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
404 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
405 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
406 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
407 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
408 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
409 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
410 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
411 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
412 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
413 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
414 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
416 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
417 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
418 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
419 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
420 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
422 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
424 // ARM64 doesn't have a direct vector ->f32 conversion instructions for
425 // elements smaller than i32, so promote the input to i32 first.
426 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
427 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
428 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
429 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
430 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
431 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
432 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
433 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
434 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
436 // ARM64 doesn't have MUL.2d:
437 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
438 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
439 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
440 // Likewise, narrowing and extending vector loads/stores aren't handled
442 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
443 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
445 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
448 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
449 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
450 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
451 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
453 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
455 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
456 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
457 setTruncStoreAction((MVT::SimpleValueType)VT,
458 (MVT::SimpleValueType)InnerVT, Expand);
459 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
460 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
461 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
464 // ARM64 has implementations of a lot of rounding-like FP operations.
465 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
466 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) {
467 MVT Ty = RoundingVecTypes[I];
468 setOperationAction(ISD::FFLOOR, Ty, Legal);
469 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
470 setOperationAction(ISD::FCEIL, Ty, Legal);
471 setOperationAction(ISD::FRINT, Ty, Legal);
472 setOperationAction(ISD::FTRUNC, Ty, Legal);
473 setOperationAction(ISD::FROUND, Ty, Legal);
478 void ARM64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
479 if (VT == MVT::v2f32) {
480 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
481 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
483 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
484 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
485 } else if (VT == MVT::v2f64 || VT == MVT::v4f32) {
486 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
487 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
489 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
490 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
493 // Mark vector float intrinsics as expand.
494 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
495 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
496 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
497 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
498 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
499 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
500 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
501 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
502 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
503 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
506 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
507 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
508 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
509 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
510 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
511 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
512 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
513 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
514 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
515 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
516 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
517 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
519 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
520 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
521 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
522 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
524 // CNT supports only B element sizes.
525 if (VT != MVT::v8i8 && VT != MVT::v16i8)
526 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
528 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
529 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
530 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
531 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
532 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
534 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
535 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
537 if (Subtarget->isLittleEndian()) {
538 for (unsigned im = (unsigned)ISD::PRE_INC;
539 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
540 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
541 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
546 void ARM64TargetLowering::addDRTypeForNEON(MVT VT) {
547 addRegisterClass(VT, &ARM64::FPR64RegClass);
548 addTypeForNEON(VT, MVT::v2i32);
551 void ARM64TargetLowering::addQRTypeForNEON(MVT VT) {
552 addRegisterClass(VT, &ARM64::FPR128RegClass);
553 addTypeForNEON(VT, MVT::v4i32);
556 EVT ARM64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
559 return VT.changeVectorElementTypeToInteger();
562 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
563 /// Mask are known to be either zero or one and return them in the
564 /// KnownZero/KnownOne bitsets.
565 void ARM64TargetLowering::computeKnownBitsForTargetNode(
566 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
567 const SelectionDAG &DAG, unsigned Depth) const {
568 switch (Op.getOpcode()) {
571 case ARM64ISD::CSEL: {
572 APInt KnownZero2, KnownOne2;
573 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
574 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
575 KnownZero &= KnownZero2;
576 KnownOne &= KnownOne2;
579 case ISD::INTRINSIC_W_CHAIN: {
580 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
581 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
584 case Intrinsic::arm64_ldaxr:
585 case Intrinsic::arm64_ldxr: {
586 unsigned BitWidth = KnownOne.getBitWidth();
587 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
588 unsigned MemBits = VT.getScalarType().getSizeInBits();
589 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
595 case ISD::INTRINSIC_WO_CHAIN:
596 case ISD::INTRINSIC_VOID: {
597 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
601 case Intrinsic::arm64_neon_umaxv:
602 case Intrinsic::arm64_neon_uminv: {
603 // Figure out the datatype of the vector operand. The UMINV instruction
604 // will zero extend the result, so we can mark as known zero all the
605 // bits larger than the element datatype. 32-bit or larget doesn't need
606 // this as those are legal types and will be handled by isel directly.
607 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
608 unsigned BitWidth = KnownZero.getBitWidth();
609 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
610 assert(BitWidth >= 8 && "Unexpected width!");
611 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
613 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
614 assert(BitWidth >= 16 && "Unexpected width!");
615 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
625 MVT ARM64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
629 unsigned ARM64TargetLowering::getMaximalGlobalOffset() const {
630 // FIXME: On ARM64, this depends on the type.
631 // Basically, the addressable offsets are o to 4095 * Ty.getSizeInBytes().
632 // and the offset has to be a multiple of the related size in bytes.
637 ARM64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
638 const TargetLibraryInfo *libInfo) const {
639 return ARM64::createFastISel(funcInfo, libInfo);
642 const char *ARM64TargetLowering::getTargetNodeName(unsigned Opcode) const {
646 case ARM64ISD::CALL: return "ARM64ISD::CALL";
647 case ARM64ISD::ADRP: return "ARM64ISD::ADRP";
648 case ARM64ISD::ADDlow: return "ARM64ISD::ADDlow";
649 case ARM64ISD::LOADgot: return "ARM64ISD::LOADgot";
650 case ARM64ISD::RET_FLAG: return "ARM64ISD::RET_FLAG";
651 case ARM64ISD::BRCOND: return "ARM64ISD::BRCOND";
652 case ARM64ISD::CSEL: return "ARM64ISD::CSEL";
653 case ARM64ISD::FCSEL: return "ARM64ISD::FCSEL";
654 case ARM64ISD::CSINV: return "ARM64ISD::CSINV";
655 case ARM64ISD::CSNEG: return "ARM64ISD::CSNEG";
656 case ARM64ISD::CSINC: return "ARM64ISD::CSINC";
657 case ARM64ISD::THREAD_POINTER: return "ARM64ISD::THREAD_POINTER";
658 case ARM64ISD::TLSDESC_CALL: return "ARM64ISD::TLSDESC_CALL";
659 case ARM64ISD::ADC: return "ARM64ISD::ADC";
660 case ARM64ISD::SBC: return "ARM64ISD::SBC";
661 case ARM64ISD::ADDS: return "ARM64ISD::ADDS";
662 case ARM64ISD::SUBS: return "ARM64ISD::SUBS";
663 case ARM64ISD::ADCS: return "ARM64ISD::ADCS";
664 case ARM64ISD::SBCS: return "ARM64ISD::SBCS";
665 case ARM64ISD::ANDS: return "ARM64ISD::ANDS";
666 case ARM64ISD::FCMP: return "ARM64ISD::FCMP";
667 case ARM64ISD::FMIN: return "ARM64ISD::FMIN";
668 case ARM64ISD::FMAX: return "ARM64ISD::FMAX";
669 case ARM64ISD::DUP: return "ARM64ISD::DUP";
670 case ARM64ISD::DUPLANE8: return "ARM64ISD::DUPLANE8";
671 case ARM64ISD::DUPLANE16: return "ARM64ISD::DUPLANE16";
672 case ARM64ISD::DUPLANE32: return "ARM64ISD::DUPLANE32";
673 case ARM64ISD::DUPLANE64: return "ARM64ISD::DUPLANE64";
674 case ARM64ISD::MOVI: return "ARM64ISD::MOVI";
675 case ARM64ISD::MOVIshift: return "ARM64ISD::MOVIshift";
676 case ARM64ISD::MOVIedit: return "ARM64ISD::MOVIedit";
677 case ARM64ISD::MOVImsl: return "ARM64ISD::MOVImsl";
678 case ARM64ISD::FMOV: return "ARM64ISD::FMOV";
679 case ARM64ISD::MVNIshift: return "ARM64ISD::MVNIshift";
680 case ARM64ISD::MVNImsl: return "ARM64ISD::MVNImsl";
681 case ARM64ISD::BICi: return "ARM64ISD::BICi";
682 case ARM64ISD::ORRi: return "ARM64ISD::ORRi";
683 case ARM64ISD::BSL: return "ARM64ISD::BSL";
684 case ARM64ISD::NEG: return "ARM64ISD::NEG";
685 case ARM64ISD::EXTR: return "ARM64ISD::EXTR";
686 case ARM64ISD::ZIP1: return "ARM64ISD::ZIP1";
687 case ARM64ISD::ZIP2: return "ARM64ISD::ZIP2";
688 case ARM64ISD::UZP1: return "ARM64ISD::UZP1";
689 case ARM64ISD::UZP2: return "ARM64ISD::UZP2";
690 case ARM64ISD::TRN1: return "ARM64ISD::TRN1";
691 case ARM64ISD::TRN2: return "ARM64ISD::TRN2";
692 case ARM64ISD::REV16: return "ARM64ISD::REV16";
693 case ARM64ISD::REV32: return "ARM64ISD::REV32";
694 case ARM64ISD::REV64: return "ARM64ISD::REV64";
695 case ARM64ISD::EXT: return "ARM64ISD::EXT";
696 case ARM64ISD::VSHL: return "ARM64ISD::VSHL";
697 case ARM64ISD::VLSHR: return "ARM64ISD::VLSHR";
698 case ARM64ISD::VASHR: return "ARM64ISD::VASHR";
699 case ARM64ISD::CMEQ: return "ARM64ISD::CMEQ";
700 case ARM64ISD::CMGE: return "ARM64ISD::CMGE";
701 case ARM64ISD::CMGT: return "ARM64ISD::CMGT";
702 case ARM64ISD::CMHI: return "ARM64ISD::CMHI";
703 case ARM64ISD::CMHS: return "ARM64ISD::CMHS";
704 case ARM64ISD::FCMEQ: return "ARM64ISD::FCMEQ";
705 case ARM64ISD::FCMGE: return "ARM64ISD::FCMGE";
706 case ARM64ISD::FCMGT: return "ARM64ISD::FCMGT";
707 case ARM64ISD::CMEQz: return "ARM64ISD::CMEQz";
708 case ARM64ISD::CMGEz: return "ARM64ISD::CMGEz";
709 case ARM64ISD::CMGTz: return "ARM64ISD::CMGTz";
710 case ARM64ISD::CMLEz: return "ARM64ISD::CMLEz";
711 case ARM64ISD::CMLTz: return "ARM64ISD::CMLTz";
712 case ARM64ISD::FCMEQz: return "ARM64ISD::FCMEQz";
713 case ARM64ISD::FCMGEz: return "ARM64ISD::FCMGEz";
714 case ARM64ISD::FCMGTz: return "ARM64ISD::FCMGTz";
715 case ARM64ISD::FCMLEz: return "ARM64ISD::FCMLEz";
716 case ARM64ISD::FCMLTz: return "ARM64ISD::FCMLTz";
717 case ARM64ISD::NOT: return "ARM64ISD::NOT";
718 case ARM64ISD::BIT: return "ARM64ISD::BIT";
719 case ARM64ISD::CBZ: return "ARM64ISD::CBZ";
720 case ARM64ISD::CBNZ: return "ARM64ISD::CBNZ";
721 case ARM64ISD::TBZ: return "ARM64ISD::TBZ";
722 case ARM64ISD::TBNZ: return "ARM64ISD::TBNZ";
723 case ARM64ISD::TC_RETURN: return "ARM64ISD::TC_RETURN";
724 case ARM64ISD::SITOF: return "ARM64ISD::SITOF";
725 case ARM64ISD::UITOF: return "ARM64ISD::UITOF";
726 case ARM64ISD::SQSHL_I: return "ARM64ISD::SQSHL_I";
727 case ARM64ISD::UQSHL_I: return "ARM64ISD::UQSHL_I";
728 case ARM64ISD::SRSHR_I: return "ARM64ISD::SRSHR_I";
729 case ARM64ISD::URSHR_I: return "ARM64ISD::URSHR_I";
730 case ARM64ISD::SQSHLU_I: return "ARM64ISD::SQSHLU_I";
731 case ARM64ISD::WrapperLarge: return "ARM64ISD::WrapperLarge";
732 case ARM64ISD::LD2post: return "ARM64ISD::LD2post";
733 case ARM64ISD::LD3post: return "ARM64ISD::LD3post";
734 case ARM64ISD::LD4post: return "ARM64ISD::LD4post";
735 case ARM64ISD::ST2post: return "ARM64ISD::ST2post";
736 case ARM64ISD::ST3post: return "ARM64ISD::ST3post";
737 case ARM64ISD::ST4post: return "ARM64ISD::ST4post";
738 case ARM64ISD::LD1x2post: return "ARM64ISD::LD1x2post";
739 case ARM64ISD::LD1x3post: return "ARM64ISD::LD1x3post";
740 case ARM64ISD::LD1x4post: return "ARM64ISD::LD1x4post";
741 case ARM64ISD::ST1x2post: return "ARM64ISD::ST1x2post";
742 case ARM64ISD::ST1x3post: return "ARM64ISD::ST1x3post";
743 case ARM64ISD::ST1x4post: return "ARM64ISD::ST1x4post";
744 case ARM64ISD::LD1DUPpost: return "ARM64ISD::LD1DUPpost";
745 case ARM64ISD::LD2DUPpost: return "ARM64ISD::LD2DUPpost";
746 case ARM64ISD::LD3DUPpost: return "ARM64ISD::LD3DUPpost";
747 case ARM64ISD::LD4DUPpost: return "ARM64ISD::LD4DUPpost";
748 case ARM64ISD::LD1LANEpost: return "ARM64ISD::LD1LANEpost";
749 case ARM64ISD::LD2LANEpost: return "ARM64ISD::LD2LANEpost";
750 case ARM64ISD::LD3LANEpost: return "ARM64ISD::LD3LANEpost";
751 case ARM64ISD::LD4LANEpost: return "ARM64ISD::LD4LANEpost";
752 case ARM64ISD::ST2LANEpost: return "ARM64ISD::ST2LANEpost";
753 case ARM64ISD::ST3LANEpost: return "ARM64ISD::ST3LANEpost";
754 case ARM64ISD::ST4LANEpost: return "ARM64ISD::ST4LANEpost";
759 ARM64TargetLowering::EmitF128CSEL(MachineInstr *MI,
760 MachineBasicBlock *MBB) const {
761 // We materialise the F128CSEL pseudo-instruction as some control flow and a
765 // [... previous instrs leading to comparison ...]
771 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
773 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
774 MachineFunction *MF = MBB->getParent();
775 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
776 DebugLoc DL = MI->getDebugLoc();
777 MachineFunction::iterator It = MBB;
780 unsigned DestReg = MI->getOperand(0).getReg();
781 unsigned IfTrueReg = MI->getOperand(1).getReg();
782 unsigned IfFalseReg = MI->getOperand(2).getReg();
783 unsigned CondCode = MI->getOperand(3).getImm();
784 bool NZCVKilled = MI->getOperand(4).isKill();
786 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
787 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
788 MF->insert(It, TrueBB);
789 MF->insert(It, EndBB);
791 // Transfer rest of current basic-block to EndBB
792 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
794 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
796 BuildMI(MBB, DL, TII->get(ARM64::Bcc)).addImm(CondCode).addMBB(TrueBB);
797 BuildMI(MBB, DL, TII->get(ARM64::B)).addMBB(EndBB);
798 MBB->addSuccessor(TrueBB);
799 MBB->addSuccessor(EndBB);
801 // TrueBB falls through to the end.
802 TrueBB->addSuccessor(EndBB);
805 TrueBB->addLiveIn(ARM64::NZCV);
806 EndBB->addLiveIn(ARM64::NZCV);
809 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(ARM64::PHI), DestReg)
815 MI->eraseFromParent();
820 ARM64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
821 MachineBasicBlock *BB) const {
822 switch (MI->getOpcode()) {
827 assert(0 && "Unexpected instruction for custom inserter!");
830 case ARM64::F128CSEL:
831 return EmitF128CSEL(MI, BB);
833 case TargetOpcode::STACKMAP:
834 case TargetOpcode::PATCHPOINT:
835 return emitPatchPoint(MI, BB);
837 llvm_unreachable("Unexpected instruction for custom inserter!");
840 //===----------------------------------------------------------------------===//
841 // ARM64 Lowering private implementation.
842 //===----------------------------------------------------------------------===//
844 //===----------------------------------------------------------------------===//
846 //===----------------------------------------------------------------------===//
848 /// changeIntCCToARM64CC - Convert a DAG integer condition code to an ARM64 CC
849 static ARM64CC::CondCode changeIntCCToARM64CC(ISD::CondCode CC) {
852 llvm_unreachable("Unknown condition code!");
876 /// changeFPCCToARM64CC - Convert a DAG fp condition code to an ARM64 CC.
877 static void changeFPCCToARM64CC(ISD::CondCode CC, ARM64CC::CondCode &CondCode,
878 ARM64CC::CondCode &CondCode2) {
879 CondCode2 = ARM64CC::AL;
882 llvm_unreachable("Unknown FP condition!");
885 CondCode = ARM64CC::EQ;
889 CondCode = ARM64CC::GT;
893 CondCode = ARM64CC::GE;
896 CondCode = ARM64CC::MI;
899 CondCode = ARM64CC::LS;
902 CondCode = ARM64CC::MI;
903 CondCode2 = ARM64CC::GT;
906 CondCode = ARM64CC::VC;
909 CondCode = ARM64CC::VS;
912 CondCode = ARM64CC::EQ;
913 CondCode2 = ARM64CC::VS;
916 CondCode = ARM64CC::HI;
919 CondCode = ARM64CC::PL;
923 CondCode = ARM64CC::LT;
927 CondCode = ARM64CC::LE;
931 CondCode = ARM64CC::NE;
936 /// changeVectorFPCCToARM64CC - Convert a DAG fp condition code to an ARM64 CC
937 /// usable with the vector instructions. Fewer operations are available without
938 /// a real NZCV register, so we have to use less efficient combinations to get
940 static void changeVectorFPCCToARM64CC(ISD::CondCode CC,
941 ARM64CC::CondCode &CondCode,
942 ARM64CC::CondCode &CondCode2,
947 // Mostly the scalar mappings work fine.
948 changeFPCCToARM64CC(CC, CondCode, CondCode2);
951 Invert = true; // Fallthrough
953 CondCode = ARM64CC::MI;
954 CondCode2 = ARM64CC::GE;
961 // All of the compare-mask comparisons are ordered, but we can switch
962 // between the two by a double inversion. E.g. ULE == !OGT.
964 changeFPCCToARM64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
969 static bool isLegalArithImmed(uint64_t C) {
970 // Matches ARM64DAGToDAGISel::SelectArithImmed().
971 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
974 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
975 SDLoc dl, SelectionDAG &DAG) {
976 EVT VT = LHS.getValueType();
978 if (VT.isFloatingPoint())
979 return DAG.getNode(ARM64ISD::FCMP, dl, VT, LHS, RHS);
981 // The CMP instruction is just an alias for SUBS, and representing it as
982 // SUBS means that it's possible to get CSE with subtract operations.
983 // A later phase can perform the optimization of setting the destination
984 // register to WZR/XZR if it ends up being unused.
985 unsigned Opcode = ARM64ISD::SUBS;
987 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
988 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
989 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
990 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
991 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
992 // can be set differently by this operation. It comes down to whether
993 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
994 // everything is fine. If not then the optimization is wrong. Thus general
995 // comparisons are only valid if op2 != 0.
997 // So, finally, the only LLVM-native comparisons that don't mention C and V
998 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
999 // the absence of information about op2.
1000 Opcode = ARM64ISD::ADDS;
1001 RHS = RHS.getOperand(1);
1002 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1003 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1004 !isUnsignedIntSetCC(CC)) {
1005 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1006 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1007 // of the signed comparisons.
1008 Opcode = ARM64ISD::ANDS;
1009 RHS = LHS.getOperand(1);
1010 LHS = LHS.getOperand(0);
1013 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1017 static SDValue getARM64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1018 SDValue &ARM64cc, SelectionDAG &DAG, SDLoc dl) {
1019 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1020 EVT VT = RHS.getValueType();
1021 uint64_t C = RHSC->getZExtValue();
1022 if (!isLegalArithImmed(C)) {
1023 // Constant does not fit, try adjusting it by one?
1029 if ((VT == MVT::i32 && C != 0x80000000 &&
1030 isLegalArithImmed((uint32_t)(C - 1))) ||
1031 (VT == MVT::i64 && C != 0x80000000ULL &&
1032 isLegalArithImmed(C - 1ULL))) {
1033 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1034 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1035 RHS = DAG.getConstant(C, VT);
1040 if ((VT == MVT::i32 && C != 0 &&
1041 isLegalArithImmed((uint32_t)(C - 1))) ||
1042 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1043 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1044 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1045 RHS = DAG.getConstant(C, VT);
1050 if ((VT == MVT::i32 && C != 0x7fffffff &&
1051 isLegalArithImmed((uint32_t)(C + 1))) ||
1052 (VT == MVT::i64 && C != 0x7ffffffffffffffULL &&
1053 isLegalArithImmed(C + 1ULL))) {
1054 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1055 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1056 RHS = DAG.getConstant(C, VT);
1061 if ((VT == MVT::i32 && C != 0xffffffff &&
1062 isLegalArithImmed((uint32_t)(C + 1))) ||
1063 (VT == MVT::i64 && C != 0xfffffffffffffffULL &&
1064 isLegalArithImmed(C + 1ULL))) {
1065 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1066 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1067 RHS = DAG.getConstant(C, VT);
1074 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1075 ARM64CC::CondCode ARM64CC = changeIntCCToARM64CC(CC);
1076 ARM64cc = DAG.getConstant(ARM64CC, MVT::i32);
1080 static std::pair<SDValue, SDValue>
1081 getARM64XALUOOp(ARM64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1082 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1083 "Unsupported value type");
1084 SDValue Value, Overflow;
1086 SDValue LHS = Op.getOperand(0);
1087 SDValue RHS = Op.getOperand(1);
1089 switch (Op.getOpcode()) {
1091 llvm_unreachable("Unknown overflow instruction!");
1093 Opc = ARM64ISD::ADDS;
1097 Opc = ARM64ISD::ADDS;
1101 Opc = ARM64ISD::SUBS;
1105 Opc = ARM64ISD::SUBS;
1108 // Multiply needs a little bit extra work.
1112 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
1113 if (Op.getValueType() == MVT::i32) {
1114 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1115 // For a 32 bit multiply with overflow check we want the instruction
1116 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1117 // need to generate the following pattern:
1118 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1119 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1120 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1121 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1122 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1123 DAG.getConstant(0, MVT::i64));
1124 // On ARM64 the upper 32 bits are always zero extended for a 32 bit
1125 // operation. We need to clear out the upper 32 bits, because we used a
1126 // widening multiply that wrote all 64 bits. In the end this should be a
1128 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1130 // The signed overflow check requires more than just a simple check for
1131 // any bit set in the upper 32 bits of the result. These bits could be
1132 // just the sign bits of a negative number. To perform the overflow
1133 // check we have to arithmetic shift right the 32nd bit of the result by
1134 // 31 bits. Then we compare the result to the upper 32 bits.
1135 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1136 DAG.getConstant(32, MVT::i64));
1137 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1138 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1139 DAG.getConstant(31, MVT::i64));
1140 // It is important that LowerBits is last, otherwise the arithmetic
1141 // shift will not be folded into the compare (SUBS).
1142 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1143 Overflow = DAG.getNode(ARM64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1146 // The overflow check for unsigned multiply is easy. We only need to
1147 // check if any of the upper 32 bits are set. This can be done with a
1148 // CMP (shifted register). For that we need to generate the following
1150 // (i64 ARM64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1151 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1152 DAG.getConstant(32, MVT::i64));
1153 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1155 DAG.getNode(ARM64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1156 UpperBits).getValue(1);
1160 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1161 // For the 64 bit multiply
1162 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1164 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1165 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1166 DAG.getConstant(63, MVT::i64));
1167 // It is important that LowerBits is last, otherwise the arithmetic
1168 // shift will not be folded into the compare (SUBS).
1169 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1170 Overflow = DAG.getNode(ARM64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1173 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1174 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1176 DAG.getNode(ARM64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1177 UpperBits).getValue(1);
1184 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1186 // Emit the ARM64 operation with overflow check.
1187 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1188 Overflow = Value.getValue(1);
1190 return std::make_pair(Value, Overflow);
1193 SDValue ARM64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1194 RTLIB::Libcall Call) const {
1195 SmallVector<SDValue, 2> Ops;
1196 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1197 Ops.push_back(Op.getOperand(i));
1199 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1203 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1204 SDValue Sel = Op.getOperand(0);
1205 SDValue Other = Op.getOperand(1);
1207 // If neither operand is a SELECT_CC, give up.
1208 if (Sel.getOpcode() != ISD::SELECT_CC)
1209 std::swap(Sel, Other);
1210 if (Sel.getOpcode() != ISD::SELECT_CC)
1213 // The folding we want to perform is:
1214 // (xor x, (select_cc a, b, cc, 0, -1) )
1216 // (csel x, (xor x, -1), cc ...)
1218 // The latter will get matched to a CSINV instruction.
1220 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1221 SDValue LHS = Sel.getOperand(0);
1222 SDValue RHS = Sel.getOperand(1);
1223 SDValue TVal = Sel.getOperand(2);
1224 SDValue FVal = Sel.getOperand(3);
1227 // FIXME: This could be generalized to non-integer comparisons.
1228 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1231 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1232 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1234 // The the values aren't constants, this isn't the pattern we're looking for.
1235 if (!CFVal || !CTVal)
1238 // We can commute the SELECT_CC by inverting the condition. This
1239 // might be needed to make this fit into a CSINV pattern.
1240 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1241 std::swap(TVal, FVal);
1242 std::swap(CTVal, CFVal);
1243 CC = ISD::getSetCCInverse(CC, true);
1246 // If the constants line up, perform the transform!
1247 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1249 SDValue Cmp = getARM64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1252 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1253 DAG.getConstant(-1ULL, Other.getValueType()));
1255 return DAG.getNode(ARM64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1262 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1263 EVT VT = Op.getValueType();
1265 // Let legalize expand this if it isn't a legal type yet.
1266 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1269 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1272 bool ExtraOp = false;
1273 switch (Op.getOpcode()) {
1275 assert(0 && "Invalid code");
1277 Opc = ARM64ISD::ADDS;
1280 Opc = ARM64ISD::SUBS;
1283 Opc = ARM64ISD::ADCS;
1287 Opc = ARM64ISD::SBCS;
1293 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1294 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1298 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1299 // Let legalize expand this if it isn't a legal type yet.
1300 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1303 ARM64CC::CondCode CC;
1304 // The actual operation that sets the overflow or carry flag.
1305 SDValue Value, Overflow;
1306 std::tie(Value, Overflow) = getARM64XALUOOp(CC, Op, DAG);
1308 // We use 0 and 1 as false and true values.
1309 SDValue TVal = DAG.getConstant(1, MVT::i32);
1310 SDValue FVal = DAG.getConstant(0, MVT::i32);
1312 // We use an inverted condition, because the conditional select is inverted
1313 // too. This will allow it to be selected to a single instruction:
1314 // CSINC Wd, WZR, WZR, invert(cond).
1315 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1316 Overflow = DAG.getNode(ARM64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal, CCVal,
1319 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1320 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1323 // Prefetch operands are:
1324 // 1: Address to prefetch
1326 // 3: int locality (0 = no locality ... 3 = extreme locality)
1327 // 4: bool isDataCache
1328 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1330 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1331 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1332 // The data thing is not used.
1333 // unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1335 bool IsStream = !Locality;
1336 // When the locality number is set
1338 // The front-end should have filtered out the out-of-range values
1339 assert(Locality <= 3 && "Prefetch locality out-of-range");
1340 // The locality degree is the opposite of the cache speed.
1341 // Put the number the other way around.
1342 // The encoding starts at 0 for level 1
1343 Locality = 3 - Locality;
1346 // built the mask value encoding the expected behavior.
1347 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1348 (Locality << 1) | // Cache level bits
1349 (unsigned)IsStream; // Stream bit
1350 return DAG.getNode(ARM64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1351 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1354 SDValue ARM64TargetLowering::LowerFP_EXTEND(SDValue Op,
1355 SelectionDAG &DAG) const {
1356 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1359 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1361 return LowerF128Call(Op, DAG, LC);
1364 SDValue ARM64TargetLowering::LowerFP_ROUND(SDValue Op,
1365 SelectionDAG &DAG) const {
1366 if (Op.getOperand(0).getValueType() != MVT::f128) {
1367 // It's legal except when f128 is involved
1372 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1374 // FP_ROUND node has a second operand indicating whether it is known to be
1375 // precise. That doesn't take part in the LibCall so we can't directly use
1377 SDValue SrcVal = Op.getOperand(0);
1378 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1379 /*isSigned*/ false, SDLoc(Op)).first;
1382 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1383 // Warning: We maintain cost tables in ARM64TargetTransformInfo.cpp.
1384 // Any additional optimization in this function should be recorded
1385 // in the cost tables.
1386 EVT InVT = Op.getOperand(0).getValueType();
1387 EVT VT = Op.getValueType();
1389 // FP_TO_XINT conversion from the same type are legal.
1390 if (VT.getSizeInBits() == InVT.getSizeInBits())
1393 if (InVT == MVT::v2f64 || InVT == MVT::v4f32) {
1396 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1398 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1399 } else if (InVT == MVT::v2f32) {
1401 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, Op.getOperand(0));
1402 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1405 // Type changing conversions are illegal.
1409 SDValue ARM64TargetLowering::LowerFP_TO_INT(SDValue Op,
1410 SelectionDAG &DAG) const {
1411 if (Op.getOperand(0).getValueType().isVector())
1412 return LowerVectorFP_TO_INT(Op, DAG);
1414 if (Op.getOperand(0).getValueType() != MVT::f128) {
1415 // It's legal except when f128 is involved
1420 if (Op.getOpcode() == ISD::FP_TO_SINT)
1421 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1423 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1425 SmallVector<SDValue, 2> Ops;
1426 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1427 Ops.push_back(Op.getOperand(i));
1429 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1433 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1434 // Warning: We maintain cost tables in ARM64TargetTransformInfo.cpp.
1435 // Any additional optimization in this function should be recorded
1436 // in the cost tables.
1437 EVT VT = Op.getValueType();
1439 SDValue In = Op.getOperand(0);
1440 EVT InVT = In.getValueType();
1442 // v2i32 to v2f32 is legal.
1443 if (VT == MVT::v2f32 && InVT == MVT::v2i32)
1446 // This function only handles v2f64 outputs.
1447 if (VT == MVT::v2f64) {
1448 // Extend the input argument to a v2i64 that we can feed into the
1449 // floating point conversion. Zero or sign extend based on whether
1450 // we're doing a signed or unsigned float conversion.
1452 Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
1453 assert(Op.getNumOperands() == 1 && "FP conversions take one argument");
1454 SDValue Promoted = DAG.getNode(Opc, dl, MVT::v2i64, Op.getOperand(0));
1455 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Promoted);
1458 // Scalarize v2i64 to v2f32 conversions.
1459 std::vector<SDValue> BuildVectorOps;
1460 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
1461 SDValue Sclr = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, In,
1462 DAG.getConstant(i, MVT::i64));
1463 Sclr = DAG.getNode(Op->getOpcode(), dl, MVT::f32, Sclr);
1464 BuildVectorOps.push_back(Sclr);
1467 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, BuildVectorOps);
1470 SDValue ARM64TargetLowering::LowerINT_TO_FP(SDValue Op,
1471 SelectionDAG &DAG) const {
1472 if (Op.getValueType().isVector())
1473 return LowerVectorINT_TO_FP(Op, DAG);
1475 // i128 conversions are libcalls.
1476 if (Op.getOperand(0).getValueType() == MVT::i128)
1479 // Other conversions are legal, unless it's to the completely software-based
1481 if (Op.getValueType() != MVT::f128)
1485 if (Op.getOpcode() == ISD::SINT_TO_FP)
1486 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1488 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1490 return LowerF128Call(Op, DAG, LC);
1493 SDValue ARM64TargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
1494 // For iOS, we want to call an alternative entry point: __sincos_stret,
1495 // which returns the values in two S / D registers.
1497 SDValue Arg = Op.getOperand(0);
1498 EVT ArgVT = Arg.getValueType();
1499 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1506 Entry.isSExt = false;
1507 Entry.isZExt = false;
1508 Args.push_back(Entry);
1510 const char *LibcallName =
1511 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1512 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1514 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
1515 TargetLowering::CallLoweringInfo CLI(DAG);
1516 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1517 .setCallee(CallingConv::Fast, RetTy, Callee, &Args, 0);
1519 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1520 return CallResult.first;
1523 SDValue ARM64TargetLowering::LowerOperation(SDValue Op,
1524 SelectionDAG &DAG) const {
1525 switch (Op.getOpcode()) {
1527 llvm_unreachable("unimplemented operand");
1529 case ISD::GlobalAddress:
1530 return LowerGlobalAddress(Op, DAG);
1531 case ISD::GlobalTLSAddress:
1532 return LowerGlobalTLSAddress(Op, DAG);
1534 return LowerSETCC(Op, DAG);
1536 return LowerBR_CC(Op, DAG);
1538 return LowerSELECT(Op, DAG);
1539 case ISD::SELECT_CC:
1540 return LowerSELECT_CC(Op, DAG);
1541 case ISD::JumpTable:
1542 return LowerJumpTable(Op, DAG);
1543 case ISD::ConstantPool:
1544 return LowerConstantPool(Op, DAG);
1545 case ISD::BlockAddress:
1546 return LowerBlockAddress(Op, DAG);
1548 return LowerVASTART(Op, DAG);
1550 return LowerVACOPY(Op, DAG);
1552 return LowerVAARG(Op, DAG);
1557 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1564 return LowerXALUO(Op, DAG);
1566 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1568 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1570 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1572 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1574 return LowerFP_ROUND(Op, DAG);
1575 case ISD::FP_EXTEND:
1576 return LowerFP_EXTEND(Op, DAG);
1577 case ISD::FRAMEADDR:
1578 return LowerFRAMEADDR(Op, DAG);
1579 case ISD::RETURNADDR:
1580 return LowerRETURNADDR(Op, DAG);
1581 case ISD::INSERT_VECTOR_ELT:
1582 return LowerINSERT_VECTOR_ELT(Op, DAG);
1583 case ISD::EXTRACT_VECTOR_ELT:
1584 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1585 case ISD::BUILD_VECTOR:
1586 return LowerBUILD_VECTOR(Op, DAG);
1587 case ISD::VECTOR_SHUFFLE:
1588 return LowerVECTOR_SHUFFLE(Op, DAG);
1589 case ISD::EXTRACT_SUBVECTOR:
1590 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1594 return LowerVectorSRA_SRL_SHL(Op, DAG);
1595 case ISD::SHL_PARTS:
1596 return LowerShiftLeftParts(Op, DAG);
1597 case ISD::SRL_PARTS:
1598 case ISD::SRA_PARTS:
1599 return LowerShiftRightParts(Op, DAG);
1601 return LowerCTPOP(Op, DAG);
1602 case ISD::FCOPYSIGN:
1603 return LowerFCOPYSIGN(Op, DAG);
1605 return LowerVectorAND(Op, DAG);
1607 return LowerVectorOR(Op, DAG);
1609 return LowerXOR(Op, DAG);
1611 return LowerPREFETCH(Op, DAG);
1612 case ISD::SINT_TO_FP:
1613 case ISD::UINT_TO_FP:
1614 return LowerINT_TO_FP(Op, DAG);
1615 case ISD::FP_TO_SINT:
1616 case ISD::FP_TO_UINT:
1617 return LowerFP_TO_INT(Op, DAG);
1619 return LowerFSINCOS(Op, DAG);
1623 /// getFunctionAlignment - Return the Log2 alignment of this function.
1624 unsigned ARM64TargetLowering::getFunctionAlignment(const Function *F) const {
1628 //===----------------------------------------------------------------------===//
1629 // Calling Convention Implementation
1630 //===----------------------------------------------------------------------===//
1632 #include "ARM64GenCallingConv.inc"
1634 /// Selects the correct CCAssignFn for a the given CallingConvention
1636 CCAssignFn *ARM64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1637 bool IsVarArg) const {
1640 llvm_unreachable("Unsupported calling convention.");
1641 case CallingConv::WebKit_JS:
1642 return CC_ARM64_WebKit_JS;
1643 case CallingConv::C:
1644 case CallingConv::Fast:
1645 if (!Subtarget->isTargetDarwin())
1646 return CC_ARM64_AAPCS;
1647 return IsVarArg ? CC_ARM64_DarwinPCS_VarArg : CC_ARM64_DarwinPCS;
1651 SDValue ARM64TargetLowering::LowerFormalArguments(
1652 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1653 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1654 SmallVectorImpl<SDValue> &InVals) const {
1655 MachineFunction &MF = DAG.getMachineFunction();
1656 MachineFrameInfo *MFI = MF.getFrameInfo();
1658 // Assign locations to all of the incoming arguments.
1659 SmallVector<CCValAssign, 16> ArgLocs;
1660 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1661 getTargetMachine(), ArgLocs, *DAG.getContext());
1663 // At this point, Ins[].VT may already be promoted to i32. To correctly
1664 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
1665 // i8 to CC_ARM64_AAPCS with i32 being ValVT and i8 being LocVT.
1666 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
1667 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
1669 unsigned NumArgs = Ins.size();
1670 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
1671 unsigned CurArgIdx = 0;
1672 for (unsigned i = 0; i != NumArgs; ++i) {
1673 MVT ValVT = Ins[i].VT;
1674 std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx);
1675 CurArgIdx = Ins[i].OrigArgIndex;
1677 // Get type of the original argument.
1678 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
1679 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
1680 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
1682 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
1684 else if (ActualMVT == MVT::i16)
1687 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
1689 AssignFn(i, ValVT, LocVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
1690 assert(!Res && "Call operand has unhandled type");
1693 assert(ArgLocs.size() == Ins.size());
1694 SmallVector<SDValue, 16> ArgValues;
1695 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1696 CCValAssign &VA = ArgLocs[i];
1698 if (Ins[i].Flags.isByVal()) {
1699 // Byval is used for HFAs in the PCS, but the system should work in a
1700 // non-compliant manner for larger structs.
1701 EVT PtrTy = getPointerTy();
1702 int Size = Ins[i].Flags.getByValSize();
1703 unsigned NumRegs = (Size + 7) / 8;
1705 // FIXME: This works on big-endian for composite byvals, which are the common
1706 // case. It should also work for fundamental types too.
1708 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
1709 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
1710 InVals.push_back(FrameIdxN);
1713 } if (VA.isRegLoc()) {
1714 // Arguments stored in registers.
1715 EVT RegVT = VA.getLocVT();
1718 const TargetRegisterClass *RC;
1720 if (RegVT == MVT::i32)
1721 RC = &ARM64::GPR32RegClass;
1722 else if (RegVT == MVT::i64)
1723 RC = &ARM64::GPR64RegClass;
1724 else if (RegVT == MVT::f32)
1725 RC = &ARM64::FPR32RegClass;
1726 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
1727 RC = &ARM64::FPR64RegClass;
1728 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
1729 RC = &ARM64::FPR128RegClass;
1731 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1733 // Transform the arguments in physical registers into virtual ones.
1734 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1735 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
1737 // If this is an 8, 16 or 32-bit value, it is really passed promoted
1738 // to 64 bits. Insert an assert[sz]ext to capture this, then
1739 // truncate to the right size.
1740 switch (VA.getLocInfo()) {
1742 llvm_unreachable("Unknown loc info!");
1743 case CCValAssign::Full:
1745 case CCValAssign::BCvt:
1746 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
1748 case CCValAssign::SExt:
1749 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
1750 DAG.getValueType(VA.getValVT()));
1751 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
1753 case CCValAssign::ZExt:
1754 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
1755 DAG.getValueType(VA.getValVT()));
1756 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
1760 InVals.push_back(ArgValue);
1762 } else { // VA.isRegLoc()
1763 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
1764 unsigned ArgOffset = VA.getLocMemOffset();
1765 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1767 uint32_t BEAlign = 0;
1768 if (ArgSize < 8 && !Subtarget->isLittleEndian())
1769 BEAlign = 8 - ArgSize;
1771 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
1773 // Create load nodes to retrieve arguments from the stack.
1774 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1777 // If the loc type and val type are not the same, create an anyext load.
1778 if (VA.getLocVT().getSizeInBits() != VA.getValVT().getSizeInBits()) {
1779 // We should only get here if this is a pure integer.
1780 assert(!VA.getValVT().isVector() && VA.getValVT().isInteger() &&
1781 "Only integer extension supported!");
1782 ArgValue = DAG.getExtLoad(ISD::EXTLOAD, DL, VA.getValVT(), Chain, FIN,
1783 MachinePointerInfo::getFixedStack(FI),
1785 false, false, false, 0);
1787 ArgValue = DAG.getLoad(VA.getValVT(), DL, Chain, FIN,
1788 MachinePointerInfo::getFixedStack(FI), false,
1792 InVals.push_back(ArgValue);
1798 if (!Subtarget->isTargetDarwin()) {
1799 // The AAPCS variadic function ABI is identical to the non-variadic
1800 // one. As a result there may be more arguments in registers and we should
1801 // save them for future reference.
1802 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
1805 ARM64FunctionInfo *AFI = MF.getInfo<ARM64FunctionInfo>();
1806 // This will point to the next argument passed via stack.
1807 unsigned StackOffset = CCInfo.getNextStackOffset();
1808 // We currently pass all varargs at 8-byte alignment.
1809 StackOffset = ((StackOffset + 7) & ~7);
1810 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
1813 ARM64FunctionInfo *FuncInfo = MF.getInfo<ARM64FunctionInfo>();
1814 unsigned StackArgSize = CCInfo.getNextStackOffset();
1815 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1816 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
1817 // This is a non-standard ABI so by fiat I say we're allowed to make full
1818 // use of the stack area to be popped, which must be aligned to 16 bytes in
1820 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
1822 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
1823 // a multiple of 16.
1824 FuncInfo->setArgumentStackToRestore(StackArgSize);
1826 // This realignment carries over to the available bytes below. Our own
1827 // callers will guarantee the space is free by giving an aligned value to
1830 // Even if we're not expected to free up the space, it's useful to know how
1831 // much is there while considering tail calls (because we can reuse it).
1832 FuncInfo->setBytesInStackArgArea(StackArgSize);
1837 void ARM64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
1838 SelectionDAG &DAG, SDLoc DL,
1839 SDValue &Chain) const {
1840 MachineFunction &MF = DAG.getMachineFunction();
1841 MachineFrameInfo *MFI = MF.getFrameInfo();
1842 ARM64FunctionInfo *FuncInfo = MF.getInfo<ARM64FunctionInfo>();
1844 SmallVector<SDValue, 8> MemOps;
1846 static const MCPhysReg GPRArgRegs[] = { ARM64::X0, ARM64::X1, ARM64::X2,
1847 ARM64::X3, ARM64::X4, ARM64::X5,
1848 ARM64::X6, ARM64::X7 };
1849 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
1850 unsigned FirstVariadicGPR =
1851 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs);
1853 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
1855 if (GPRSaveSize != 0) {
1856 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
1858 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
1860 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
1861 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &ARM64::GPR64RegClass);
1862 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
1864 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1865 MachinePointerInfo::getStack(i * 8), false, false, 0);
1866 MemOps.push_back(Store);
1867 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1868 DAG.getConstant(8, getPointerTy()));
1871 FuncInfo->setVarArgsGPRIndex(GPRIdx);
1872 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
1874 if (Subtarget->hasFPARMv8()) {
1875 static const MCPhysReg FPRArgRegs[] = { ARM64::Q0, ARM64::Q1, ARM64::Q2,
1876 ARM64::Q3, ARM64::Q4, ARM64::Q5,
1877 ARM64::Q6, ARM64::Q7 };
1878 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
1879 unsigned FirstVariadicFPR =
1880 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs);
1882 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
1884 if (FPRSaveSize != 0) {
1885 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
1887 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
1889 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
1890 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &ARM64::FPR128RegClass);
1891 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
1894 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1895 MachinePointerInfo::getStack(i * 16), false, false, 0);
1896 MemOps.push_back(Store);
1897 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1898 DAG.getConstant(16, getPointerTy()));
1901 FuncInfo->setVarArgsFPRIndex(FPRIdx);
1902 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
1905 if (!MemOps.empty()) {
1906 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
1910 /// LowerCallResult - Lower the result values of a call into the
1911 /// appropriate copies out of appropriate physical registers.
1912 SDValue ARM64TargetLowering::LowerCallResult(
1913 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1914 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1915 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1916 SDValue ThisVal) const {
1917 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS ? RetCC_ARM64_WebKit_JS
1918 : RetCC_ARM64_AAPCS;
1919 // Assign locations to each value returned by this call.
1920 SmallVector<CCValAssign, 16> RVLocs;
1921 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1922 getTargetMachine(), RVLocs, *DAG.getContext());
1923 CCInfo.AnalyzeCallResult(Ins, RetCC);
1925 // Copy all of the result registers out of their specified physreg.
1926 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1927 CCValAssign VA = RVLocs[i];
1929 // Pass 'this' value directly from the argument to return value, to avoid
1930 // reg unit interference
1931 if (i == 0 && isThisReturn) {
1932 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
1933 "unexpected return calling convention register assignment");
1934 InVals.push_back(ThisVal);
1939 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
1940 Chain = Val.getValue(1);
1941 InFlag = Val.getValue(2);
1943 switch (VA.getLocInfo()) {
1945 llvm_unreachable("Unknown loc info!");
1946 case CCValAssign::Full:
1948 case CCValAssign::BCvt:
1949 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
1953 InVals.push_back(Val);
1959 bool ARM64TargetLowering::isEligibleForTailCallOptimization(
1960 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
1961 bool isCalleeStructRet, bool isCallerStructRet,
1962 const SmallVectorImpl<ISD::OutputArg> &Outs,
1963 const SmallVectorImpl<SDValue> &OutVals,
1964 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
1965 // For CallingConv::C this function knows whether the ABI needs
1966 // changing. That's not true for other conventions so they will have to opt in
1968 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1971 const MachineFunction &MF = DAG.getMachineFunction();
1972 const Function *CallerF = MF.getFunction();
1973 CallingConv::ID CallerCC = CallerF->getCallingConv();
1974 bool CCMatch = CallerCC == CalleeCC;
1976 // Byval parameters hand the function a pointer directly into the stack area
1977 // we want to reuse during a tail call. Working around this *is* possible (see
1978 // X86) but less efficient and uglier in LowerCall.
1979 for (Function::const_arg_iterator i = CallerF->arg_begin(),
1980 e = CallerF->arg_end();
1982 if (i->hasByValAttr())
1985 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
1986 if (IsTailCallConvention(CalleeCC) && CCMatch)
1991 // Now we search for cases where we can use a tail call without changing the
1992 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
1995 // I want anyone implementing a new calling convention to think long and hard
1996 // about this assert.
1997 assert((!isVarArg || CalleeCC == CallingConv::C) &&
1998 "Unexpected variadic calling convention");
2000 if (isVarArg && !Outs.empty()) {
2001 // At least two cases here: if caller is fastcc then we can't have any
2002 // memory arguments (we'd be expected to clean up the stack afterwards). If
2003 // caller is C then we could potentially use its argument area.
2005 // FIXME: for now we take the most conservative of these in both cases:
2006 // disallow all variadic memory operands.
2007 SmallVector<CCValAssign, 16> ArgLocs;
2008 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2009 getTargetMachine(), ArgLocs, *DAG.getContext());
2011 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2012 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2013 if (!ArgLocs[i].isRegLoc())
2017 // If the calling conventions do not match, then we'd better make sure the
2018 // results are returned in the same way as what the caller expects.
2020 SmallVector<CCValAssign, 16> RVLocs1;
2021 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2022 getTargetMachine(), RVLocs1, *DAG.getContext());
2023 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2025 SmallVector<CCValAssign, 16> RVLocs2;
2026 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2027 getTargetMachine(), RVLocs2, *DAG.getContext());
2028 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2030 if (RVLocs1.size() != RVLocs2.size())
2032 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2033 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2035 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2037 if (RVLocs1[i].isRegLoc()) {
2038 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2041 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2047 // Nothing more to check if the callee is taking no arguments
2051 SmallVector<CCValAssign, 16> ArgLocs;
2052 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2053 getTargetMachine(), ArgLocs, *DAG.getContext());
2055 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2057 const ARM64FunctionInfo *FuncInfo = MF.getInfo<ARM64FunctionInfo>();
2059 // If the stack arguments for this call would fit into our own save area then
2060 // the call can be made tail.
2061 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2064 SDValue ARM64TargetLowering::addTokenForArgument(SDValue Chain,
2066 MachineFrameInfo *MFI,
2067 int ClobberedFI) const {
2068 SmallVector<SDValue, 8> ArgChains;
2069 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2070 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2072 // Include the original chain at the beginning of the list. When this is
2073 // used by target LowerCall hooks, this helps legalize find the
2074 // CALLSEQ_BEGIN node.
2075 ArgChains.push_back(Chain);
2077 // Add a chain value for each stack argument corresponding
2078 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2079 UE = DAG.getEntryNode().getNode()->use_end();
2081 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2082 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2083 if (FI->getIndex() < 0) {
2084 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2085 int64_t InLastByte = InFirstByte;
2086 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2088 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2089 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2090 ArgChains.push_back(SDValue(L, 1));
2093 // Build a tokenfactor for all the chains.
2094 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2097 bool ARM64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2098 bool TailCallOpt) const {
2099 return CallCC == CallingConv::Fast && TailCallOpt;
2102 bool ARM64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2103 return CallCC == CallingConv::Fast;
2106 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2107 /// and add input and output parameter nodes.
2108 SDValue ARM64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2109 SmallVectorImpl<SDValue> &InVals) const {
2110 SelectionDAG &DAG = CLI.DAG;
2112 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2113 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2114 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2115 SDValue Chain = CLI.Chain;
2116 SDValue Callee = CLI.Callee;
2117 bool &IsTailCall = CLI.IsTailCall;
2118 CallingConv::ID CallConv = CLI.CallConv;
2119 bool IsVarArg = CLI.IsVarArg;
2121 MachineFunction &MF = DAG.getMachineFunction();
2122 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2123 bool IsThisReturn = false;
2125 ARM64FunctionInfo *FuncInfo = MF.getInfo<ARM64FunctionInfo>();
2126 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2127 bool IsSibCall = false;
2130 // Check if it's really possible to do a tail call.
2131 IsTailCall = isEligibleForTailCallOptimization(
2132 Callee, CallConv, IsVarArg, IsStructRet,
2133 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2134 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2135 report_fatal_error("failed to perform tail call elimination on a call "
2136 "site marked musttail");
2138 // A sibling call is one where we're under the usual C ABI and not planning
2139 // to change that but can still do a tail call:
2140 if (!TailCallOpt && IsTailCall)
2147 // Analyze operands of the call, assigning locations to each operand.
2148 SmallVector<CCValAssign, 16> ArgLocs;
2149 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2150 getTargetMachine(), ArgLocs, *DAG.getContext());
2153 // Handle fixed and variable vector arguments differently.
2154 // Variable vector arguments always go into memory.
2155 unsigned NumArgs = Outs.size();
2157 for (unsigned i = 0; i != NumArgs; ++i) {
2158 MVT ArgVT = Outs[i].VT;
2159 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2160 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2161 /*IsVarArg=*/ !Outs[i].IsFixed);
2162 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2163 assert(!Res && "Call operand has unhandled type");
2167 // At this point, Outs[].VT may already be promoted to i32. To correctly
2168 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2169 // i8 to CC_ARM64_AAPCS with i32 being ValVT and i8 being LocVT.
2170 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2171 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2173 unsigned NumArgs = Outs.size();
2174 for (unsigned i = 0; i != NumArgs; ++i) {
2175 MVT ValVT = Outs[i].VT;
2176 // Get type of the original argument.
2177 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2178 /*AllowUnknown*/ true);
2179 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2180 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2181 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2183 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2185 else if (ActualMVT == MVT::i16)
2188 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2189 bool Res = AssignFn(i, ValVT, LocVT, CCValAssign::Full, ArgFlags, CCInfo);
2190 assert(!Res && "Call operand has unhandled type");
2195 // Get a count of how many bytes are to be pushed on the stack.
2196 unsigned NumBytes = CCInfo.getNextStackOffset();
2199 // Since we're not changing the ABI to make this a tail call, the memory
2200 // operands are already available in the caller's incoming argument space.
2204 // FPDiff is the byte offset of the call's argument area from the callee's.
2205 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2206 // by this amount for a tail call. In a sibling call it must be 0 because the
2207 // caller will deallocate the entire stack and the callee still expects its
2208 // arguments to begin at SP+0. Completely unused for non-tail calls.
2211 if (IsTailCall && !IsSibCall) {
2212 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2214 // Since callee will pop argument stack as a tail call, we must keep the
2215 // popped size 16-byte aligned.
2216 NumBytes = RoundUpToAlignment(NumBytes, 16);
2218 // FPDiff will be negative if this tail call requires more space than we
2219 // would automatically have in our incoming argument space. Positive if we
2220 // can actually shrink the stack.
2221 FPDiff = NumReusableBytes - NumBytes;
2223 // The stack pointer must be 16-byte aligned at all times it's used for a
2224 // memory operation, which in practice means at *all* times and in
2225 // particular across call boundaries. Therefore our own arguments started at
2226 // a 16-byte aligned SP and the delta applied for the tail call should
2227 // satisfy the same constraint.
2228 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2231 // Adjust the stack pointer for the new arguments...
2232 // These operations are automatically eliminated by the prolog/epilog pass
2235 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2237 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, ARM64::SP, getPointerTy());
2239 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2240 SmallVector<SDValue, 8> MemOpChains;
2242 // Walk the register/memloc assignments, inserting copies/loads.
2243 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2244 ++i, ++realArgIdx) {
2245 CCValAssign &VA = ArgLocs[i];
2246 SDValue Arg = OutVals[realArgIdx];
2247 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2249 // Promote the value if needed.
2250 switch (VA.getLocInfo()) {
2252 llvm_unreachable("Unknown loc info!");
2253 case CCValAssign::Full:
2255 case CCValAssign::SExt:
2256 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2258 case CCValAssign::ZExt:
2259 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2261 case CCValAssign::AExt:
2262 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2264 case CCValAssign::BCvt:
2265 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2267 case CCValAssign::FPExt:
2268 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2272 if (VA.isRegLoc()) {
2273 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2274 assert(VA.getLocVT() == MVT::i64 &&
2275 "unexpected calling convention register assignment");
2276 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2277 "unexpected use of 'returned'");
2278 IsThisReturn = true;
2280 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2282 assert(VA.isMemLoc());
2285 MachinePointerInfo DstInfo;
2287 // FIXME: This works on big-endian for composite byvals, which are the
2288 // common case. It should also work for fundamental types too.
2289 uint32_t BEAlign = 0;
2290 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2291 : VA.getLocVT().getSizeInBits();
2292 OpSize = (OpSize + 7) / 8;
2293 if (!Subtarget->isLittleEndian() && !Flags.isByVal()) {
2295 BEAlign = 8 - OpSize;
2297 unsigned LocMemOffset = VA.getLocMemOffset();
2298 int32_t Offset = LocMemOffset + BEAlign;
2299 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2300 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2303 Offset = Offset + FPDiff;
2304 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2306 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2307 DstInfo = MachinePointerInfo::getFixedStack(FI);
2309 // Make sure any stack arguments overlapping with where we're storing
2310 // are loaded before this eventual operation. Otherwise they'll be
2312 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2314 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2316 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2317 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2320 if (Outs[i].Flags.isByVal()) {
2322 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2323 SDValue Cpy = DAG.getMemcpy(
2324 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2325 /*isVolatile = */ false,
2326 /*alwaysInline = */ false, DstInfo, MachinePointerInfo());
2328 MemOpChains.push_back(Cpy);
2330 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2331 // promoted to a legal register type i32, we should truncate Arg back to
2333 if (Arg.getValueType().isSimple() &&
2334 Arg.getValueType().getSimpleVT() == MVT::i32 &&
2335 (VA.getLocVT() == MVT::i1 || VA.getLocVT() == MVT::i8 ||
2336 VA.getLocVT() == MVT::i16))
2337 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getLocVT(), Arg);
2340 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2341 MemOpChains.push_back(Store);
2346 if (!MemOpChains.empty())
2347 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2349 // Build a sequence of copy-to-reg nodes chained together with token chain
2350 // and flag operands which copy the outgoing args into the appropriate regs.
2352 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2353 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2354 RegsToPass[i].second, InFlag);
2355 InFlag = Chain.getValue(1);
2358 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2359 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2360 // node so that legalize doesn't hack it.
2361 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2362 Subtarget->isTargetMachO()) {
2363 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2364 const GlobalValue *GV = G->getGlobal();
2365 bool InternalLinkage = GV->hasInternalLinkage();
2366 if (InternalLinkage)
2367 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2369 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2371 Callee = DAG.getNode(ARM64ISD::LOADgot, DL, getPointerTy(), Callee);
2373 } else if (ExternalSymbolSDNode *S =
2374 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2375 const char *Sym = S->getSymbol();
2377 DAG.getTargetExternalSymbol(Sym, getPointerTy(), ARM64II::MO_GOT);
2378 Callee = DAG.getNode(ARM64ISD::LOADgot, DL, getPointerTy(), Callee);
2380 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2381 const GlobalValue *GV = G->getGlobal();
2382 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2383 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2384 const char *Sym = S->getSymbol();
2385 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2388 // We don't usually want to end the call-sequence here because we would tidy
2389 // the frame up *after* the call, however in the ABI-changing tail-call case
2390 // we've carefully laid out the parameters so that when sp is reset they'll be
2391 // in the correct location.
2392 if (IsTailCall && !IsSibCall) {
2393 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2394 DAG.getIntPtrConstant(0, true), InFlag, DL);
2395 InFlag = Chain.getValue(1);
2398 std::vector<SDValue> Ops;
2399 Ops.push_back(Chain);
2400 Ops.push_back(Callee);
2403 // Each tail call may have to adjust the stack by a different amount, so
2404 // this information must travel along with the operation for eventual
2405 // consumption by emitEpilogue.
2406 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2409 // Add argument registers to the end of the list so that they are known live
2411 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2412 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2413 RegsToPass[i].second.getValueType()));
2415 // Add a register mask operand representing the call-preserved registers.
2416 const uint32_t *Mask;
2417 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2418 const ARM64RegisterInfo *ARI = static_cast<const ARM64RegisterInfo *>(TRI);
2420 // For 'this' returns, use the X0-preserving mask if applicable
2421 Mask = ARI->getThisReturnPreservedMask(CallConv);
2423 IsThisReturn = false;
2424 Mask = ARI->getCallPreservedMask(CallConv);
2427 Mask = ARI->getCallPreservedMask(CallConv);
2429 assert(Mask && "Missing call preserved mask for calling convention");
2430 Ops.push_back(DAG.getRegisterMask(Mask));
2432 if (InFlag.getNode())
2433 Ops.push_back(InFlag);
2435 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2437 // If we're doing a tall call, use a TC_RETURN here rather than an
2438 // actual call instruction.
2440 return DAG.getNode(ARM64ISD::TC_RETURN, DL, NodeTys, Ops);
2442 // Returns a chain and a flag for retval copy to use.
2443 Chain = DAG.getNode(ARM64ISD::CALL, DL, NodeTys, Ops);
2444 InFlag = Chain.getValue(1);
2446 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2447 ? RoundUpToAlignment(NumBytes, 16)
2450 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2451 DAG.getIntPtrConstant(CalleePopBytes, true),
2454 InFlag = Chain.getValue(1);
2456 // Handle result values, copying them out of physregs into vregs that we
2458 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2459 InVals, IsThisReturn,
2460 IsThisReturn ? OutVals[0] : SDValue());
2463 bool ARM64TargetLowering::CanLowerReturn(
2464 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2465 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2466 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS ? RetCC_ARM64_WebKit_JS
2467 : RetCC_ARM64_AAPCS;
2468 SmallVector<CCValAssign, 16> RVLocs;
2469 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
2470 return CCInfo.CheckReturn(Outs, RetCC);
2474 ARM64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2476 const SmallVectorImpl<ISD::OutputArg> &Outs,
2477 const SmallVectorImpl<SDValue> &OutVals,
2478 SDLoc DL, SelectionDAG &DAG) const {
2479 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS ? RetCC_ARM64_WebKit_JS
2480 : RetCC_ARM64_AAPCS;
2481 SmallVector<CCValAssign, 16> RVLocs;
2482 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2483 getTargetMachine(), RVLocs, *DAG.getContext());
2484 CCInfo.AnalyzeReturn(Outs, RetCC);
2486 // Copy the result values into the output registers.
2488 SmallVector<SDValue, 4> RetOps(1, Chain);
2489 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2490 ++i, ++realRVLocIdx) {
2491 CCValAssign &VA = RVLocs[i];
2492 assert(VA.isRegLoc() && "Can only return in registers!");
2493 SDValue Arg = OutVals[realRVLocIdx];
2495 switch (VA.getLocInfo()) {
2497 llvm_unreachable("Unknown loc info!");
2498 case CCValAssign::Full:
2500 case CCValAssign::BCvt:
2501 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2505 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2506 Flag = Chain.getValue(1);
2507 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2510 RetOps[0] = Chain; // Update chain.
2512 // Add the flag if we have it.
2514 RetOps.push_back(Flag);
2516 return DAG.getNode(ARM64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2519 //===----------------------------------------------------------------------===//
2520 // Other Lowering Code
2521 //===----------------------------------------------------------------------===//
2523 SDValue ARM64TargetLowering::LowerGlobalAddress(SDValue Op,
2524 SelectionDAG &DAG) const {
2525 EVT PtrVT = getPointerTy();
2527 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2528 unsigned char OpFlags =
2529 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2531 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2532 "unexpected offset in global node");
2534 // This also catched the large code model case for Darwin.
2535 if ((OpFlags & ARM64II::MO_GOT) != 0) {
2536 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2537 // FIXME: Once remat is capable of dealing with instructions with register
2538 // operands, expand this into two nodes instead of using a wrapper node.
2539 return DAG.getNode(ARM64ISD::LOADgot, DL, PtrVT, GotAddr);
2542 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2543 const unsigned char MO_NC = ARM64II::MO_NC;
2545 ARM64ISD::WrapperLarge, DL, PtrVT,
2546 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, ARM64II::MO_G3),
2547 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, ARM64II::MO_G2 | MO_NC),
2548 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, ARM64II::MO_G1 | MO_NC),
2549 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, ARM64II::MO_G0 | MO_NC));
2551 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2552 // the only correct model on Darwin.
2553 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2554 OpFlags | ARM64II::MO_PAGE);
2555 unsigned char LoFlags = OpFlags | ARM64II::MO_PAGEOFF | ARM64II::MO_NC;
2556 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2558 SDValue ADRP = DAG.getNode(ARM64ISD::ADRP, DL, PtrVT, Hi);
2559 return DAG.getNode(ARM64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2563 /// \brief Convert a TLS address reference into the correct sequence of loads
2564 /// and calls to compute the variable's address (for Darwin, currently) and
2565 /// return an SDValue containing the final node.
2567 /// Darwin only has one TLS scheme which must be capable of dealing with the
2568 /// fully general situation, in the worst case. This means:
2569 /// + "extern __thread" declaration.
2570 /// + Defined in a possibly unknown dynamic library.
2572 /// The general system is that each __thread variable has a [3 x i64] descriptor
2573 /// which contains information used by the runtime to calculate the address. The
2574 /// only part of this the compiler needs to know about is the first xword, which
2575 /// contains a function pointer that must be called with the address of the
2576 /// entire descriptor in "x0".
2578 /// Since this descriptor may be in a different unit, in general even the
2579 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2581 /// adrp x0, _var@TLVPPAGE
2582 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2583 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2584 /// ; the function pointer
2585 /// blr x1 ; Uses descriptor address in x0
2586 /// ; Address of _var is now in x0.
2588 /// If the address of _var's descriptor *is* known to the linker, then it can
2589 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2590 /// a slight efficiency gain.
2592 ARM64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
2593 SelectionDAG &DAG) const {
2594 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
2597 MVT PtrVT = getPointerTy();
2598 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2601 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, ARM64II::MO_TLS);
2602 SDValue DescAddr = DAG.getNode(ARM64ISD::LOADgot, DL, PtrVT, TLVPAddr);
2604 // The first entry in the descriptor is a function pointer that we must call
2605 // to obtain the address of the variable.
2606 SDValue Chain = DAG.getEntryNode();
2607 SDValue FuncTLVGet =
2608 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
2609 false, true, true, 8);
2610 Chain = FuncTLVGet.getValue(1);
2612 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2613 MFI->setAdjustsStack(true);
2615 // TLS calls preserve all registers except those that absolutely must be
2616 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2618 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2619 const ARM64RegisterInfo *ARI = static_cast<const ARM64RegisterInfo *>(TRI);
2620 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2622 // Finally, we can make the call. This is just a degenerate version of a
2623 // normal ARM64 call node: x0 takes the address of the descriptor, and returns
2624 // the address of the variable in this thread.
2625 Chain = DAG.getCopyToReg(Chain, DL, ARM64::X0, DescAddr, SDValue());
2626 Chain = DAG.getNode(ARM64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2627 Chain, FuncTLVGet, DAG.getRegister(ARM64::X0, MVT::i64),
2628 DAG.getRegisterMask(Mask), Chain.getValue(1));
2629 return DAG.getCopyFromReg(Chain, DL, ARM64::X0, PtrVT, Chain.getValue(1));
2632 /// When accessing thread-local variables under either the general-dynamic or
2633 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
2634 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
2635 /// is a function pointer to carry out the resolution. This function takes the
2636 /// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All
2637 /// other registers (except LR, NZCV) are preserved.
2639 /// Thus, the ideal call sequence on AArch64 is:
2641 /// adrp x0, :tlsdesc:thread_var
2642 /// ldr x8, [x0, :tlsdesc_lo12:thread_var]
2643 /// add x0, x0, :tlsdesc_lo12:thread_var
2644 /// .tlsdesccall thread_var
2646 /// (TPIDR_EL0 offset now in x0).
2648 /// The ".tlsdesccall" directive instructs the assembler to insert a particular
2649 /// relocation to help the linker relax this sequence if it turns out to be too
2652 /// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this
2654 SDValue ARM64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
2655 SDValue DescAddr, SDLoc DL,
2656 SelectionDAG &DAG) const {
2657 EVT PtrVT = getPointerTy();
2659 // The function we need to call is simply the first entry in the GOT for this
2660 // descriptor, load it in preparation.
2661 SDValue Func = DAG.getNode(ARM64ISD::LOADgot, DL, PtrVT, SymAddr);
2663 // TLS calls preserve all registers except those that absolutely must be
2664 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2666 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2667 const ARM64RegisterInfo *ARI = static_cast<const ARM64RegisterInfo *>(TRI);
2668 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2670 // The function takes only one argument: the address of the descriptor itself
2672 SDValue Glue, Chain;
2673 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM64::X0, DescAddr, Glue);
2674 Glue = Chain.getValue(1);
2676 // We're now ready to populate the argument list, as with a normal call:
2677 SmallVector<SDValue, 6> Ops;
2678 Ops.push_back(Chain);
2679 Ops.push_back(Func);
2680 Ops.push_back(SymAddr);
2681 Ops.push_back(DAG.getRegister(ARM64::X0, PtrVT));
2682 Ops.push_back(DAG.getRegisterMask(Mask));
2683 Ops.push_back(Glue);
2685 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2686 Chain = DAG.getNode(ARM64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
2687 Glue = Chain.getValue(1);
2689 return DAG.getCopyFromReg(Chain, DL, ARM64::X0, PtrVT, Glue);
2692 SDValue ARM64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
2693 SelectionDAG &DAG) const {
2694 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
2695 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2696 "ELF TLS only supported in small memory model");
2697 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2699 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2702 EVT PtrVT = getPointerTy();
2704 const GlobalValue *GV = GA->getGlobal();
2706 SDValue ThreadBase = DAG.getNode(ARM64ISD::THREAD_POINTER, DL, PtrVT);
2708 if (Model == TLSModel::LocalExec) {
2709 SDValue HiVar = DAG.getTargetGlobalAddress(
2710 GV, DL, PtrVT, 0, ARM64II::MO_TLS | ARM64II::MO_G1);
2711 SDValue LoVar = DAG.getTargetGlobalAddress(
2712 GV, DL, PtrVT, 0, ARM64II::MO_TLS | ARM64II::MO_G0 | ARM64II::MO_NC);
2714 TPOff = SDValue(DAG.getMachineNode(ARM64::MOVZXi, DL, PtrVT, HiVar,
2715 DAG.getTargetConstant(16, MVT::i32)),
2717 TPOff = SDValue(DAG.getMachineNode(ARM64::MOVKXi, DL, PtrVT, TPOff, LoVar,
2718 DAG.getTargetConstant(0, MVT::i32)),
2720 } else if (Model == TLSModel::InitialExec) {
2721 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, ARM64II::MO_TLS);
2722 TPOff = DAG.getNode(ARM64ISD::LOADgot, DL, PtrVT, TPOff);
2723 } else if (Model == TLSModel::LocalDynamic) {
2724 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2725 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2726 // the beginning of the module's TLS region, followed by a DTPREL offset
2729 // These accesses will need deduplicating if there's more than one.
2730 ARM64FunctionInfo *MFI =
2731 DAG.getMachineFunction().getInfo<ARM64FunctionInfo>();
2732 MFI->incNumLocalDynamicTLSAccesses();
2734 // Accesses used in this sequence go via the TLS descriptor which lives in
2735 // the GOT. Prepare an address we can use to handle this.
2736 SDValue HiDesc = DAG.getTargetExternalSymbol(
2737 "_TLS_MODULE_BASE_", PtrVT, ARM64II::MO_TLS | ARM64II::MO_PAGE);
2738 SDValue LoDesc = DAG.getTargetExternalSymbol(
2739 "_TLS_MODULE_BASE_", PtrVT,
2740 ARM64II::MO_TLS | ARM64II::MO_PAGEOFF | ARM64II::MO_NC);
2742 // First argument to the descriptor call is the address of the descriptor
2744 SDValue DescAddr = DAG.getNode(ARM64ISD::ADRP, DL, PtrVT, HiDesc);
2745 DescAddr = DAG.getNode(ARM64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2747 // The call needs a relocation too for linker relaxation. It doesn't make
2748 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2750 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2753 // Now we can calculate the offset from TPIDR_EL0 to this module's
2754 // thread-local area.
2755 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2757 // Now use :dtprel_whatever: operations to calculate this variable's offset
2758 // in its thread-storage area.
2759 SDValue HiVar = DAG.getTargetGlobalAddress(
2760 GV, DL, MVT::i64, 0, ARM64II::MO_TLS | ARM64II::MO_G1);
2761 SDValue LoVar = DAG.getTargetGlobalAddress(
2762 GV, DL, MVT::i64, 0, ARM64II::MO_TLS | ARM64II::MO_G0 | ARM64II::MO_NC);
2765 SDValue(DAG.getMachineNode(ARM64::MOVZXi, DL, PtrVT, HiVar,
2766 DAG.getTargetConstant(16, MVT::i32)),
2768 DTPOff = SDValue(DAG.getMachineNode(ARM64::MOVKXi, DL, PtrVT, DTPOff, LoVar,
2769 DAG.getTargetConstant(0, MVT::i32)),
2772 TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff);
2773 } else if (Model == TLSModel::GeneralDynamic) {
2774 // Accesses used in this sequence go via the TLS descriptor which lives in
2775 // the GOT. Prepare an address we can use to handle this.
2776 SDValue HiDesc = DAG.getTargetGlobalAddress(
2777 GV, DL, PtrVT, 0, ARM64II::MO_TLS | ARM64II::MO_PAGE);
2778 SDValue LoDesc = DAG.getTargetGlobalAddress(
2780 ARM64II::MO_TLS | ARM64II::MO_PAGEOFF | ARM64II::MO_NC);
2782 // First argument to the descriptor call is the address of the descriptor
2784 SDValue DescAddr = DAG.getNode(ARM64ISD::ADRP, DL, PtrVT, HiDesc);
2785 DescAddr = DAG.getNode(ARM64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2787 // The call needs a relocation too for linker relaxation. It doesn't make
2788 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2791 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, ARM64II::MO_TLS);
2793 // Finally we can make a call to calculate the offset from tpidr_el0.
2794 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2796 llvm_unreachable("Unsupported ELF TLS access model");
2798 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2801 SDValue ARM64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2802 SelectionDAG &DAG) const {
2803 if (Subtarget->isTargetDarwin())
2804 return LowerDarwinGlobalTLSAddress(Op, DAG);
2805 else if (Subtarget->isTargetELF())
2806 return LowerELFGlobalTLSAddress(Op, DAG);
2808 llvm_unreachable("Unexpected platform trying to use TLS");
2810 SDValue ARM64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2811 SDValue Chain = Op.getOperand(0);
2812 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2813 SDValue LHS = Op.getOperand(2);
2814 SDValue RHS = Op.getOperand(3);
2815 SDValue Dest = Op.getOperand(4);
2818 // Handle f128 first, since lowering it will result in comparing the return
2819 // value of a libcall against zero, which is just what the rest of LowerBR_CC
2820 // is expecting to deal with.
2821 if (LHS.getValueType() == MVT::f128) {
2822 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2824 // If softenSetCCOperands returned a scalar, we need to compare the result
2825 // against zero to select between true and false values.
2826 if (!RHS.getNode()) {
2827 RHS = DAG.getConstant(0, LHS.getValueType());
2832 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
2834 unsigned Opc = LHS.getOpcode();
2835 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
2836 cast<ConstantSDNode>(RHS)->isOne() &&
2837 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
2838 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
2839 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
2840 "Unexpected condition code.");
2841 // Only lower legal XALUO ops.
2842 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
2845 // The actual operation with overflow check.
2846 ARM64CC::CondCode OFCC;
2847 SDValue Value, Overflow;
2848 std::tie(Value, Overflow) = getARM64XALUOOp(OFCC, LHS.getValue(0), DAG);
2850 if (CC == ISD::SETNE)
2851 OFCC = getInvertedCondCode(OFCC);
2852 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
2854 return DAG.getNode(ARM64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,
2858 if (LHS.getValueType().isInteger()) {
2859 assert((LHS.getValueType() == RHS.getValueType()) &&
2860 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
2862 // If the RHS of the comparison is zero, we can potentially fold this
2863 // to a specialized branch.
2864 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
2865 if (RHSC && RHSC->getZExtValue() == 0) {
2866 if (CC == ISD::SETEQ) {
2867 // See if we can use a TBZ to fold in an AND as well.
2868 // TBZ has a smaller branch displacement than CBZ. If the offset is
2869 // out of bounds, a late MI-layer pass rewrites branches.
2870 // 403.gcc is an example that hits this case.
2871 if (LHS.getOpcode() == ISD::AND &&
2872 isa<ConstantSDNode>(LHS.getOperand(1)) &&
2873 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
2874 SDValue Test = LHS.getOperand(0);
2875 uint64_t Mask = LHS.getConstantOperandVal(1);
2877 // TBZ only operates on i64's, but the ext should be free.
2878 if (Test.getValueType() == MVT::i32)
2879 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2881 return DAG.getNode(ARM64ISD::TBZ, dl, MVT::Other, Chain, Test,
2882 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2885 return DAG.getNode(ARM64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
2886 } else if (CC == ISD::SETNE) {
2887 // See if we can use a TBZ to fold in an AND as well.
2888 // TBZ has a smaller branch displacement than CBZ. If the offset is
2889 // out of bounds, a late MI-layer pass rewrites branches.
2890 // 403.gcc is an example that hits this case.
2891 if (LHS.getOpcode() == ISD::AND &&
2892 isa<ConstantSDNode>(LHS.getOperand(1)) &&
2893 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
2894 SDValue Test = LHS.getOperand(0);
2895 uint64_t Mask = LHS.getConstantOperandVal(1);
2897 // TBNZ only operates on i64's, but the ext should be free.
2898 if (Test.getValueType() == MVT::i32)
2899 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2901 return DAG.getNode(ARM64ISD::TBNZ, dl, MVT::Other, Chain, Test,
2902 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2905 return DAG.getNode(ARM64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
2910 SDValue Cmp = getARM64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
2911 return DAG.getNode(ARM64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
2915 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2917 // Unfortunately, the mapping of LLVM FP CC's onto ARM64 CC's isn't totally
2918 // clean. Some of them require two branches to implement.
2919 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
2920 ARM64CC::CondCode CC1, CC2;
2921 changeFPCCToARM64CC(CC, CC1, CC2);
2922 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
2924 DAG.getNode(ARM64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
2925 if (CC2 != ARM64CC::AL) {
2926 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
2927 return DAG.getNode(ARM64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
2934 SDValue ARM64TargetLowering::LowerFCOPYSIGN(SDValue Op,
2935 SelectionDAG &DAG) const {
2936 EVT VT = Op.getValueType();
2939 SDValue In1 = Op.getOperand(0);
2940 SDValue In2 = Op.getOperand(1);
2941 EVT SrcVT = In2.getValueType();
2943 if (SrcVT == MVT::f32 && VT == MVT::f64)
2944 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
2945 else if (SrcVT == MVT::f64 && VT == MVT::f32)
2946 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
2948 // FIXME: Src type is different, bail out for now. Can VT really be a
2955 SDValue EltMask, VecVal1, VecVal2;
2956 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
2959 EltMask = DAG.getConstant(0x80000000ULL, EltVT);
2961 if (!VT.isVector()) {
2962 VecVal1 = DAG.getTargetInsertSubreg(ARM64::ssub, DL, VecVT,
2963 DAG.getUNDEF(VecVT), In1);
2964 VecVal2 = DAG.getTargetInsertSubreg(ARM64::ssub, DL, VecVT,
2965 DAG.getUNDEF(VecVT), In2);
2967 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
2968 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
2970 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
2974 // We want to materialize a mask with the the high bit set, but the AdvSIMD
2975 // immediate moves cannot materialize that in a single instruction for
2976 // 64-bit elements. Instead, materialize zero and then negate it.
2977 EltMask = DAG.getConstant(0, EltVT);
2979 if (!VT.isVector()) {
2980 VecVal1 = DAG.getTargetInsertSubreg(ARM64::dsub, DL, VecVT,
2981 DAG.getUNDEF(VecVT), In1);
2982 VecVal2 = DAG.getTargetInsertSubreg(ARM64::dsub, DL, VecVT,
2983 DAG.getUNDEF(VecVT), In2);
2985 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
2986 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
2989 llvm_unreachable("Invalid type for copysign!");
2992 std::vector<SDValue> BuildVectorOps;
2993 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
2994 BuildVectorOps.push_back(EltMask);
2996 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps);
2998 // If we couldn't materialize the mask above, then the mask vector will be
2999 // the zero vector, and we need to negate it here.
3000 if (VT == MVT::f64 || VT == MVT::v2f64) {
3001 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3002 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3003 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3007 DAG.getNode(ARM64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3010 return DAG.getTargetExtractSubreg(ARM64::ssub, DL, VT, Sel);
3011 else if (VT == MVT::f64)
3012 return DAG.getTargetExtractSubreg(ARM64::dsub, DL, VT, Sel);
3014 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3017 SDValue ARM64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3018 if (DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
3019 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat))
3022 // While there is no integer popcount instruction, it can
3023 // be more efficiently lowered to the following sequence that uses
3024 // AdvSIMD registers/instructions as long as the copies to/from
3025 // the AdvSIMD registers are cheap.
3026 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3027 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3028 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3029 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3030 SDValue Val = Op.getOperand(0);
3032 EVT VT = Op.getValueType();
3033 SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
3036 if (VT == MVT::i32) {
3037 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
3039 DAG.getTargetInsertSubreg(ARM64::ssub, DL, MVT::v8i8, ZeroVec, VecVal);
3041 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3044 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
3045 SDValue UaddLV = DAG.getNode(
3046 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3047 DAG.getConstant(Intrinsic::arm64_neon_uaddlv, MVT::i32), CtPop);
3050 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3054 SDValue ARM64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3056 if (Op.getValueType().isVector())
3057 return LowerVSETCC(Op, DAG);
3059 SDValue LHS = Op.getOperand(0);
3060 SDValue RHS = Op.getOperand(1);
3061 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3064 // We chose ZeroOrOneBooleanContents, so use zero and one.
3065 EVT VT = Op.getValueType();
3066 SDValue TVal = DAG.getConstant(1, VT);
3067 SDValue FVal = DAG.getConstant(0, VT);
3069 // Handle f128 first, since one possible outcome is a normal integer
3070 // comparison which gets picked up by the next if statement.
3071 if (LHS.getValueType() == MVT::f128) {
3072 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3074 // If softenSetCCOperands returned a scalar, use it.
3075 if (!RHS.getNode()) {
3076 assert(LHS.getValueType() == Op.getValueType() &&
3077 "Unexpected setcc expansion!");
3082 if (LHS.getValueType().isInteger()) {
3085 getARM64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3087 // Note that we inverted the condition above, so we reverse the order of
3088 // the true and false operands here. This will allow the setcc to be
3089 // matched to a single CSINC instruction.
3090 return DAG.getNode(ARM64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3093 // Now we know we're dealing with FP values.
3094 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3096 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3097 // and do the comparison.
3098 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3100 ARM64CC::CondCode CC1, CC2;
3101 changeFPCCToARM64CC(CC, CC1, CC2);
3102 if (CC2 == ARM64CC::AL) {
3103 changeFPCCToARM64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3104 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3106 // Note that we inverted the condition above, so we reverse the order of
3107 // the true and false operands here. This will allow the setcc to be
3108 // matched to a single CSINC instruction.
3109 return DAG.getNode(ARM64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3111 // Unfortunately, the mapping of LLVM FP CC's onto ARM64 CC's isn't totally
3112 // clean. Some of them require two CSELs to implement. As is in this case,
3113 // we emit the first CSEL and then emit a second using the output of the
3114 // first as the RHS. We're effectively OR'ing the two CC's together.
3116 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3117 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3118 SDValue CS1 = DAG.getNode(ARM64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3120 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3121 return DAG.getNode(ARM64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3125 /// A SELECT_CC operation is really some kind of max or min if both values being
3126 /// compared are, in some sense, equal to the results in either case. However,
3127 /// it is permissible to compare f32 values and produce directly extended f64
3130 /// Extending the comparison operands would also be allowed, but is less likely
3131 /// to happen in practice since their use is right here. Note that truncate
3132 /// operations would *not* be semantically equivalent.
3133 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3137 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3138 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3139 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3140 Result.getValueType() == MVT::f64) {
3142 APFloat CmpVal = CCmp->getValueAPF();
3143 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3144 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3147 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3150 SDValue ARM64TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
3151 SDValue CC = Op->getOperand(0);
3152 SDValue TVal = Op->getOperand(1);
3153 SDValue FVal = Op->getOperand(2);
3156 unsigned Opc = CC.getOpcode();
3157 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3159 if (CC.getResNo() == 1 &&
3160 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3161 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3162 // Only lower legal XALUO ops.
3163 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3166 ARM64CC::CondCode OFCC;
3167 SDValue Value, Overflow;
3168 std::tie(Value, Overflow) = getARM64XALUOOp(OFCC, CC.getValue(0), DAG);
3169 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3171 return DAG.getNode(ARM64ISD::CSEL, DL, Op.getValueType(), TVal, FVal, CCVal,
3175 if (CC.getOpcode() == ISD::SETCC)
3176 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3177 cast<CondCodeSDNode>(CC.getOperand(2))->get());
3179 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3183 SDValue ARM64TargetLowering::LowerSELECT_CC(SDValue Op,
3184 SelectionDAG &DAG) const {
3185 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3186 SDValue LHS = Op.getOperand(0);
3187 SDValue RHS = Op.getOperand(1);
3188 SDValue TVal = Op.getOperand(2);
3189 SDValue FVal = Op.getOperand(3);
3192 // Handle f128 first, because it will result in a comparison of some RTLIB
3193 // call result against zero.
3194 if (LHS.getValueType() == MVT::f128) {
3195 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3197 // If softenSetCCOperands returned a scalar, we need to compare the result
3198 // against zero to select between true and false values.
3199 if (!RHS.getNode()) {
3200 RHS = DAG.getConstant(0, LHS.getValueType());
3205 // Handle integers first.
3206 if (LHS.getValueType().isInteger()) {
3207 assert((LHS.getValueType() == RHS.getValueType()) &&
3208 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3210 unsigned Opcode = ARM64ISD::CSEL;
3212 // If both the TVal and the FVal are constants, see if we can swap them in
3213 // order to for a CSINV or CSINC out of them.
3214 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3215 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3217 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3218 std::swap(TVal, FVal);
3219 std::swap(CTVal, CFVal);
3220 CC = ISD::getSetCCInverse(CC, true);
3221 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3222 std::swap(TVal, FVal);
3223 std::swap(CTVal, CFVal);
3224 CC = ISD::getSetCCInverse(CC, true);
3225 } else if (TVal.getOpcode() == ISD::XOR) {
3226 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3227 // with a CSINV rather than a CSEL.
3228 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3230 if (CVal && CVal->isAllOnesValue()) {
3231 std::swap(TVal, FVal);
3232 std::swap(CTVal, CFVal);
3233 CC = ISD::getSetCCInverse(CC, true);
3235 } else if (TVal.getOpcode() == ISD::SUB) {
3236 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3237 // that we can match with a CSNEG rather than a CSEL.
3238 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3240 if (CVal && CVal->isNullValue()) {
3241 std::swap(TVal, FVal);
3242 std::swap(CTVal, CFVal);
3243 CC = ISD::getSetCCInverse(CC, true);
3245 } else if (CTVal && CFVal) {
3246 const int64_t TrueVal = CTVal->getSExtValue();
3247 const int64_t FalseVal = CFVal->getSExtValue();
3250 // If both TVal and FVal are constants, see if FVal is the
3251 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3252 // instead of a CSEL in that case.
3253 if (TrueVal == ~FalseVal) {
3254 Opcode = ARM64ISD::CSINV;
3255 } else if (TrueVal == -FalseVal) {
3256 Opcode = ARM64ISD::CSNEG;
3257 } else if (TVal.getValueType() == MVT::i32) {
3258 // If our operands are only 32-bit wide, make sure we use 32-bit
3259 // arithmetic for the check whether we can use CSINC. This ensures that
3260 // the addition in the check will wrap around properly in case there is
3261 // an overflow (which would not be the case if we do the check with
3262 // 64-bit arithmetic).
3263 const uint32_t TrueVal32 = CTVal->getZExtValue();
3264 const uint32_t FalseVal32 = CFVal->getZExtValue();
3266 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3267 Opcode = ARM64ISD::CSINC;
3269 if (TrueVal32 > FalseVal32) {
3273 // 64-bit check whether we can use CSINC.
3274 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3275 Opcode = ARM64ISD::CSINC;
3277 if (TrueVal > FalseVal) {
3282 // Swap TVal and FVal if necessary.
3284 std::swap(TVal, FVal);
3285 std::swap(CTVal, CFVal);
3286 CC = ISD::getSetCCInverse(CC, true);
3289 if (Opcode != ARM64ISD::CSEL) {
3290 // Drop FVal since we can get its value by simply inverting/negating
3297 SDValue Cmp = getARM64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3299 EVT VT = Op.getValueType();
3300 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3303 // Now we know we're dealing with FP values.
3304 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3305 assert(LHS.getValueType() == RHS.getValueType());
3306 EVT VT = Op.getValueType();
3308 // Try to match this select into a max/min operation, which have dedicated
3309 // opcode in the instruction set.
3310 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3312 if (getTargetMachine().Options.NoNaNsFPMath) {
3313 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3314 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3315 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3316 CC = ISD::getSetCCSwappedOperands(CC);
3317 std::swap(MinMaxLHS, MinMaxRHS);
3320 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3321 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3331 return DAG.getNode(ARM64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3339 return DAG.getNode(ARM64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3345 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3346 // and do the comparison.
3347 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3349 // Unfortunately, the mapping of LLVM FP CC's onto ARM64 CC's isn't totally
3350 // clean. Some of them require two CSELs to implement.
3351 ARM64CC::CondCode CC1, CC2;
3352 changeFPCCToARM64CC(CC, CC1, CC2);
3353 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3354 SDValue CS1 = DAG.getNode(ARM64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3356 // If we need a second CSEL, emit it, using the output of the first as the
3357 // RHS. We're effectively OR'ing the two CC's together.
3358 if (CC2 != ARM64CC::AL) {
3359 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3360 return DAG.getNode(ARM64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3363 // Otherwise, return the output of the first CSEL.
3367 SDValue ARM64TargetLowering::LowerJumpTable(SDValue Op,
3368 SelectionDAG &DAG) const {
3369 // Jump table entries as PC relative offsets. No additional tweaking
3370 // is necessary here. Just get the address of the jump table.
3371 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3372 EVT PtrVT = getPointerTy();
3375 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3376 !Subtarget->isTargetMachO()) {
3377 const unsigned char MO_NC = ARM64II::MO_NC;
3379 ARM64ISD::WrapperLarge, DL, PtrVT,
3380 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, ARM64II::MO_G3),
3381 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, ARM64II::MO_G2 | MO_NC),
3382 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, ARM64II::MO_G1 | MO_NC),
3383 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, ARM64II::MO_G0 | MO_NC));
3386 SDValue Hi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, ARM64II::MO_PAGE);
3387 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3388 ARM64II::MO_PAGEOFF | ARM64II::MO_NC);
3389 SDValue ADRP = DAG.getNode(ARM64ISD::ADRP, DL, PtrVT, Hi);
3390 return DAG.getNode(ARM64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3393 SDValue ARM64TargetLowering::LowerConstantPool(SDValue Op,
3394 SelectionDAG &DAG) const {
3395 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3396 EVT PtrVT = getPointerTy();
3399 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3400 // Use the GOT for the large code model on iOS.
3401 if (Subtarget->isTargetMachO()) {
3402 SDValue GotAddr = DAG.getTargetConstantPool(
3403 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3405 return DAG.getNode(ARM64ISD::LOADgot, DL, PtrVT, GotAddr);
3408 const unsigned char MO_NC = ARM64II::MO_NC;
3410 ARM64ISD::WrapperLarge, DL, PtrVT,
3411 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3412 CP->getOffset(), ARM64II::MO_G3),
3413 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3414 CP->getOffset(), ARM64II::MO_G2 | MO_NC),
3415 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3416 CP->getOffset(), ARM64II::MO_G1 | MO_NC),
3417 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3418 CP->getOffset(), ARM64II::MO_G0 | MO_NC));
3420 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3421 // ELF, the only valid one on Darwin.
3423 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3424 CP->getOffset(), ARM64II::MO_PAGE);
3425 SDValue Lo = DAG.getTargetConstantPool(
3426 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3427 ARM64II::MO_PAGEOFF | ARM64II::MO_NC);
3429 SDValue ADRP = DAG.getNode(ARM64ISD::ADRP, DL, PtrVT, Hi);
3430 return DAG.getNode(ARM64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3434 SDValue ARM64TargetLowering::LowerBlockAddress(SDValue Op,
3435 SelectionDAG &DAG) const {
3436 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3437 EVT PtrVT = getPointerTy();
3439 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3440 !Subtarget->isTargetMachO()) {
3441 const unsigned char MO_NC = ARM64II::MO_NC;
3443 ARM64ISD::WrapperLarge, DL, PtrVT,
3444 DAG.getTargetBlockAddress(BA, PtrVT, 0, ARM64II::MO_G3),
3445 DAG.getTargetBlockAddress(BA, PtrVT, 0, ARM64II::MO_G2 | MO_NC),
3446 DAG.getTargetBlockAddress(BA, PtrVT, 0, ARM64II::MO_G1 | MO_NC),
3447 DAG.getTargetBlockAddress(BA, PtrVT, 0, ARM64II::MO_G0 | MO_NC));
3449 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, ARM64II::MO_PAGE);
3450 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, ARM64II::MO_PAGEOFF |
3452 SDValue ADRP = DAG.getNode(ARM64ISD::ADRP, DL, PtrVT, Hi);
3453 return DAG.getNode(ARM64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3457 SDValue ARM64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3458 SelectionDAG &DAG) const {
3459 ARM64FunctionInfo *FuncInfo =
3460 DAG.getMachineFunction().getInfo<ARM64FunctionInfo>();
3464 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3465 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3466 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3467 MachinePointerInfo(SV), false, false, 0);
3470 SDValue ARM64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3471 SelectionDAG &DAG) const {
3472 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3473 // Standard, section B.3.
3474 MachineFunction &MF = DAG.getMachineFunction();
3475 ARM64FunctionInfo *FuncInfo = MF.getInfo<ARM64FunctionInfo>();
3478 SDValue Chain = Op.getOperand(0);
3479 SDValue VAList = Op.getOperand(1);
3480 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3481 SmallVector<SDValue, 4> MemOps;
3483 // void *__stack at offset 0
3485 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3486 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3487 MachinePointerInfo(SV), false, false, 8));
3489 // void *__gr_top at offset 8
3490 int GPRSize = FuncInfo->getVarArgsGPRSize();
3492 SDValue GRTop, GRTopAddr;
3494 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3495 DAG.getConstant(8, getPointerTy()));
3497 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3498 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3499 DAG.getConstant(GPRSize, getPointerTy()));
3501 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3502 MachinePointerInfo(SV, 8), false, false, 8));
3505 // void *__vr_top at offset 16
3506 int FPRSize = FuncInfo->getVarArgsFPRSize();
3508 SDValue VRTop, VRTopAddr;
3509 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3510 DAG.getConstant(16, getPointerTy()));
3512 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3513 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3514 DAG.getConstant(FPRSize, getPointerTy()));
3516 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3517 MachinePointerInfo(SV, 16), false, false, 8));
3520 // int __gr_offs at offset 24
3521 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3522 DAG.getConstant(24, getPointerTy()));
3523 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3524 GROffsAddr, MachinePointerInfo(SV, 24), false,
3527 // int __vr_offs at offset 28
3528 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3529 DAG.getConstant(28, getPointerTy()));
3530 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3531 VROffsAddr, MachinePointerInfo(SV, 28), false,
3534 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3537 SDValue ARM64TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3538 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3539 : LowerAAPCS_VASTART(Op, DAG);
3542 SDValue ARM64TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
3543 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3545 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3546 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3547 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3549 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3550 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3551 8, false, false, MachinePointerInfo(DestSV),
3552 MachinePointerInfo(SrcSV));
3555 SDValue ARM64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3556 assert(Subtarget->isTargetDarwin() &&
3557 "automatic va_arg instruction only works on Darwin");
3559 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3560 EVT VT = Op.getValueType();
3562 SDValue Chain = Op.getOperand(0);
3563 SDValue Addr = Op.getOperand(1);
3564 unsigned Align = Op.getConstantOperandVal(3);
3566 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3567 MachinePointerInfo(V), false, false, false, 0);
3568 Chain = VAList.getValue(1);
3571 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3572 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3573 DAG.getConstant(Align - 1, getPointerTy()));
3574 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3575 DAG.getConstant(-(int64_t)Align, getPointerTy()));
3578 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
3579 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
3581 // Scalar integer and FP values smaller than 64 bits are implicitly extended
3582 // up to 64 bits. At the very least, we have to increase the striding of the
3583 // vaargs list to match this, and for FP values we need to introduce
3584 // FP_ROUND nodes as well.
3585 if (VT.isInteger() && !VT.isVector())
3587 bool NeedFPTrunc = false;
3588 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
3593 // Increment the pointer, VAList, to the next vaarg
3594 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3595 DAG.getConstant(ArgSize, getPointerTy()));
3596 // Store the incremented VAList to the legalized pointer
3597 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
3600 // Load the actual argument out of the pointer VAList
3602 // Load the value as an f64.
3603 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
3604 MachinePointerInfo(), false, false, false, 0);
3605 // Round the value down to an f32.
3606 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
3607 DAG.getIntPtrConstant(1));
3608 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
3609 // Merge the rounded value with the chain output of the load.
3610 return DAG.getMergeValues(Ops, DL);
3613 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
3617 SDValue ARM64TargetLowering::LowerFRAMEADDR(SDValue Op,
3618 SelectionDAG &DAG) const {
3619 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3620 MFI->setFrameAddressIsTaken(true);
3622 EVT VT = Op.getValueType();
3624 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3625 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, ARM64::FP, VT);
3627 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
3628 MachinePointerInfo(), false, false, false, 0);
3632 // FIXME? Maybe this could be a TableGen attribute on some registers and
3633 // this table could be generated automatically from RegInfo.
3634 unsigned ARM64TargetLowering::getRegisterByName(const char* RegName,
3636 unsigned Reg = StringSwitch<unsigned>(RegName)
3637 .Case("sp", ARM64::SP)
3641 report_fatal_error("Invalid register name global variable");
3644 SDValue ARM64TargetLowering::LowerRETURNADDR(SDValue Op,
3645 SelectionDAG &DAG) const {
3646 MachineFunction &MF = DAG.getMachineFunction();
3647 MachineFrameInfo *MFI = MF.getFrameInfo();
3648 MFI->setReturnAddressIsTaken(true);
3650 EVT VT = Op.getValueType();
3652 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3654 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3655 SDValue Offset = DAG.getConstant(8, getPointerTy());
3656 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
3657 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
3658 MachinePointerInfo(), false, false, false, 0);
3661 // Return LR, which contains the return address. Mark it an implicit live-in.
3662 unsigned Reg = MF.addLiveIn(ARM64::LR, &ARM64::GPR64RegClass);
3663 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
3666 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3667 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3668 SDValue ARM64TargetLowering::LowerShiftRightParts(SDValue Op,
3669 SelectionDAG &DAG) const {
3670 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3671 EVT VT = Op.getValueType();
3672 unsigned VTBits = VT.getSizeInBits();
3674 SDValue ShOpLo = Op.getOperand(0);
3675 SDValue ShOpHi = Op.getOperand(1);
3676 SDValue ShAmt = Op.getOperand(2);
3678 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3680 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3682 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3683 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3684 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3685 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3686 DAG.getConstant(VTBits, MVT::i64));
3687 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3689 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3690 ISD::SETGE, dl, DAG);
3691 SDValue CCVal = DAG.getConstant(ARM64CC::GE, MVT::i32);
3693 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3694 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3696 DAG.getNode(ARM64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3698 // ARM64 shifts larger than the register width are wrapped rather than
3699 // clamped, so we can't just emit "hi >> x".
3700 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3701 SDValue TrueValHi = Opc == ISD::SRA
3702 ? DAG.getNode(Opc, dl, VT, ShOpHi,
3703 DAG.getConstant(VTBits - 1, MVT::i64))
3704 : DAG.getConstant(0, VT);
3706 DAG.getNode(ARM64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
3708 SDValue Ops[2] = { Lo, Hi };
3709 return DAG.getMergeValues(Ops, dl);
3712 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3713 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3714 SDValue ARM64TargetLowering::LowerShiftLeftParts(SDValue Op,
3715 SelectionDAG &DAG) const {
3716 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3717 EVT VT = Op.getValueType();
3718 unsigned VTBits = VT.getSizeInBits();
3720 SDValue ShOpLo = Op.getOperand(0);
3721 SDValue ShOpHi = Op.getOperand(1);
3722 SDValue ShAmt = Op.getOperand(2);
3725 assert(Op.getOpcode() == ISD::SHL_PARTS);
3726 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3727 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3728 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3729 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3730 DAG.getConstant(VTBits, MVT::i64));
3731 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3732 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3734 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3736 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3737 ISD::SETGE, dl, DAG);
3738 SDValue CCVal = DAG.getConstant(ARM64CC::GE, MVT::i32);
3739 SDValue Hi = DAG.getNode(ARM64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
3741 // ARM64 shifts of larger than register sizes are wrapped rather than clamped,
3742 // so we can't just emit "lo << a" if a is too big.
3743 SDValue TrueValLo = DAG.getConstant(0, VT);
3744 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3746 DAG.getNode(ARM64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3748 SDValue Ops[2] = { Lo, Hi };
3749 return DAG.getMergeValues(Ops, dl);
3753 ARM64TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3754 // The ARM64 target doesn't support folding offsets into global addresses.
3758 bool ARM64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3759 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
3760 // FIXME: We should be able to handle f128 as well with a clever lowering.
3761 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
3765 return ARM64_AM::getFP64Imm(Imm) != -1;
3766 else if (VT == MVT::f32)
3767 return ARM64_AM::getFP32Imm(Imm) != -1;
3771 //===----------------------------------------------------------------------===//
3772 // ARM64 Optimization Hooks
3773 //===----------------------------------------------------------------------===//
3775 //===----------------------------------------------------------------------===//
3776 // ARM64 Inline Assembly Support
3777 //===----------------------------------------------------------------------===//
3779 // Table of Constraints
3780 // TODO: This is the current set of constraints supported by ARM for the
3781 // compiler, not all of them may make sense, e.g. S may be difficult to support.
3783 // r - A general register
3784 // w - An FP/SIMD register of some size in the range v0-v31
3785 // x - An FP/SIMD register of some size in the range v0-v15
3786 // I - Constant that can be used with an ADD instruction
3787 // J - Constant that can be used with a SUB instruction
3788 // K - Constant that can be used with a 32-bit logical instruction
3789 // L - Constant that can be used with a 64-bit logical instruction
3790 // M - Constant that can be used as a 32-bit MOV immediate
3791 // N - Constant that can be used as a 64-bit MOV immediate
3792 // Q - A memory reference with base register and no offset
3793 // S - A symbolic address
3794 // Y - Floating point constant zero
3795 // Z - Integer constant zero
3797 // Note that general register operands will be output using their 64-bit x
3798 // register name, whatever the size of the variable, unless the asm operand
3799 // is prefixed by the %w modifier. Floating-point and SIMD register operands
3800 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
3803 /// getConstraintType - Given a constraint letter, return the type of
3804 /// constraint it is for this target.
3805 ARM64TargetLowering::ConstraintType
3806 ARM64TargetLowering::getConstraintType(const std::string &Constraint) const {
3807 if (Constraint.size() == 1) {
3808 switch (Constraint[0]) {
3815 return C_RegisterClass;
3816 // An address with a single base register. Due to the way we
3817 // currently handle addresses it is the same as 'r'.
3822 return TargetLowering::getConstraintType(Constraint);
3825 /// Examine constraint type and operand type and determine a weight value.
3826 /// This object must already have been set up with the operand type
3827 /// and the current alternative constraint selected.
3828 TargetLowering::ConstraintWeight
3829 ARM64TargetLowering::getSingleConstraintMatchWeight(
3830 AsmOperandInfo &info, const char *constraint) const {
3831 ConstraintWeight weight = CW_Invalid;
3832 Value *CallOperandVal = info.CallOperandVal;
3833 // If we don't have a value, we can't do a match,
3834 // but allow it at the lowest weight.
3835 if (!CallOperandVal)
3837 Type *type = CallOperandVal->getType();
3838 // Look at the constraint type.
3839 switch (*constraint) {
3841 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3845 if (type->isFloatingPointTy() || type->isVectorTy())
3846 weight = CW_Register;
3849 weight = CW_Constant;
3855 std::pair<unsigned, const TargetRegisterClass *>
3856 ARM64TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3858 if (Constraint.size() == 1) {
3859 switch (Constraint[0]) {
3861 if (VT.getSizeInBits() == 64)
3862 return std::make_pair(0U, &ARM64::GPR64commonRegClass);
3863 return std::make_pair(0U, &ARM64::GPR32commonRegClass);
3866 return std::make_pair(0U, &ARM64::FPR32RegClass);
3867 if (VT.getSizeInBits() == 64)
3868 return std::make_pair(0U, &ARM64::FPR64RegClass);
3869 if (VT.getSizeInBits() == 128)
3870 return std::make_pair(0U, &ARM64::FPR128RegClass);
3872 // The instructions that this constraint is designed for can
3873 // only take 128-bit registers so just use that regclass.
3875 if (VT.getSizeInBits() == 128)
3876 return std::make_pair(0U, &ARM64::FPR128_loRegClass);
3880 if (StringRef("{cc}").equals_lower(Constraint))
3881 return std::make_pair(unsigned(ARM64::NZCV), &ARM64::CCRRegClass);
3883 // Use the default implementation in TargetLowering to convert the register
3884 // constraint into a member of a register class.
3885 std::pair<unsigned, const TargetRegisterClass *> Res;
3886 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3888 // Not found as a standard register?
3890 unsigned Size = Constraint.size();
3891 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
3892 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
3893 const std::string Reg =
3894 std::string(&Constraint[2], &Constraint[Size - 1]);
3895 int RegNo = atoi(Reg.c_str());
3896 if (RegNo >= 0 && RegNo <= 31) {
3897 // v0 - v31 are aliases of q0 - q31.
3898 // By default we'll emit v0-v31 for this unless there's a modifier where
3899 // we'll emit the correct register as well.
3900 Res.first = ARM64::FPR128RegClass.getRegister(RegNo);
3901 Res.second = &ARM64::FPR128RegClass;
3909 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3910 /// vector. If it is invalid, don't add anything to Ops.
3911 void ARM64TargetLowering::LowerAsmOperandForConstraint(
3912 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
3913 SelectionDAG &DAG) const {
3916 // Currently only support length 1 constraints.
3917 if (Constraint.length() != 1)
3920 char ConstraintLetter = Constraint[0];
3921 switch (ConstraintLetter) {
3925 // This set of constraints deal with valid constants for various instructions.
3926 // Validate and return a target constant for them if we can.
3928 // 'z' maps to xzr or wzr so it needs an input of 0.
3929 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3930 if (!C || C->getZExtValue() != 0)
3933 if (Op.getValueType() == MVT::i64)
3934 Result = DAG.getRegister(ARM64::XZR, MVT::i64);
3936 Result = DAG.getRegister(ARM64::WZR, MVT::i32);
3946 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3950 // Grab the value and do some validation.
3951 uint64_t CVal = C->getZExtValue();
3952 switch (ConstraintLetter) {
3953 // The I constraint applies only to simple ADD or SUB immediate operands:
3954 // i.e. 0 to 4095 with optional shift by 12
3955 // The J constraint applies only to ADD or SUB immediates that would be
3956 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
3957 // instruction [or vice versa], in other words -1 to -4095 with optional
3958 // left shift by 12.
3960 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
3964 uint64_t NVal = -C->getSExtValue();
3965 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal))
3969 // The K and L constraints apply *only* to logical immediates, including
3970 // what used to be the MOVI alias for ORR (though the MOVI alias has now
3971 // been removed and MOV should be used). So these constraints have to
3972 // distinguish between bit patterns that are valid 32-bit or 64-bit
3973 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
3974 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
3977 if (ARM64_AM::isLogicalImmediate(CVal, 32))
3981 if (ARM64_AM::isLogicalImmediate(CVal, 64))
3984 // The M and N constraints are a superset of K and L respectively, for use
3985 // with the MOV (immediate) alias. As well as the logical immediates they
3986 // also match 32 or 64-bit immediates that can be loaded either using a
3987 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
3988 // (M) or 64-bit 0x1234000000000000 (N) etc.
3989 // As a note some of this code is liberally stolen from the asm parser.
3991 if (!isUInt<32>(CVal))
3993 if (ARM64_AM::isLogicalImmediate(CVal, 32))
3995 if ((CVal & 0xFFFF) == CVal)
3997 if ((CVal & 0xFFFF0000ULL) == CVal)
3999 uint64_t NCVal = ~(uint32_t)CVal;
4000 if ((NCVal & 0xFFFFULL) == NCVal)
4002 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4007 if (ARM64_AM::isLogicalImmediate(CVal, 64))
4009 if ((CVal & 0xFFFFULL) == CVal)
4011 if ((CVal & 0xFFFF0000ULL) == CVal)
4013 if ((CVal & 0xFFFF00000000ULL) == CVal)
4015 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4017 uint64_t NCVal = ~CVal;
4018 if ((NCVal & 0xFFFFULL) == NCVal)
4020 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4022 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4024 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4032 // All assembler immediates are 64-bit integers.
4033 Result = DAG.getTargetConstant(CVal, MVT::i64);
4037 if (Result.getNode()) {
4038 Ops.push_back(Result);
4042 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4045 //===----------------------------------------------------------------------===//
4046 // ARM64 Advanced SIMD Support
4047 //===----------------------------------------------------------------------===//
4049 /// WidenVector - Given a value in the V64 register class, produce the
4050 /// equivalent value in the V128 register class.
4051 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4052 EVT VT = V64Reg.getValueType();
4053 unsigned NarrowSize = VT.getVectorNumElements();
4054 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4055 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4058 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4059 V64Reg, DAG.getConstant(0, MVT::i32));
4062 /// getExtFactor - Determine the adjustment factor for the position when
4063 /// generating an "extract from vector registers" instruction.
4064 static unsigned getExtFactor(SDValue &V) {
4065 EVT EltType = V.getValueType().getVectorElementType();
4066 return EltType.getSizeInBits() / 8;
4069 /// NarrowVector - Given a value in the V128 register class, produce the
4070 /// equivalent value in the V64 register class.
4071 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4072 EVT VT = V128Reg.getValueType();
4073 unsigned WideSize = VT.getVectorNumElements();
4074 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4075 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4078 return DAG.getTargetExtractSubreg(ARM64::dsub, DL, NarrowTy, V128Reg);
4081 // Gather data to see if the operation can be modelled as a
4082 // shuffle in combination with VEXTs.
4083 SDValue ARM64TargetLowering::ReconstructShuffle(SDValue Op,
4084 SelectionDAG &DAG) const {
4086 EVT VT = Op.getValueType();
4087 unsigned NumElts = VT.getVectorNumElements();
4089 SmallVector<SDValue, 2> SourceVecs;
4090 SmallVector<unsigned, 2> MinElts;
4091 SmallVector<unsigned, 2> MaxElts;
4093 for (unsigned i = 0; i < NumElts; ++i) {
4094 SDValue V = Op.getOperand(i);
4095 if (V.getOpcode() == ISD::UNDEF)
4097 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4098 // A shuffle can only come from building a vector from various
4099 // elements of other vectors.
4103 // Record this extraction against the appropriate vector if possible...
4104 SDValue SourceVec = V.getOperand(0);
4105 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4106 bool FoundSource = false;
4107 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4108 if (SourceVecs[j] == SourceVec) {
4109 if (MinElts[j] > EltNo)
4111 if (MaxElts[j] < EltNo)
4118 // Or record a new source if not...
4120 SourceVecs.push_back(SourceVec);
4121 MinElts.push_back(EltNo);
4122 MaxElts.push_back(EltNo);
4126 // Currently only do something sane when at most two source vectors
4128 if (SourceVecs.size() > 2)
4131 SDValue ShuffleSrcs[2] = { DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4132 int VEXTOffsets[2] = { 0, 0 };
4134 // This loop extracts the usage patterns of the source vectors
4135 // and prepares appropriate SDValues for a shuffle if possible.
4136 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4137 if (SourceVecs[i].getValueType() == VT) {
4138 // No VEXT necessary
4139 ShuffleSrcs[i] = SourceVecs[i];
4142 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4143 // We can pad out the smaller vector for free, so if it's part of a
4145 ShuffleSrcs[i] = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, SourceVecs[i],
4146 DAG.getUNDEF(SourceVecs[i].getValueType()));
4150 // Don't attempt to extract subvectors from BUILD_VECTOR sources
4151 // that expand or trunc the original value.
4152 // TODO: We can try to bitcast and ANY_EXTEND the result but
4153 // we need to consider the cost of vector ANY_EXTEND, and the
4154 // legality of all the types.
4155 if (SourceVecs[i].getValueType().getVectorElementType() !=
4156 VT.getVectorElementType())
4159 // Since only 64-bit and 128-bit vectors are legal on ARM and
4160 // we've eliminated the other cases...
4161 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2 * NumElts &&
4162 "unexpected vector sizes in ReconstructShuffle");
4164 if (MaxElts[i] - MinElts[i] >= NumElts) {
4165 // Span too large for a VEXT to cope
4169 if (MinElts[i] >= NumElts) {
4170 // The extraction can just take the second half
4171 VEXTOffsets[i] = NumElts;
4173 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SourceVecs[i],
4174 DAG.getIntPtrConstant(NumElts));
4175 } else if (MaxElts[i] < NumElts) {
4176 // The extraction can just take the first half
4178 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4179 SourceVecs[i], DAG.getIntPtrConstant(0));
4181 // An actual VEXT is needed
4182 VEXTOffsets[i] = MinElts[i];
4183 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4184 SourceVecs[i], DAG.getIntPtrConstant(0));
4186 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SourceVecs[i],
4187 DAG.getIntPtrConstant(NumElts));
4188 unsigned Imm = VEXTOffsets[i] * getExtFactor(VEXTSrc1);
4189 ShuffleSrcs[i] = DAG.getNode(ARM64ISD::EXT, dl, VT, VEXTSrc1, VEXTSrc2,
4190 DAG.getConstant(Imm, MVT::i32));
4194 SmallVector<int, 8> Mask;
4196 for (unsigned i = 0; i < NumElts; ++i) {
4197 SDValue Entry = Op.getOperand(i);
4198 if (Entry.getOpcode() == ISD::UNDEF) {
4203 SDValue ExtractVec = Entry.getOperand(0);
4205 cast<ConstantSDNode>(Op.getOperand(i).getOperand(1))->getSExtValue();
4206 if (ExtractVec == SourceVecs[0]) {
4207 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4209 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4213 // Final check before we try to produce nonsense...
4214 if (isShuffleMaskLegal(Mask, VT))
4215 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4221 // check if an EXT instruction can handle the shuffle mask when the
4222 // vector sources of the shuffle are the same.
4223 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4224 unsigned NumElts = VT.getVectorNumElements();
4226 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4232 // If this is a VEXT shuffle, the immediate value is the index of the first
4233 // element. The other shuffle indices must be the successive elements after
4235 unsigned ExpectedElt = Imm;
4236 for (unsigned i = 1; i < NumElts; ++i) {
4237 // Increment the expected index. If it wraps around, just follow it
4238 // back to index zero and keep going.
4240 if (ExpectedElt == NumElts)
4244 continue; // ignore UNDEF indices
4245 if (ExpectedElt != static_cast<unsigned>(M[i]))
4252 // check if an EXT instruction can handle the shuffle mask when the
4253 // vector sources of the shuffle are different.
4254 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4256 // Look for the first non-undef element.
4257 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4258 [](int Elt) {return Elt >= 0;});
4260 // Benefit form APInt to handle overflow when calculating expected element.
4261 unsigned NumElts = VT.getVectorNumElements();
4262 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4263 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4264 // The following shuffle indices must be the successive elements after the
4265 // first real element.
4266 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4267 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4268 if (FirstWrongElt != M.end())
4271 // The index of an EXT is the first element if it is not UNDEF.
4272 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4273 // value of the first element. E.g.
4274 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4275 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4276 // ExpectedElt is the last mask index plus 1.
4277 Imm = ExpectedElt.getZExtValue();
4279 // There are two difference cases requiring to reverse input vectors.
4280 // For example, for vector <4 x i32> we have the following cases,
4281 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4282 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4283 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4284 // to reverse two input vectors.
4293 /// isREVMask - Check if a vector shuffle corresponds to a REV
4294 /// instruction with the specified blocksize. (The order of the elements
4295 /// within each block of the vector is reversed.)
4296 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4297 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4298 "Only possible block sizes for REV are: 16, 32, 64");
4300 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4304 unsigned NumElts = VT.getVectorNumElements();
4305 unsigned BlockElts = M[0] + 1;
4306 // If the first shuffle index is UNDEF, be optimistic.
4308 BlockElts = BlockSize / EltSz;
4310 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4313 for (unsigned i = 0; i < NumElts; ++i) {
4315 continue; // ignore UNDEF indices
4316 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4323 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4324 unsigned NumElts = VT.getVectorNumElements();
4325 WhichResult = (M[0] == 0 ? 0 : 1);
4326 unsigned Idx = WhichResult * NumElts / 2;
4327 for (unsigned i = 0; i != NumElts; i += 2) {
4328 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4329 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4337 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4338 unsigned NumElts = VT.getVectorNumElements();
4339 WhichResult = (M[0] == 0 ? 0 : 1);
4340 for (unsigned i = 0; i != NumElts; ++i) {
4342 continue; // ignore UNDEF indices
4343 if ((unsigned)M[i] != 2 * i + WhichResult)
4350 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4351 unsigned NumElts = VT.getVectorNumElements();
4352 WhichResult = (M[0] == 0 ? 0 : 1);
4353 for (unsigned i = 0; i < NumElts; i += 2) {
4354 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4355 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4361 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4362 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4363 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4364 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4365 unsigned NumElts = VT.getVectorNumElements();
4366 WhichResult = (M[0] == 0 ? 0 : 1);
4367 unsigned Idx = WhichResult * NumElts / 2;
4368 for (unsigned i = 0; i != NumElts; i += 2) {
4369 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4370 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4378 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4379 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4380 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4381 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4382 unsigned Half = VT.getVectorNumElements() / 2;
4383 WhichResult = (M[0] == 0 ? 0 : 1);
4384 for (unsigned j = 0; j != 2; ++j) {
4385 unsigned Idx = WhichResult;
4386 for (unsigned i = 0; i != Half; ++i) {
4387 int MIdx = M[i + j * Half];
4388 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4397 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4398 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4399 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4400 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4401 unsigned NumElts = VT.getVectorNumElements();
4402 WhichResult = (M[0] == 0 ? 0 : 1);
4403 for (unsigned i = 0; i < NumElts; i += 2) {
4404 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4405 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4411 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4412 bool &DstIsLeft, int &Anomaly) {
4413 if (M.size() != static_cast<size_t>(NumInputElements))
4416 int NumLHSMatch = 0, NumRHSMatch = 0;
4417 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4419 for (int i = 0; i < NumInputElements; ++i) {
4429 LastLHSMismatch = i;
4431 if (M[i] == i + NumInputElements)
4434 LastRHSMismatch = i;
4437 if (NumLHSMatch == NumInputElements - 1) {
4439 Anomaly = LastLHSMismatch;
4441 } else if (NumRHSMatch == NumInputElements - 1) {
4443 Anomaly = LastRHSMismatch;
4450 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4451 if (VT.getSizeInBits() != 128)
4454 unsigned NumElts = VT.getVectorNumElements();
4456 for (int I = 0, E = NumElts / 2; I != E; I++) {
4461 int Offset = NumElts / 2;
4462 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4463 if (Mask[I] != I + SplitLHS * Offset)
4470 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4472 EVT VT = Op.getValueType();
4473 SDValue V0 = Op.getOperand(0);
4474 SDValue V1 = Op.getOperand(1);
4475 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4477 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4478 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4481 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4483 if (!isConcatMask(Mask, VT, SplitV0))
4486 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4487 VT.getVectorNumElements() / 2);
4489 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4490 DAG.getConstant(0, MVT::i64));
4492 if (V1.getValueType().getSizeInBits() == 128) {
4493 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4494 DAG.getConstant(0, MVT::i64));
4496 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4499 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4500 /// the specified operations to build the shuffle.
4501 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4502 SDValue RHS, SelectionDAG &DAG,
4504 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4505 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4506 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4509 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4518 OP_VUZPL, // VUZP, left result
4519 OP_VUZPR, // VUZP, right result
4520 OP_VZIPL, // VZIP, left result
4521 OP_VZIPR, // VZIP, right result
4522 OP_VTRNL, // VTRN, left result
4523 OP_VTRNR // VTRN, right result
4526 if (OpNum == OP_COPY) {
4527 if (LHSID == (1 * 9 + 2) * 9 + 3)
4529 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
4533 SDValue OpLHS, OpRHS;
4534 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4535 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4536 EVT VT = OpLHS.getValueType();
4540 llvm_unreachable("Unknown shuffle opcode!");
4542 // VREV divides the vector in half and swaps within the half.
4543 if (VT.getVectorElementType() == MVT::i32 ||
4544 VT.getVectorElementType() == MVT::f32)
4545 return DAG.getNode(ARM64ISD::REV64, dl, VT, OpLHS);
4546 // vrev <4 x i16> -> REV32
4547 if (VT.getVectorElementType() == MVT::i16)
4548 return DAG.getNode(ARM64ISD::REV32, dl, VT, OpLHS);
4549 // vrev <4 x i8> -> REV16
4550 assert(VT.getVectorElementType() == MVT::i8);
4551 return DAG.getNode(ARM64ISD::REV16, dl, VT, OpLHS);
4556 EVT EltTy = VT.getVectorElementType();
4558 if (EltTy == MVT::i8)
4559 Opcode = ARM64ISD::DUPLANE8;
4560 else if (EltTy == MVT::i16)
4561 Opcode = ARM64ISD::DUPLANE16;
4562 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
4563 Opcode = ARM64ISD::DUPLANE32;
4564 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
4565 Opcode = ARM64ISD::DUPLANE64;
4567 llvm_unreachable("Invalid vector element type?");
4569 if (VT.getSizeInBits() == 64)
4570 OpLHS = WidenVector(OpLHS, DAG);
4571 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
4572 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
4577 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
4578 return DAG.getNode(ARM64ISD::EXT, dl, VT, OpLHS, OpRHS,
4579 DAG.getConstant(Imm, MVT::i32));
4582 return DAG.getNode(ARM64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS, OpRHS);
4584 return DAG.getNode(ARM64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS, OpRHS);
4586 return DAG.getNode(ARM64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS, OpRHS);
4588 return DAG.getNode(ARM64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS, OpRHS);
4590 return DAG.getNode(ARM64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS, OpRHS);
4592 return DAG.getNode(ARM64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS, OpRHS);
4596 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
4597 SelectionDAG &DAG) {
4598 // Check to see if we can use the TBL instruction.
4599 SDValue V1 = Op.getOperand(0);
4600 SDValue V2 = Op.getOperand(1);
4603 EVT EltVT = Op.getValueType().getVectorElementType();
4604 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
4606 SmallVector<SDValue, 8> TBLMask;
4607 for (int Val : ShuffleMask) {
4608 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
4609 unsigned Offset = Byte + Val * BytesPerElt;
4610 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
4614 MVT IndexVT = MVT::v8i8;
4615 unsigned IndexLen = 8;
4616 if (Op.getValueType().getSizeInBits() == 128) {
4617 IndexVT = MVT::v16i8;
4621 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
4622 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
4625 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
4627 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
4628 Shuffle = DAG.getNode(
4629 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4630 DAG.getConstant(Intrinsic::arm64_neon_tbl1, MVT::i32), V1Cst,
4631 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4632 makeArrayRef(TBLMask.data(), IndexLen)));
4634 if (IndexLen == 8) {
4635 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
4636 Shuffle = DAG.getNode(
4637 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4638 DAG.getConstant(Intrinsic::arm64_neon_tbl1, MVT::i32), V1Cst,
4639 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4640 makeArrayRef(TBLMask.data(), IndexLen)));
4642 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
4643 // cannot currently represent the register constraints on the input
4645 // Shuffle = DAG.getNode(ARM64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
4646 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4647 // &TBLMask[0], IndexLen));
4648 Shuffle = DAG.getNode(
4649 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4650 DAG.getConstant(Intrinsic::arm64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
4651 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4652 makeArrayRef(TBLMask.data(), IndexLen)));
4655 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
4658 static unsigned getDUPLANEOp(EVT EltType) {
4659 if (EltType == MVT::i8)
4660 return ARM64ISD::DUPLANE8;
4661 if (EltType == MVT::i16)
4662 return ARM64ISD::DUPLANE16;
4663 if (EltType == MVT::i32 || EltType == MVT::f32)
4664 return ARM64ISD::DUPLANE32;
4665 if (EltType == MVT::i64 || EltType == MVT::f64)
4666 return ARM64ISD::DUPLANE64;
4668 llvm_unreachable("Invalid vector element type?");
4671 SDValue ARM64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4672 SelectionDAG &DAG) const {
4674 EVT VT = Op.getValueType();
4676 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4678 // Convert shuffles that are directly supported on NEON to target-specific
4679 // DAG nodes, instead of keeping them as shuffles and matching them again
4680 // during code selection. This is more efficient and avoids the possibility
4681 // of inconsistencies between legalization and selection.
4682 ArrayRef<int> ShuffleMask = SVN->getMask();
4684 SDValue V1 = Op.getOperand(0);
4685 SDValue V2 = Op.getOperand(1);
4687 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
4688 V1.getValueType().getSimpleVT())) {
4689 int Lane = SVN->getSplatIndex();
4690 // If this is undef splat, generate it via "just" vdup, if possible.
4694 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
4695 return DAG.getNode(ARM64ISD::DUP, dl, V1.getValueType(),
4697 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
4698 // constant. If so, we can just reference the lane's definition directly.
4699 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
4700 !isa<ConstantSDNode>(V1.getOperand(Lane)))
4701 return DAG.getNode(ARM64ISD::DUP, dl, VT, V1.getOperand(Lane));
4703 // Otherwise, duplicate from the lane of the input vector.
4704 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
4706 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
4707 // to make a vector of the same size as this SHUFFLE. We can ignore the
4708 // extract entirely, and canonicalise the concat using WidenVector.
4709 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
4710 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
4711 V1 = V1.getOperand(0);
4712 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
4713 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
4714 Lane -= Idx * VT.getVectorNumElements() / 2;
4715 V1 = WidenVector(V1.getOperand(Idx), DAG);
4716 } else if (VT.getSizeInBits() == 64)
4717 V1 = WidenVector(V1, DAG);
4719 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
4722 if (isREVMask(ShuffleMask, VT, 64))
4723 return DAG.getNode(ARM64ISD::REV64, dl, V1.getValueType(), V1, V2);
4724 if (isREVMask(ShuffleMask, VT, 32))
4725 return DAG.getNode(ARM64ISD::REV32, dl, V1.getValueType(), V1, V2);
4726 if (isREVMask(ShuffleMask, VT, 16))
4727 return DAG.getNode(ARM64ISD::REV16, dl, V1.getValueType(), V1, V2);
4729 bool ReverseEXT = false;
4731 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
4734 Imm *= getExtFactor(V1);
4735 return DAG.getNode(ARM64ISD::EXT, dl, V1.getValueType(), V1, V2,
4736 DAG.getConstant(Imm, MVT::i32));
4737 } else if (V2->getOpcode() == ISD::UNDEF &&
4738 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
4739 Imm *= getExtFactor(V1);
4740 return DAG.getNode(ARM64ISD::EXT, dl, V1.getValueType(), V1, V1,
4741 DAG.getConstant(Imm, MVT::i32));
4744 unsigned WhichResult;
4745 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
4746 unsigned Opc = (WhichResult == 0) ? ARM64ISD::ZIP1 : ARM64ISD::ZIP2;
4747 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4749 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
4750 unsigned Opc = (WhichResult == 0) ? ARM64ISD::UZP1 : ARM64ISD::UZP2;
4751 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4753 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
4754 unsigned Opc = (WhichResult == 0) ? ARM64ISD::TRN1 : ARM64ISD::TRN2;
4755 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4758 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4759 unsigned Opc = (WhichResult == 0) ? ARM64ISD::ZIP1 : ARM64ISD::ZIP2;
4760 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4762 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4763 unsigned Opc = (WhichResult == 0) ? ARM64ISD::UZP1 : ARM64ISD::UZP2;
4764 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4766 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4767 unsigned Opc = (WhichResult == 0) ? ARM64ISD::TRN1 : ARM64ISD::TRN2;
4768 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4771 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
4772 if (Concat.getNode())
4777 int NumInputElements = V1.getValueType().getVectorNumElements();
4778 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
4779 SDValue DstVec = DstIsLeft ? V1 : V2;
4780 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
4782 SDValue SrcVec = V1;
4783 int SrcLane = ShuffleMask[Anomaly];
4784 if (SrcLane >= NumInputElements) {
4786 SrcLane -= VT.getVectorNumElements();
4788 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
4790 EVT ScalarVT = VT.getVectorElementType();
4791 if (ScalarVT.getSizeInBits() < 32)
4792 ScalarVT = MVT::i32;
4795 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
4796 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
4800 // If the shuffle is not directly supported and it has 4 elements, use
4801 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4802 unsigned NumElts = VT.getVectorNumElements();
4804 unsigned PFIndexes[4];
4805 for (unsigned i = 0; i != 4; ++i) {
4806 if (ShuffleMask[i] < 0)
4809 PFIndexes[i] = ShuffleMask[i];
4812 // Compute the index in the perfect shuffle table.
4813 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
4814 PFIndexes[2] * 9 + PFIndexes[3];
4815 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4816 unsigned Cost = (PFEntry >> 30);
4819 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4822 return GenerateTBL(Op, ShuffleMask, DAG);
4825 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
4827 EVT VT = BVN->getValueType(0);
4828 APInt SplatBits, SplatUndef;
4829 unsigned SplatBitSize;
4831 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4832 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
4834 for (unsigned i = 0; i < NumSplats; ++i) {
4835 CnstBits <<= SplatBitSize;
4836 UndefBits <<= SplatBitSize;
4837 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
4838 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
4847 SDValue ARM64TargetLowering::LowerVectorAND(SDValue Op,
4848 SelectionDAG &DAG) const {
4849 BuildVectorSDNode *BVN =
4850 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
4851 SDValue LHS = Op.getOperand(0);
4853 EVT VT = Op.getValueType();
4858 APInt CnstBits(VT.getSizeInBits(), 0);
4859 APInt UndefBits(VT.getSizeInBits(), 0);
4860 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
4861 // We only have BIC vector immediate instruction, which is and-not.
4862 CnstBits = ~CnstBits;
4864 // We make use of a little bit of goto ickiness in order to avoid having to
4865 // duplicate the immediate matching logic for the undef toggled case.
4866 bool SecondTry = false;
4869 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
4870 CnstBits = CnstBits.zextOrTrunc(64);
4871 uint64_t CnstVal = CnstBits.getZExtValue();
4873 if (ARM64_AM::isAdvSIMDModImmType1(CnstVal)) {
4874 CnstVal = ARM64_AM::encodeAdvSIMDModImmType1(CnstVal);
4875 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4876 SDValue Mov = DAG.getNode(ARM64ISD::BICi, dl, MovTy, LHS,
4877 DAG.getConstant(CnstVal, MVT::i32),
4878 DAG.getConstant(0, MVT::i32));
4879 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4882 if (ARM64_AM::isAdvSIMDModImmType2(CnstVal)) {
4883 CnstVal = ARM64_AM::encodeAdvSIMDModImmType2(CnstVal);
4884 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4885 SDValue Mov = DAG.getNode(ARM64ISD::BICi, dl, MovTy, LHS,
4886 DAG.getConstant(CnstVal, MVT::i32),
4887 DAG.getConstant(8, MVT::i32));
4888 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4891 if (ARM64_AM::isAdvSIMDModImmType3(CnstVal)) {
4892 CnstVal = ARM64_AM::encodeAdvSIMDModImmType3(CnstVal);
4893 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4894 SDValue Mov = DAG.getNode(ARM64ISD::BICi, dl, MovTy, LHS,
4895 DAG.getConstant(CnstVal, MVT::i32),
4896 DAG.getConstant(16, MVT::i32));
4897 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4900 if (ARM64_AM::isAdvSIMDModImmType4(CnstVal)) {
4901 CnstVal = ARM64_AM::encodeAdvSIMDModImmType4(CnstVal);
4902 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4903 SDValue Mov = DAG.getNode(ARM64ISD::BICi, dl, MovTy, LHS,
4904 DAG.getConstant(CnstVal, MVT::i32),
4905 DAG.getConstant(24, MVT::i32));
4906 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4909 if (ARM64_AM::isAdvSIMDModImmType5(CnstVal)) {
4910 CnstVal = ARM64_AM::encodeAdvSIMDModImmType5(CnstVal);
4911 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4912 SDValue Mov = DAG.getNode(ARM64ISD::BICi, dl, MovTy, LHS,
4913 DAG.getConstant(CnstVal, MVT::i32),
4914 DAG.getConstant(0, MVT::i32));
4915 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4918 if (ARM64_AM::isAdvSIMDModImmType6(CnstVal)) {
4919 CnstVal = ARM64_AM::encodeAdvSIMDModImmType6(CnstVal);
4920 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4921 SDValue Mov = DAG.getNode(ARM64ISD::BICi, dl, MovTy, LHS,
4922 DAG.getConstant(CnstVal, MVT::i32),
4923 DAG.getConstant(8, MVT::i32));
4924 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4931 CnstBits = ~UndefBits;
4935 // We can always fall back to a non-immediate AND.
4940 // Specialized code to quickly find if PotentialBVec is a BuildVector that
4941 // consists of only the same constant int value, returned in reference arg
4943 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
4944 uint64_t &ConstVal) {
4945 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
4948 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
4951 EVT VT = Bvec->getValueType(0);
4952 unsigned NumElts = VT.getVectorNumElements();
4953 for (unsigned i = 1; i < NumElts; ++i)
4954 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
4956 ConstVal = FirstElt->getZExtValue();
4960 static unsigned getIntrinsicID(const SDNode *N) {
4961 unsigned Opcode = N->getOpcode();
4964 return Intrinsic::not_intrinsic;
4965 case ISD::INTRINSIC_WO_CHAIN: {
4966 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4967 if (IID < Intrinsic::num_intrinsics)
4969 return Intrinsic::not_intrinsic;
4974 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
4975 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
4976 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
4977 // Also, logical shift right -> sri, with the same structure.
4978 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
4979 EVT VT = N->getValueType(0);
4986 // Is the first op an AND?
4987 const SDValue And = N->getOperand(0);
4988 if (And.getOpcode() != ISD::AND)
4991 // Is the second op an shl or lshr?
4992 SDValue Shift = N->getOperand(1);
4993 // This will have been turned into: ARM64ISD::VSHL vector, #shift
4994 // or ARM64ISD::VLSHR vector, #shift
4995 unsigned ShiftOpc = Shift.getOpcode();
4996 if ((ShiftOpc != ARM64ISD::VSHL && ShiftOpc != ARM64ISD::VLSHR))
4998 bool IsShiftRight = ShiftOpc == ARM64ISD::VLSHR;
5000 // Is the shift amount constant?
5001 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5005 // Is the and mask vector all constant?
5007 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5010 // Is C1 == ~C2, taking into account how much one can shift elements of a
5012 uint64_t C2 = C2node->getZExtValue();
5013 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5014 if (C2 > ElemSizeInBits)
5016 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5017 if ((C1 & ElemMask) != (~C2 & ElemMask))
5020 SDValue X = And.getOperand(0);
5021 SDValue Y = Shift.getOperand(0);
5024 IsShiftRight ? Intrinsic::arm64_neon_vsri : Intrinsic::arm64_neon_vsli;
5026 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5027 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5029 DEBUG(dbgs() << "arm64-lower: transformed: \n");
5030 DEBUG(N->dump(&DAG));
5031 DEBUG(dbgs() << "into: \n");
5032 DEBUG(ResultSLI->dump(&DAG));
5038 SDValue ARM64TargetLowering::LowerVectorOR(SDValue Op,
5039 SelectionDAG &DAG) const {
5040 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5041 if (EnableARM64SlrGeneration) {
5042 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5047 BuildVectorSDNode *BVN =
5048 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5049 SDValue LHS = Op.getOperand(1);
5051 EVT VT = Op.getValueType();
5053 // OR commutes, so try swapping the operands.
5055 LHS = Op.getOperand(0);
5056 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5061 APInt CnstBits(VT.getSizeInBits(), 0);
5062 APInt UndefBits(VT.getSizeInBits(), 0);
5063 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5064 // We make use of a little bit of goto ickiness in order to avoid having to
5065 // duplicate the immediate matching logic for the undef toggled case.
5066 bool SecondTry = false;
5069 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5070 CnstBits = CnstBits.zextOrTrunc(64);
5071 uint64_t CnstVal = CnstBits.getZExtValue();
5073 if (ARM64_AM::isAdvSIMDModImmType1(CnstVal)) {
5074 CnstVal = ARM64_AM::encodeAdvSIMDModImmType1(CnstVal);
5075 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5076 SDValue Mov = DAG.getNode(ARM64ISD::ORRi, dl, MovTy, LHS,
5077 DAG.getConstant(CnstVal, MVT::i32),
5078 DAG.getConstant(0, MVT::i32));
5079 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5082 if (ARM64_AM::isAdvSIMDModImmType2(CnstVal)) {
5083 CnstVal = ARM64_AM::encodeAdvSIMDModImmType2(CnstVal);
5084 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5085 SDValue Mov = DAG.getNode(ARM64ISD::ORRi, dl, MovTy, LHS,
5086 DAG.getConstant(CnstVal, MVT::i32),
5087 DAG.getConstant(8, MVT::i32));
5088 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5091 if (ARM64_AM::isAdvSIMDModImmType3(CnstVal)) {
5092 CnstVal = ARM64_AM::encodeAdvSIMDModImmType3(CnstVal);
5093 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5094 SDValue Mov = DAG.getNode(ARM64ISD::ORRi, dl, MovTy, LHS,
5095 DAG.getConstant(CnstVal, MVT::i32),
5096 DAG.getConstant(16, MVT::i32));
5097 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5100 if (ARM64_AM::isAdvSIMDModImmType4(CnstVal)) {
5101 CnstVal = ARM64_AM::encodeAdvSIMDModImmType4(CnstVal);
5102 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5103 SDValue Mov = DAG.getNode(ARM64ISD::ORRi, dl, MovTy, LHS,
5104 DAG.getConstant(CnstVal, MVT::i32),
5105 DAG.getConstant(24, MVT::i32));
5106 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5109 if (ARM64_AM::isAdvSIMDModImmType5(CnstVal)) {
5110 CnstVal = ARM64_AM::encodeAdvSIMDModImmType5(CnstVal);
5111 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5112 SDValue Mov = DAG.getNode(ARM64ISD::ORRi, dl, MovTy, LHS,
5113 DAG.getConstant(CnstVal, MVT::i32),
5114 DAG.getConstant(0, MVT::i32));
5115 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5118 if (ARM64_AM::isAdvSIMDModImmType6(CnstVal)) {
5119 CnstVal = ARM64_AM::encodeAdvSIMDModImmType6(CnstVal);
5120 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5121 SDValue Mov = DAG.getNode(ARM64ISD::ORRi, dl, MovTy, LHS,
5122 DAG.getConstant(CnstVal, MVT::i32),
5123 DAG.getConstant(8, MVT::i32));
5124 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5131 CnstBits = UndefBits;
5135 // We can always fall back to a non-immediate OR.
5140 SDValue ARM64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5141 SelectionDAG &DAG) const {
5142 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5144 EVT VT = Op.getValueType();
5146 APInt CnstBits(VT.getSizeInBits(), 0);
5147 APInt UndefBits(VT.getSizeInBits(), 0);
5148 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5149 // We make use of a little bit of goto ickiness in order to avoid having to
5150 // duplicate the immediate matching logic for the undef toggled case.
5151 bool SecondTry = false;
5154 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5155 CnstBits = CnstBits.zextOrTrunc(64);
5156 uint64_t CnstVal = CnstBits.getZExtValue();
5158 // Certain magic vector constants (used to express things like NOT
5159 // and NEG) are passed through unmodified. This allows codegen patterns
5160 // for these operations to match. Special-purpose patterns will lower
5161 // these immediates to MOVIs if it proves necessary.
5162 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5165 // The many faces of MOVI...
5166 if (ARM64_AM::isAdvSIMDModImmType10(CnstVal)) {
5167 CnstVal = ARM64_AM::encodeAdvSIMDModImmType10(CnstVal);
5168 if (VT.getSizeInBits() == 128) {
5169 SDValue Mov = DAG.getNode(ARM64ISD::MOVIedit, dl, MVT::v2i64,
5170 DAG.getConstant(CnstVal, MVT::i32));
5171 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5174 // Support the V64 version via subregister insertion.
5175 SDValue Mov = DAG.getNode(ARM64ISD::MOVIedit, dl, MVT::f64,
5176 DAG.getConstant(CnstVal, MVT::i32));
5177 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5180 if (ARM64_AM::isAdvSIMDModImmType1(CnstVal)) {
5181 CnstVal = ARM64_AM::encodeAdvSIMDModImmType1(CnstVal);
5182 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5183 SDValue Mov = DAG.getNode(ARM64ISD::MOVIshift, dl, MovTy,
5184 DAG.getConstant(CnstVal, MVT::i32),
5185 DAG.getConstant(0, MVT::i32));
5186 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5189 if (ARM64_AM::isAdvSIMDModImmType2(CnstVal)) {
5190 CnstVal = ARM64_AM::encodeAdvSIMDModImmType2(CnstVal);
5191 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5192 SDValue Mov = DAG.getNode(ARM64ISD::MOVIshift, dl, MovTy,
5193 DAG.getConstant(CnstVal, MVT::i32),
5194 DAG.getConstant(8, MVT::i32));
5195 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5198 if (ARM64_AM::isAdvSIMDModImmType3(CnstVal)) {
5199 CnstVal = ARM64_AM::encodeAdvSIMDModImmType3(CnstVal);
5200 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5201 SDValue Mov = DAG.getNode(ARM64ISD::MOVIshift, dl, MovTy,
5202 DAG.getConstant(CnstVal, MVT::i32),
5203 DAG.getConstant(16, MVT::i32));
5204 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5207 if (ARM64_AM::isAdvSIMDModImmType4(CnstVal)) {
5208 CnstVal = ARM64_AM::encodeAdvSIMDModImmType4(CnstVal);
5209 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5210 SDValue Mov = DAG.getNode(ARM64ISD::MOVIshift, dl, MovTy,
5211 DAG.getConstant(CnstVal, MVT::i32),
5212 DAG.getConstant(24, MVT::i32));
5213 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5216 if (ARM64_AM::isAdvSIMDModImmType5(CnstVal)) {
5217 CnstVal = ARM64_AM::encodeAdvSIMDModImmType5(CnstVal);
5218 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5219 SDValue Mov = DAG.getNode(ARM64ISD::MOVIshift, dl, MovTy,
5220 DAG.getConstant(CnstVal, MVT::i32),
5221 DAG.getConstant(0, MVT::i32));
5222 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5225 if (ARM64_AM::isAdvSIMDModImmType6(CnstVal)) {
5226 CnstVal = ARM64_AM::encodeAdvSIMDModImmType6(CnstVal);
5227 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5228 SDValue Mov = DAG.getNode(ARM64ISD::MOVIshift, dl, MovTy,
5229 DAG.getConstant(CnstVal, MVT::i32),
5230 DAG.getConstant(8, MVT::i32));
5231 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5234 if (ARM64_AM::isAdvSIMDModImmType7(CnstVal)) {
5235 CnstVal = ARM64_AM::encodeAdvSIMDModImmType7(CnstVal);
5236 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5237 SDValue Mov = DAG.getNode(ARM64ISD::MOVImsl, dl, MovTy,
5238 DAG.getConstant(CnstVal, MVT::i32),
5239 DAG.getConstant(264, MVT::i32));
5240 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5243 if (ARM64_AM::isAdvSIMDModImmType8(CnstVal)) {
5244 CnstVal = ARM64_AM::encodeAdvSIMDModImmType8(CnstVal);
5245 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5246 SDValue Mov = DAG.getNode(ARM64ISD::MOVImsl, dl, MovTy,
5247 DAG.getConstant(CnstVal, MVT::i32),
5248 DAG.getConstant(272, MVT::i32));
5249 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5252 if (ARM64_AM::isAdvSIMDModImmType9(CnstVal)) {
5253 CnstVal = ARM64_AM::encodeAdvSIMDModImmType9(CnstVal);
5254 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5255 SDValue Mov = DAG.getNode(ARM64ISD::MOVI, dl, MovTy,
5256 DAG.getConstant(CnstVal, MVT::i32));
5257 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5260 // The few faces of FMOV...
5261 if (ARM64_AM::isAdvSIMDModImmType11(CnstVal)) {
5262 CnstVal = ARM64_AM::encodeAdvSIMDModImmType11(CnstVal);
5263 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5264 SDValue Mov = DAG.getNode(ARM64ISD::FMOV, dl, MovTy,
5265 DAG.getConstant(CnstVal, MVT::i32));
5266 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5269 if (ARM64_AM::isAdvSIMDModImmType12(CnstVal) &&
5270 VT.getSizeInBits() == 128) {
5271 CnstVal = ARM64_AM::encodeAdvSIMDModImmType12(CnstVal);
5272 SDValue Mov = DAG.getNode(ARM64ISD::FMOV, dl, MVT::v2f64,
5273 DAG.getConstant(CnstVal, MVT::i32));
5274 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5277 // The many faces of MVNI...
5279 if (ARM64_AM::isAdvSIMDModImmType1(CnstVal)) {
5280 CnstVal = ARM64_AM::encodeAdvSIMDModImmType1(CnstVal);
5281 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5282 SDValue Mov = DAG.getNode(ARM64ISD::MVNIshift, dl, MovTy,
5283 DAG.getConstant(CnstVal, MVT::i32),
5284 DAG.getConstant(0, MVT::i32));
5285 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5288 if (ARM64_AM::isAdvSIMDModImmType2(CnstVal)) {
5289 CnstVal = ARM64_AM::encodeAdvSIMDModImmType2(CnstVal);
5290 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5291 SDValue Mov = DAG.getNode(ARM64ISD::MVNIshift, dl, MovTy,
5292 DAG.getConstant(CnstVal, MVT::i32),
5293 DAG.getConstant(8, MVT::i32));
5294 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5297 if (ARM64_AM::isAdvSIMDModImmType3(CnstVal)) {
5298 CnstVal = ARM64_AM::encodeAdvSIMDModImmType3(CnstVal);
5299 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5300 SDValue Mov = DAG.getNode(ARM64ISD::MVNIshift, dl, MovTy,
5301 DAG.getConstant(CnstVal, MVT::i32),
5302 DAG.getConstant(16, MVT::i32));
5303 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5306 if (ARM64_AM::isAdvSIMDModImmType4(CnstVal)) {
5307 CnstVal = ARM64_AM::encodeAdvSIMDModImmType4(CnstVal);
5308 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5309 SDValue Mov = DAG.getNode(ARM64ISD::MVNIshift, dl, MovTy,
5310 DAG.getConstant(CnstVal, MVT::i32),
5311 DAG.getConstant(24, MVT::i32));
5312 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5315 if (ARM64_AM::isAdvSIMDModImmType5(CnstVal)) {
5316 CnstVal = ARM64_AM::encodeAdvSIMDModImmType5(CnstVal);
5317 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5318 SDValue Mov = DAG.getNode(ARM64ISD::MVNIshift, dl, MovTy,
5319 DAG.getConstant(CnstVal, MVT::i32),
5320 DAG.getConstant(0, MVT::i32));
5321 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5324 if (ARM64_AM::isAdvSIMDModImmType6(CnstVal)) {
5325 CnstVal = ARM64_AM::encodeAdvSIMDModImmType6(CnstVal);
5326 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5327 SDValue Mov = DAG.getNode(ARM64ISD::MVNIshift, dl, MovTy,
5328 DAG.getConstant(CnstVal, MVT::i32),
5329 DAG.getConstant(8, MVT::i32));
5330 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5333 if (ARM64_AM::isAdvSIMDModImmType7(CnstVal)) {
5334 CnstVal = ARM64_AM::encodeAdvSIMDModImmType7(CnstVal);
5335 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5336 SDValue Mov = DAG.getNode(ARM64ISD::MVNImsl, dl, MovTy,
5337 DAG.getConstant(CnstVal, MVT::i32),
5338 DAG.getConstant(264, MVT::i32));
5339 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5342 if (ARM64_AM::isAdvSIMDModImmType8(CnstVal)) {
5343 CnstVal = ARM64_AM::encodeAdvSIMDModImmType8(CnstVal);
5344 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5345 SDValue Mov = DAG.getNode(ARM64ISD::MVNImsl, dl, MovTy,
5346 DAG.getConstant(CnstVal, MVT::i32),
5347 DAG.getConstant(272, MVT::i32));
5348 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5355 CnstBits = UndefBits;
5360 // Scan through the operands to find some interesting properties we can
5362 // 1) If only one value is used, we can use a DUP, or
5363 // 2) if only the low element is not undef, we can just insert that, or
5364 // 3) if only one constant value is used (w/ some non-constant lanes),
5365 // we can splat the constant value into the whole vector then fill
5366 // in the non-constant lanes.
5367 // 4) FIXME: If different constant values are used, but we can intelligently
5368 // select the values we'll be overwriting for the non-constant
5369 // lanes such that we can directly materialize the vector
5370 // some other way (MOVI, e.g.), we can be sneaky.
5371 unsigned NumElts = VT.getVectorNumElements();
5372 bool isOnlyLowElement = true;
5373 bool usesOnlyOneValue = true;
5374 bool usesOnlyOneConstantValue = true;
5375 bool isConstant = true;
5376 unsigned NumConstantLanes = 0;
5378 SDValue ConstantValue;
5379 for (unsigned i = 0; i < NumElts; ++i) {
5380 SDValue V = Op.getOperand(i);
5381 if (V.getOpcode() == ISD::UNDEF)
5384 isOnlyLowElement = false;
5385 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5388 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5390 if (!ConstantValue.getNode())
5392 else if (ConstantValue != V)
5393 usesOnlyOneConstantValue = false;
5396 if (!Value.getNode())
5398 else if (V != Value)
5399 usesOnlyOneValue = false;
5402 if (!Value.getNode())
5403 return DAG.getUNDEF(VT);
5405 if (isOnlyLowElement)
5406 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5408 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5409 // i32 and try again.
5410 if (usesOnlyOneValue) {
5412 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5413 Value.getValueType() != VT)
5414 return DAG.getNode(ARM64ISD::DUP, dl, VT, Value);
5416 // This is actually a DUPLANExx operation, which keeps everything vectory.
5418 // DUPLANE works on 128-bit vectors, widen it if necessary.
5419 SDValue Lane = Value.getOperand(1);
5420 Value = Value.getOperand(0);
5421 if (Value.getValueType().getSizeInBits() == 64)
5422 Value = WidenVector(Value, DAG);
5424 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5425 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5428 if (VT.getVectorElementType().isFloatingPoint()) {
5429 SmallVector<SDValue, 8> Ops;
5431 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
5432 for (unsigned i = 0; i < NumElts; ++i)
5433 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5434 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5435 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5436 Val = LowerBUILD_VECTOR(Val, DAG);
5438 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5442 // If there was only one constant value used and for more than one lane,
5443 // start by splatting that value, then replace the non-constant lanes. This
5444 // is better than the default, which will perform a separate initialization
5446 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5447 SDValue Val = DAG.getNode(ARM64ISD::DUP, dl, VT, ConstantValue);
5448 // Now insert the non-constant lanes.
5449 for (unsigned i = 0; i < NumElts; ++i) {
5450 SDValue V = Op.getOperand(i);
5451 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5452 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5453 // Note that type legalization likely mucked about with the VT of the
5454 // source operand, so we may have to convert it here before inserting.
5455 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5461 // If all elements are constants and the case above didn't get hit, fall back
5462 // to the default expansion, which will generate a load from the constant
5467 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5469 SDValue shuffle = ReconstructShuffle(Op, DAG);
5470 if (shuffle != SDValue())
5474 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5475 // know the default expansion would otherwise fall back on something even
5476 // worse. For a vector with one or two non-undef values, that's
5477 // scalar_to_vector for the elements followed by a shuffle (provided the
5478 // shuffle is valid for the target) and materialization element by element
5479 // on the stack followed by a load for everything else.
5480 if (!isConstant && !usesOnlyOneValue) {
5481 SDValue Vec = DAG.getUNDEF(VT);
5482 SDValue Op0 = Op.getOperand(0);
5483 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5485 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
5486 // a) Avoid a RMW dependency on the full vector register, and
5487 // b) Allow the register coalescer to fold away the copy if the
5488 // value is already in an S or D register.
5489 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
5490 unsigned SubIdx = ElemSize == 32 ? ARM64::ssub : ARM64::dsub;
5492 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
5493 DAG.getTargetConstant(SubIdx, MVT::i32));
5494 Vec = SDValue(N, 0);
5497 for (; i < NumElts; ++i) {
5498 SDValue V = Op.getOperand(i);
5499 if (V.getOpcode() == ISD::UNDEF)
5501 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5502 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5507 // Just use the default expansion. We failed to find a better alternative.
5511 SDValue ARM64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
5512 SelectionDAG &DAG) const {
5513 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
5515 // Check for non-constant lane.
5516 if (!isa<ConstantSDNode>(Op.getOperand(2)))
5519 EVT VT = Op.getOperand(0).getValueType();
5521 // Insertion/extraction are legal for V128 types.
5522 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5523 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5526 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5527 VT != MVT::v1i64 && VT != MVT::v2f32)
5530 // For V64 types, we perform insertion by expanding the value
5531 // to a V128 type and perform the insertion on that.
5533 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5534 EVT WideTy = WideVec.getValueType();
5536 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
5537 Op.getOperand(1), Op.getOperand(2));
5538 // Re-narrow the resultant vector.
5539 return NarrowVector(Node, DAG);
5542 SDValue ARM64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5543 SelectionDAG &DAG) const {
5544 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
5546 // Check for non-constant lane.
5547 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5550 EVT VT = Op.getOperand(0).getValueType();
5552 // Insertion/extraction are legal for V128 types.
5553 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5554 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5557 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5558 VT != MVT::v1i64 && VT != MVT::v2f32)
5561 // For V64 types, we perform extraction by expanding the value
5562 // to a V128 type and perform the extraction on that.
5564 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5565 EVT WideTy = WideVec.getValueType();
5567 EVT ExtrTy = WideTy.getVectorElementType();
5568 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
5571 // For extractions, we just return the result directly.
5572 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
5576 SDValue ARM64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
5577 SelectionDAG &DAG) const {
5578 EVT VT = Op.getOperand(0).getValueType();
5584 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5587 unsigned Val = Cst->getZExtValue();
5589 unsigned Size = Op.getValueType().getSizeInBits();
5593 return DAG.getTargetExtractSubreg(ARM64::bsub, dl, Op.getValueType(),
5596 return DAG.getTargetExtractSubreg(ARM64::hsub, dl, Op.getValueType(),
5599 return DAG.getTargetExtractSubreg(ARM64::ssub, dl, Op.getValueType(),
5602 return DAG.getTargetExtractSubreg(ARM64::dsub, dl, Op.getValueType(),
5605 llvm_unreachable("Unexpected vector type in extract_subvector!");
5608 // If this is extracting the upper 64-bits of a 128-bit vector, we match
5610 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
5616 bool ARM64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5618 if (VT.getVectorNumElements() == 4 &&
5619 (VT.is128BitVector() || VT.is64BitVector())) {
5620 unsigned PFIndexes[4];
5621 for (unsigned i = 0; i != 4; ++i) {
5625 PFIndexes[i] = M[i];
5628 // Compute the index in the perfect shuffle table.
5629 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5630 PFIndexes[2] * 9 + PFIndexes[3];
5631 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5632 unsigned Cost = (PFEntry >> 30);
5640 unsigned DummyUnsigned;
5642 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
5643 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
5644 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
5645 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
5646 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
5647 isZIPMask(M, VT, DummyUnsigned) ||
5648 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
5649 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
5650 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
5651 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
5652 isConcatMask(M, VT, VT.getSizeInBits() == 128));
5655 /// getVShiftImm - Check if this is a valid build_vector for the immediate
5656 /// operand of a vector shift operation, where all the elements of the
5657 /// build_vector must have the same constant integer value.
5658 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
5659 // Ignore bit_converts.
5660 while (Op.getOpcode() == ISD::BITCAST)
5661 Op = Op.getOperand(0);
5662 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5663 APInt SplatBits, SplatUndef;
5664 unsigned SplatBitSize;
5666 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5667 HasAnyUndefs, ElementBits) ||
5668 SplatBitSize > ElementBits)
5670 Cnt = SplatBits.getSExtValue();
5674 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5675 /// operand of a vector shift left operation. That value must be in the range:
5676 /// 0 <= Value < ElementBits for a left shift; or
5677 /// 0 <= Value <= ElementBits for a long left shift.
5678 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5679 assert(VT.isVector() && "vector shift count is not a vector type");
5680 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5681 if (!getVShiftImm(Op, ElementBits, Cnt))
5683 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
5686 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5687 /// operand of a vector shift right operation. For a shift opcode, the value
5688 /// is positive, but for an intrinsic the value count must be negative. The
5689 /// absolute value must be in the range:
5690 /// 1 <= |Value| <= ElementBits for a right shift; or
5691 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5692 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5694 assert(VT.isVector() && "vector shift count is not a vector type");
5695 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5696 if (!getVShiftImm(Op, ElementBits, Cnt))
5700 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
5703 SDValue ARM64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
5704 SelectionDAG &DAG) const {
5705 EVT VT = Op.getValueType();
5709 if (!Op.getOperand(1).getValueType().isVector())
5711 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5713 switch (Op.getOpcode()) {
5715 llvm_unreachable("unexpected shift opcode");
5718 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
5719 return DAG.getNode(ARM64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
5720 DAG.getConstant(Cnt, MVT::i32));
5721 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5722 DAG.getConstant(Intrinsic::arm64_neon_ushl, MVT::i32),
5723 Op.getOperand(0), Op.getOperand(1));
5726 // Right shift immediate
5727 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
5730 (Op.getOpcode() == ISD::SRA) ? ARM64ISD::VASHR : ARM64ISD::VLSHR;
5731 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
5732 DAG.getConstant(Cnt, MVT::i32));
5735 // Right shift register. Note, there is not a shift right register
5736 // instruction, but the shift left register instruction takes a signed
5737 // value, where negative numbers specify a right shift.
5738 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::arm64_neon_sshl
5739 : Intrinsic::arm64_neon_ushl;
5740 // negate the shift amount
5741 SDValue NegShift = DAG.getNode(ARM64ISD::NEG, DL, VT, Op.getOperand(1));
5742 SDValue NegShiftLeft =
5743 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5744 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
5745 return NegShiftLeft;
5751 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
5752 ARM64CC::CondCode CC, bool NoNans, EVT VT,
5753 SDLoc dl, SelectionDAG &DAG) {
5754 EVT SrcVT = LHS.getValueType();
5756 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
5757 APInt CnstBits(VT.getSizeInBits(), 0);
5758 APInt UndefBits(VT.getSizeInBits(), 0);
5759 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
5760 bool IsZero = IsCnst && (CnstBits == 0);
5762 if (SrcVT.getVectorElementType().isFloatingPoint()) {
5769 Fcmeq = DAG.getNode(ARM64ISD::FCMEQz, dl, VT, LHS);
5771 Fcmeq = DAG.getNode(ARM64ISD::FCMEQ, dl, VT, LHS, RHS);
5772 return DAG.getNode(ARM64ISD::NOT, dl, VT, Fcmeq);
5776 return DAG.getNode(ARM64ISD::FCMEQz, dl, VT, LHS);
5777 return DAG.getNode(ARM64ISD::FCMEQ, dl, VT, LHS, RHS);
5780 return DAG.getNode(ARM64ISD::FCMGEz, dl, VT, LHS);
5781 return DAG.getNode(ARM64ISD::FCMGE, dl, VT, LHS, RHS);
5784 return DAG.getNode(ARM64ISD::FCMGTz, dl, VT, LHS);
5785 return DAG.getNode(ARM64ISD::FCMGT, dl, VT, LHS, RHS);
5788 return DAG.getNode(ARM64ISD::FCMLEz, dl, VT, LHS);
5789 return DAG.getNode(ARM64ISD::FCMGE, dl, VT, RHS, LHS);
5793 // If we ignore NaNs then we can use to the MI implementation.
5797 return DAG.getNode(ARM64ISD::FCMLTz, dl, VT, LHS);
5798 return DAG.getNode(ARM64ISD::FCMGT, dl, VT, RHS, LHS);
5808 Cmeq = DAG.getNode(ARM64ISD::CMEQz, dl, VT, LHS);
5810 Cmeq = DAG.getNode(ARM64ISD::CMEQ, dl, VT, LHS, RHS);
5811 return DAG.getNode(ARM64ISD::NOT, dl, VT, Cmeq);
5815 return DAG.getNode(ARM64ISD::CMEQz, dl, VT, LHS);
5816 return DAG.getNode(ARM64ISD::CMEQ, dl, VT, LHS, RHS);
5819 return DAG.getNode(ARM64ISD::CMGEz, dl, VT, LHS);
5820 return DAG.getNode(ARM64ISD::CMGE, dl, VT, LHS, RHS);
5823 return DAG.getNode(ARM64ISD::CMGTz, dl, VT, LHS);
5824 return DAG.getNode(ARM64ISD::CMGT, dl, VT, LHS, RHS);
5827 return DAG.getNode(ARM64ISD::CMLEz, dl, VT, LHS);
5828 return DAG.getNode(ARM64ISD::CMGE, dl, VT, RHS, LHS);
5830 return DAG.getNode(ARM64ISD::CMHS, dl, VT, RHS, LHS);
5832 return DAG.getNode(ARM64ISD::CMHI, dl, VT, RHS, LHS);
5835 return DAG.getNode(ARM64ISD::CMLTz, dl, VT, LHS);
5836 return DAG.getNode(ARM64ISD::CMGT, dl, VT, RHS, LHS);
5838 return DAG.getNode(ARM64ISD::CMHI, dl, VT, LHS, RHS);
5840 return DAG.getNode(ARM64ISD::CMHS, dl, VT, LHS, RHS);
5844 SDValue ARM64TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
5845 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5846 SDValue LHS = Op.getOperand(0);
5847 SDValue RHS = Op.getOperand(1);
5850 if (LHS.getValueType().getVectorElementType().isInteger()) {
5851 assert(LHS.getValueType() == RHS.getValueType());
5852 ARM64CC::CondCode ARM64CC = changeIntCCToARM64CC(CC);
5853 return EmitVectorComparison(LHS, RHS, ARM64CC, false, Op.getValueType(), dl,
5857 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
5858 LHS.getValueType().getVectorElementType() == MVT::f64);
5860 // Unfortunately, the mapping of LLVM FP CC's onto ARM64 CC's isn't totally
5861 // clean. Some of them require two branches to implement.
5862 ARM64CC::CondCode CC1, CC2;
5864 changeVectorFPCCToARM64CC(CC, CC1, CC2, ShouldInvert);
5866 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
5868 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG);
5872 if (CC2 != ARM64CC::AL) {
5874 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG);
5875 if (!Cmp2.getNode())
5878 Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2);
5882 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
5887 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
5888 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
5889 /// specified in the intrinsic calls.
5890 bool ARM64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5892 unsigned Intrinsic) const {
5893 switch (Intrinsic) {
5894 case Intrinsic::arm64_neon_ld2:
5895 case Intrinsic::arm64_neon_ld3:
5896 case Intrinsic::arm64_neon_ld4:
5897 case Intrinsic::arm64_neon_ld1x2:
5898 case Intrinsic::arm64_neon_ld1x3:
5899 case Intrinsic::arm64_neon_ld1x4:
5900 case Intrinsic::arm64_neon_ld2lane:
5901 case Intrinsic::arm64_neon_ld3lane:
5902 case Intrinsic::arm64_neon_ld4lane:
5903 case Intrinsic::arm64_neon_ld2r:
5904 case Intrinsic::arm64_neon_ld3r:
5905 case Intrinsic::arm64_neon_ld4r: {
5906 Info.opc = ISD::INTRINSIC_W_CHAIN;
5907 // Conservatively set memVT to the entire set of vectors loaded.
5908 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
5909 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5910 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
5913 Info.vol = false; // volatile loads with NEON intrinsics not supported
5914 Info.readMem = true;
5915 Info.writeMem = false;
5918 case Intrinsic::arm64_neon_st2:
5919 case Intrinsic::arm64_neon_st3:
5920 case Intrinsic::arm64_neon_st4:
5921 case Intrinsic::arm64_neon_st1x2:
5922 case Intrinsic::arm64_neon_st1x3:
5923 case Intrinsic::arm64_neon_st1x4:
5924 case Intrinsic::arm64_neon_st2lane:
5925 case Intrinsic::arm64_neon_st3lane:
5926 case Intrinsic::arm64_neon_st4lane: {
5927 Info.opc = ISD::INTRINSIC_VOID;
5928 // Conservatively set memVT to the entire set of vectors stored.
5929 unsigned NumElts = 0;
5930 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
5931 Type *ArgTy = I.getArgOperand(ArgI)->getType();
5932 if (!ArgTy->isVectorTy())
5934 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
5936 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5937 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
5940 Info.vol = false; // volatile stores with NEON intrinsics not supported
5941 Info.readMem = false;
5942 Info.writeMem = true;
5945 case Intrinsic::arm64_ldaxr:
5946 case Intrinsic::arm64_ldxr: {
5947 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
5948 Info.opc = ISD::INTRINSIC_W_CHAIN;
5949 Info.memVT = MVT::getVT(PtrTy->getElementType());
5950 Info.ptrVal = I.getArgOperand(0);
5952 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
5954 Info.readMem = true;
5955 Info.writeMem = false;
5958 case Intrinsic::arm64_stlxr:
5959 case Intrinsic::arm64_stxr: {
5960 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
5961 Info.opc = ISD::INTRINSIC_W_CHAIN;
5962 Info.memVT = MVT::getVT(PtrTy->getElementType());
5963 Info.ptrVal = I.getArgOperand(1);
5965 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
5967 Info.readMem = false;
5968 Info.writeMem = true;
5971 case Intrinsic::arm64_ldaxp:
5972 case Intrinsic::arm64_ldxp: {
5973 Info.opc = ISD::INTRINSIC_W_CHAIN;
5974 Info.memVT = MVT::i128;
5975 Info.ptrVal = I.getArgOperand(0);
5979 Info.readMem = true;
5980 Info.writeMem = false;
5983 case Intrinsic::arm64_stlxp:
5984 case Intrinsic::arm64_stxp: {
5985 Info.opc = ISD::INTRINSIC_W_CHAIN;
5986 Info.memVT = MVT::i128;
5987 Info.ptrVal = I.getArgOperand(2);
5991 Info.readMem = false;
5992 Info.writeMem = true;
6002 // Truncations from 64-bit GPR to 32-bit GPR is free.
6003 bool ARM64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6004 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6006 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6007 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6008 if (NumBits1 <= NumBits2)
6012 bool ARM64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6013 if (!VT1.isInteger() || !VT2.isInteger())
6015 unsigned NumBits1 = VT1.getSizeInBits();
6016 unsigned NumBits2 = VT2.getSizeInBits();
6017 if (NumBits1 <= NumBits2)
6022 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6024 bool ARM64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6025 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6027 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6028 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6029 if (NumBits1 == 32 && NumBits2 == 64)
6033 bool ARM64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6034 if (!VT1.isInteger() || !VT2.isInteger())
6036 unsigned NumBits1 = VT1.getSizeInBits();
6037 unsigned NumBits2 = VT2.getSizeInBits();
6038 if (NumBits1 == 32 && NumBits2 == 64)
6043 bool ARM64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6044 EVT VT1 = Val.getValueType();
6045 if (isZExtFree(VT1, VT2)) {
6049 if (Val.getOpcode() != ISD::LOAD)
6052 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6053 return (VT1.isSimple() && VT1.isInteger() && VT2.isSimple() &&
6054 VT2.isInteger() && VT1.getSizeInBits() <= 32);
6057 bool ARM64TargetLowering::hasPairedLoad(Type *LoadedType,
6058 unsigned &RequiredAligment) const {
6059 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6061 // Cyclone supports unaligned accesses.
6062 RequiredAligment = 0;
6063 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6064 return NumBits == 32 || NumBits == 64;
6067 bool ARM64TargetLowering::hasPairedLoad(EVT LoadedType,
6068 unsigned &RequiredAligment) const {
6069 if (!LoadedType.isSimple() ||
6070 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6072 // Cyclone supports unaligned accesses.
6073 RequiredAligment = 0;
6074 unsigned NumBits = LoadedType.getSizeInBits();
6075 return NumBits == 32 || NumBits == 64;
6078 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6079 unsigned AlignCheck) {
6080 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6081 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6084 EVT ARM64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6085 unsigned SrcAlign, bool IsMemset,
6086 bool ZeroMemset, bool MemcpyStrSrc,
6087 MachineFunction &MF) const {
6088 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6089 // instruction to materialize the v2i64 zero and one store (with restrictive
6090 // addressing mode). Just do two i64 store of zero-registers.
6092 const Function *F = MF.getFunction();
6093 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6094 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
6095 Attribute::NoImplicitFloat) &&
6096 (memOpAlign(SrcAlign, DstAlign, 16) ||
6097 (allowsUnalignedMemoryAccesses(MVT::f128, 0, &Fast) && Fast)))
6100 return Size >= 8 ? MVT::i64 : MVT::i32;
6103 // 12-bit optionally shifted immediates are legal for adds.
6104 bool ARM64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6105 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6110 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6111 // immediates is the same as for an add or a sub.
6112 bool ARM64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6115 return isLegalAddImmediate(Immed);
6118 /// isLegalAddressingMode - Return true if the addressing mode represented
6119 /// by AM is legal for this target, for a load/store of the specified type.
6120 bool ARM64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6122 // ARM64 has five basic addressing modes:
6124 // reg + 9-bit signed offset
6125 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6127 // reg + SIZE_IN_BYTES * reg
6129 // No global is ever allowed as a base.
6133 // No reg+reg+imm addressing.
6134 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6137 // check reg + imm case:
6138 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6139 uint64_t NumBytes = 0;
6140 if (Ty->isSized()) {
6141 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6142 NumBytes = NumBits / 8;
6143 if (!isPowerOf2_64(NumBits))
6148 int64_t Offset = AM.BaseOffs;
6150 // 9-bit signed offset
6151 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6154 // 12-bit unsigned offset
6155 unsigned shift = Log2_64(NumBytes);
6156 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6157 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6158 (Offset >> shift) << shift == Offset)
6163 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6165 if (!AM.Scale || AM.Scale == 1 ||
6166 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6171 int ARM64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6173 // Scaling factors are not free at all.
6174 // Operands | Rt Latency
6175 // -------------------------------------------
6177 // -------------------------------------------
6178 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6179 // Rt, [Xn, Wm, <extend> #imm] |
6180 if (isLegalAddressingMode(AM, Ty))
6181 // Scale represents reg2 * scale, thus account for 1 if
6182 // it is not equal to 0 or 1.
6183 return AM.Scale != 0 && AM.Scale != 1;
6187 bool ARM64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6188 VT = VT.getScalarType();
6193 switch (VT.getSimpleVT().SimpleTy) {
6205 ARM64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6206 // LR is a callee-save register, but we must treat it as clobbered by any call
6207 // site. Hence we include LR in the scratch registers, which are in turn added
6208 // as implicit-defs for stackmaps and patchpoints.
6209 static const MCPhysReg ScratchRegs[] = {
6210 ARM64::X16, ARM64::X17, ARM64::LR, 0
6215 bool ARM64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6216 EVT VT = N->getValueType(0);
6217 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6218 // it with shift to let it be lowered to UBFX.
6219 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6220 isa<ConstantSDNode>(N->getOperand(1))) {
6221 uint64_t TruncMask = N->getConstantOperandVal(1);
6222 if (isMask_64(TruncMask) &&
6223 N->getOperand(0).getOpcode() == ISD::SRL &&
6224 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6230 bool ARM64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6232 assert(Ty->isIntegerTy());
6234 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6238 int64_t Val = Imm.getSExtValue();
6239 if (Val == 0 || ARM64_AM::isLogicalImmediate(Val, BitSize))
6242 if ((int64_t)Val < 0)
6245 Val &= (1LL << 32) - 1;
6247 unsigned LZ = countLeadingZeros((uint64_t)Val);
6248 unsigned Shift = (63 - LZ) / 16;
6249 // MOVZ is free so return true for one or fewer MOVK.
6250 return (Shift < 3) ? true : false;
6253 // Generate SUBS and CSEL for integer abs.
6254 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6255 EVT VT = N->getValueType(0);
6257 SDValue N0 = N->getOperand(0);
6258 SDValue N1 = N->getOperand(1);
6261 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6262 // and change it to SUB and CSEL.
6263 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6264 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6265 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6266 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6267 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6268 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6270 // Generate SUBS & CSEL.
6272 DAG.getNode(ARM64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6273 N0.getOperand(0), DAG.getConstant(0, VT));
6274 return DAG.getNode(ARM64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6275 DAG.getConstant(ARM64CC::PL, MVT::i32),
6276 SDValue(Cmp.getNode(), 1));
6281 // performXorCombine - Attempts to handle integer ABS.
6282 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6283 TargetLowering::DAGCombinerInfo &DCI,
6284 const ARM64Subtarget *Subtarget) {
6285 if (DCI.isBeforeLegalizeOps())
6288 return performIntegerAbsCombine(N, DAG);
6291 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6292 TargetLowering::DAGCombinerInfo &DCI,
6293 const ARM64Subtarget *Subtarget) {
6294 if (DCI.isBeforeLegalizeOps())
6297 // Multiplication of a power of two plus/minus one can be done more
6298 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6299 // future CPUs have a cheaper MADD instruction, this may need to be
6300 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6301 // 64-bit is 5 cycles, so this is always a win.
6302 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6303 APInt Value = C->getAPIntValue();
6304 EVT VT = N->getValueType(0);
6305 APInt VP1 = Value + 1;
6306 if (VP1.isPowerOf2()) {
6307 // Multiplying by one less than a power of two, replace with a shift
6309 SDValue ShiftedVal =
6310 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6311 DAG.getConstant(VP1.logBase2(), MVT::i64));
6312 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6314 APInt VM1 = Value - 1;
6315 if (VM1.isPowerOf2()) {
6316 // Multiplying by one more than a power of two, replace with a shift
6318 SDValue ShiftedVal =
6319 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6320 DAG.getConstant(VM1.logBase2(), MVT::i64));
6321 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6327 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
6328 EVT VT = N->getValueType(0);
6329 if (VT != MVT::f32 && VT != MVT::f64)
6331 // Only optimize when the source and destination types have the same width.
6332 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
6335 // If the result of an integer load is only used by an integer-to-float
6336 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
6337 // This eliminates an "integer-to-vector-move UOP and improve throughput.
6338 SDValue N0 = N->getOperand(0);
6339 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6340 // Do not change the width of a volatile load.
6341 !cast<LoadSDNode>(N0)->isVolatile()) {
6342 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6343 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
6344 LN0->getPointerInfo(), LN0->isVolatile(),
6345 LN0->isNonTemporal(), LN0->isInvariant(),
6346 LN0->getAlignment());
6348 // Make sure successors of the original load stay after it by updating them
6349 // to use the new Chain.
6350 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
6353 (N->getOpcode() == ISD::SINT_TO_FP) ? ARM64ISD::SITOF : ARM64ISD::UITOF;
6354 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
6360 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6361 /// searches for and classifies those shifts.
6362 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
6364 if (N.getOpcode() == ISD::SHL)
6366 else if (N.getOpcode() == ISD::SRL)
6371 if (!isa<ConstantSDNode>(N.getOperand(1)))
6374 ShiftAmount = N->getConstantOperandVal(1);
6375 Src = N->getOperand(0);
6379 /// EXTR instruction extracts a contiguous chunk of bits from two existing
6380 /// registers viewed as a high/low pair. This function looks for the pattern:
6381 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
6382 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
6384 static SDValue tryCombineToEXTR(SDNode *N,
6385 TargetLowering::DAGCombinerInfo &DCI) {
6386 SelectionDAG &DAG = DCI.DAG;
6388 EVT VT = N->getValueType(0);
6390 assert(N->getOpcode() == ISD::OR && "Unexpected root");
6392 if (VT != MVT::i32 && VT != MVT::i64)
6396 uint32_t ShiftLHS = 0;
6398 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
6402 uint32_t ShiftRHS = 0;
6404 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
6407 // If they're both trying to come from the high part of the register, they're
6408 // not really an EXTR.
6409 if (LHSFromHi == RHSFromHi)
6412 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
6416 std::swap(LHS, RHS);
6417 std::swap(ShiftLHS, ShiftRHS);
6420 return DAG.getNode(ARM64ISD::EXTR, DL, VT, LHS, RHS,
6421 DAG.getConstant(ShiftRHS, MVT::i64));
6424 static SDValue tryCombineToBSL(SDNode *N,
6425 TargetLowering::DAGCombinerInfo &DCI) {
6426 EVT VT = N->getValueType(0);
6427 SelectionDAG &DAG = DCI.DAG;
6433 SDValue N0 = N->getOperand(0);
6434 if (N0.getOpcode() != ISD::AND)
6437 SDValue N1 = N->getOperand(1);
6438 if (N1.getOpcode() != ISD::AND)
6441 // We only have to look for constant vectors here since the general, variable
6442 // case can be handled in TableGen.
6443 unsigned Bits = VT.getVectorElementType().getSizeInBits();
6444 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
6445 for (int i = 1; i >= 0; --i)
6446 for (int j = 1; j >= 0; --j) {
6447 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
6448 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
6452 bool FoundMatch = true;
6453 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
6454 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
6455 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
6457 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
6464 return DAG.getNode(ARM64ISD::BSL, DL, VT, SDValue(BVN0, 0),
6465 N0->getOperand(1 - i), N1->getOperand(1 - j));
6471 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
6472 const ARM64Subtarget *Subtarget) {
6473 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
6474 if (!EnableARM64ExtrGeneration)
6476 SelectionDAG &DAG = DCI.DAG;
6477 EVT VT = N->getValueType(0);
6479 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6482 SDValue Res = tryCombineToEXTR(N, DCI);
6486 Res = tryCombineToBSL(N, DCI);
6493 static SDValue performBitcastCombine(SDNode *N,
6494 TargetLowering::DAGCombinerInfo &DCI,
6495 SelectionDAG &DAG) {
6496 // Wait 'til after everything is legalized to try this. That way we have
6497 // legal vector types and such.
6498 if (DCI.isBeforeLegalizeOps())
6501 // Remove extraneous bitcasts around an extract_subvector.
6503 // (v4i16 (bitconvert
6504 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
6506 // (extract_subvector ((v8i16 ...), (i64 4)))
6508 // Only interested in 64-bit vectors as the ultimate result.
6509 EVT VT = N->getValueType(0);
6512 if (VT.getSimpleVT().getSizeInBits() != 64)
6514 // Is the operand an extract_subvector starting at the beginning or halfway
6515 // point of the vector? A low half may also come through as an
6516 // EXTRACT_SUBREG, so look for that, too.
6517 SDValue Op0 = N->getOperand(0);
6518 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
6519 !(Op0->isMachineOpcode() &&
6520 Op0->getMachineOpcode() == ARM64::EXTRACT_SUBREG))
6522 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
6523 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
6524 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
6526 } else if (Op0->getMachineOpcode() == ARM64::EXTRACT_SUBREG) {
6527 if (idx != ARM64::dsub)
6529 // The dsub reference is equivalent to a lane zero subvector reference.
6532 // Look through the bitcast of the input to the extract.
6533 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
6535 SDValue Source = Op0->getOperand(0)->getOperand(0);
6536 // If the source type has twice the number of elements as our destination
6537 // type, we know this is an extract of the high or low half of the vector.
6538 EVT SVT = Source->getValueType(0);
6539 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
6542 DEBUG(dbgs() << "arm64-lower: bitcast extract_subvector simplification\n");
6544 // Create the simplified form to just extract the low or high half of the
6545 // vector directly rather than bothering with the bitcasts.
6547 unsigned NumElements = VT.getVectorNumElements();
6549 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
6550 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
6552 SDValue SubReg = DAG.getTargetConstant(ARM64::dsub, MVT::i32);
6553 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
6559 static SDValue performConcatVectorsCombine(SDNode *N,
6560 TargetLowering::DAGCombinerInfo &DCI,
6561 SelectionDAG &DAG) {
6562 // Wait 'til after everything is legalized to try this. That way we have
6563 // legal vector types and such.
6564 if (DCI.isBeforeLegalizeOps())
6568 EVT VT = N->getValueType(0);
6570 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
6571 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
6572 // canonicalise to that.
6573 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) {
6574 assert(VT.getVectorElementType().getSizeInBits() == 64);
6575 return DAG.getNode(ARM64ISD::DUPLANE64, dl, VT,
6576 WidenVector(N->getOperand(0), DAG),
6577 DAG.getConstant(0, MVT::i64));
6580 // Canonicalise concat_vectors so that the right-hand vector has as few
6581 // bit-casts as possible before its real operation. The primary matching
6582 // destination for these operations will be the narrowing "2" instructions,
6583 // which depend on the operation being performed on this right-hand vector.
6585 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
6587 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
6589 SDValue Op1 = N->getOperand(1);
6590 if (Op1->getOpcode() != ISD::BITCAST)
6592 SDValue RHS = Op1->getOperand(0);
6593 MVT RHSTy = RHS.getValueType().getSimpleVT();
6594 // If the RHS is not a vector, this is not the pattern we're looking for.
6595 if (!RHSTy.isVector())
6598 DEBUG(dbgs() << "arm64-lower: concat_vectors bitcast simplification\n");
6600 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
6601 RHSTy.getVectorNumElements() * 2);
6603 ISD::BITCAST, dl, VT,
6604 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
6605 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS));
6608 static SDValue tryCombineFixedPointConvert(SDNode *N,
6609 TargetLowering::DAGCombinerInfo &DCI,
6610 SelectionDAG &DAG) {
6611 // Wait 'til after everything is legalized to try this. That way we have
6612 // legal vector types and such.
6613 if (DCI.isBeforeLegalizeOps())
6615 // Transform a scalar conversion of a value from a lane extract into a
6616 // lane extract of a vector conversion. E.g., from foo1 to foo2:
6617 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
6618 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
6620 // The second form interacts better with instruction selection and the
6621 // register allocator to avoid cross-class register copies that aren't
6622 // coalescable due to a lane reference.
6624 // Check the operand and see if it originates from a lane extract.
6625 SDValue Op1 = N->getOperand(1);
6626 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6627 // Yep, no additional predication needed. Perform the transform.
6628 SDValue IID = N->getOperand(0);
6629 SDValue Shift = N->getOperand(2);
6630 SDValue Vec = Op1.getOperand(0);
6631 SDValue Lane = Op1.getOperand(1);
6632 EVT ResTy = N->getValueType(0);
6636 // The vector width should be 128 bits by the time we get here, even
6637 // if it started as 64 bits (the extract_vector handling will have
6639 assert(Vec.getValueType().getSizeInBits() == 128 &&
6640 "unexpected vector size on extract_vector_elt!");
6641 if (Vec.getValueType() == MVT::v4i32)
6642 VecResTy = MVT::v4f32;
6643 else if (Vec.getValueType() == MVT::v2i64)
6644 VecResTy = MVT::v2f64;
6646 assert(0 && "unexpected vector type!");
6649 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
6650 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
6655 // AArch64 high-vector "long" operations are formed by performing the non-high
6656 // version on an extract_subvector of each operand which gets the high half:
6658 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
6660 // However, there are cases which don't have an extract_high explicitly, but
6661 // have another operation that can be made compatible with one for free. For
6664 // (dupv64 scalar) --> (extract_high (dup128 scalar))
6666 // This routine does the actual conversion of such DUPs, once outer routines
6667 // have determined that everything else is in order.
6668 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
6669 // We can handle most types of duplicate, but the lane ones have an extra
6670 // operand saying *which* lane, so we need to know.
6672 switch (N.getOpcode()) {
6676 case ARM64ISD::DUPLANE8:
6677 case ARM64ISD::DUPLANE16:
6678 case ARM64ISD::DUPLANE32:
6679 case ARM64ISD::DUPLANE64:
6686 MVT NarrowTy = N.getSimpleValueType();
6687 if (!NarrowTy.is64BitVector())
6690 MVT ElementTy = NarrowTy.getVectorElementType();
6691 unsigned NumElems = NarrowTy.getVectorNumElements();
6692 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
6696 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
6699 NewDUP = DAG.getNode(ARM64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
6701 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
6702 NewDUP, DAG.getConstant(NumElems, MVT::i64));
6705 static bool isEssentiallyExtractSubvector(SDValue N) {
6706 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
6709 return N.getOpcode() == ISD::BITCAST &&
6710 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
6713 /// \brief Helper structure to keep track of ISD::SET_CC operands.
6714 struct GenericSetCCInfo {
6715 const SDValue *Opnd0;
6716 const SDValue *Opnd1;
6720 /// \brief Helper structure to keep track of a SET_CC lowered into ARM64 code.
6721 struct ARM64SetCCInfo {
6723 ARM64CC::CondCode CC;
6726 /// \brief Helper structure to keep track of SetCC information.
6728 GenericSetCCInfo Generic;
6729 ARM64SetCCInfo ARM64;
6732 /// \brief Helper structure to be able to read SetCC information.
6733 /// If set to true, IsARM64 field, Info is a ARM64SetCCInfo, otherwise Info is
6734 /// a GenericSetCCInfo.
6735 struct SetCCInfoAndKind {
6740 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
6742 /// ARM64 lowered one.
6743 /// \p SetCCInfo is filled accordingly.
6744 /// \post SetCCInfo is meanginfull only when this function returns true.
6745 /// \return True when Op is a kind of SET_CC operation.
6746 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
6747 // If this is a setcc, this is straight forward.
6748 if (Op.getOpcode() == ISD::SETCC) {
6749 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
6750 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
6751 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6752 SetCCInfo.IsARM64 = false;
6755 // Otherwise, check if this is a matching csel instruction.
6759 if (Op.getOpcode() != ARM64ISD::CSEL)
6761 // Set the information about the operands.
6762 // TODO: we want the operands of the Cmp not the csel
6763 SetCCInfo.Info.ARM64.Cmp = &Op.getOperand(3);
6764 SetCCInfo.IsARM64 = true;
6765 SetCCInfo.Info.ARM64.CC = static_cast<ARM64CC::CondCode>(
6766 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
6768 // Check that the operands matches the constraints:
6769 // (1) Both operands must be constants.
6770 // (2) One must be 1 and the other must be 0.
6771 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
6772 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6775 if (!TValue || !FValue)
6779 if (!TValue->isOne()) {
6780 // Update the comparison when we are interested in !cc.
6781 std::swap(TValue, FValue);
6782 SetCCInfo.Info.ARM64.CC =
6783 ARM64CC::getInvertedCondCode(SetCCInfo.Info.ARM64.CC);
6785 return TValue->isOne() && FValue->isNullValue();
6788 // Returns true if Op is setcc or zext of setcc.
6789 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
6790 if (isSetCC(Op, Info))
6792 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
6793 isSetCC(Op->getOperand(0), Info));
6796 // The folding we want to perform is:
6797 // (add x, [zext] (setcc cc ...) )
6799 // (csel x, (add x, 1), !cc ...)
6801 // The latter will get matched to a CSINC instruction.
6802 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
6803 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
6804 SDValue LHS = Op->getOperand(0);
6805 SDValue RHS = Op->getOperand(1);
6806 SetCCInfoAndKind InfoAndKind;
6808 // If neither operand is a SET_CC, give up.
6809 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
6810 std::swap(LHS, RHS);
6811 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
6815 // FIXME: This could be generatized to work for FP comparisons.
6816 EVT CmpVT = InfoAndKind.IsARM64
6817 ? InfoAndKind.Info.ARM64.Cmp->getOperand(0).getValueType()
6818 : InfoAndKind.Info.Generic.Opnd0->getValueType();
6819 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
6825 if (InfoAndKind.IsARM64) {
6826 CCVal = DAG.getConstant(
6827 ARM64CC::getInvertedCondCode(InfoAndKind.Info.ARM64.CC), MVT::i32);
6828 Cmp = *InfoAndKind.Info.ARM64.Cmp;
6830 Cmp = getARM64Cmp(*InfoAndKind.Info.Generic.Opnd0,
6831 *InfoAndKind.Info.Generic.Opnd1,
6832 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
6835 EVT VT = Op->getValueType(0);
6836 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
6837 return DAG.getNode(ARM64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
6840 // The basic add/sub long vector instructions have variants with "2" on the end
6841 // which act on the high-half of their inputs. They are normally matched by
6844 // (add (zeroext (extract_high LHS)),
6845 // (zeroext (extract_high RHS)))
6846 // -> uaddl2 vD, vN, vM
6848 // However, if one of the extracts is something like a duplicate, this
6849 // instruction can still be used profitably. This function puts the DAG into a
6850 // more appropriate form for those patterns to trigger.
6851 static SDValue performAddSubLongCombine(SDNode *N,
6852 TargetLowering::DAGCombinerInfo &DCI,
6853 SelectionDAG &DAG) {
6854 if (DCI.isBeforeLegalizeOps())
6857 MVT VT = N->getSimpleValueType(0);
6858 if (!VT.is128BitVector()) {
6859 if (N->getOpcode() == ISD::ADD)
6860 return performSetccAddFolding(N, DAG);
6864 // Make sure both branches are extended in the same way.
6865 SDValue LHS = N->getOperand(0);
6866 SDValue RHS = N->getOperand(1);
6867 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
6868 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
6869 LHS.getOpcode() != RHS.getOpcode())
6872 unsigned ExtType = LHS.getOpcode();
6874 // It's not worth doing if at least one of the inputs isn't already an
6875 // extract, but we don't know which it'll be so we have to try both.
6876 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
6877 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
6881 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
6882 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
6883 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
6887 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
6890 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
6893 // Massage DAGs which we can use the high-half "long" operations on into
6894 // something isel will recognize better. E.g.
6896 // (arm64_neon_umull (extract_high vec) (dupv64 scalar)) -->
6897 // (arm64_neon_umull (extract_high (v2i64 vec)))
6898 // (extract_high (v2i64 (dup128 scalar)))))
6900 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
6901 TargetLowering::DAGCombinerInfo &DCI,
6902 SelectionDAG &DAG) {
6903 if (DCI.isBeforeLegalizeOps())
6906 SDValue LHS = N->getOperand(1);
6907 SDValue RHS = N->getOperand(2);
6908 assert(LHS.getValueType().is64BitVector() &&
6909 RHS.getValueType().is64BitVector() &&
6910 "unexpected shape for long operation");
6912 // Either node could be a DUP, but it's not worth doing both of them (you'd
6913 // just as well use the non-high version) so look for a corresponding extract
6914 // operation on the other "wing".
6915 if (isEssentiallyExtractSubvector(LHS)) {
6916 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
6919 } else if (isEssentiallyExtractSubvector(RHS)) {
6920 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
6925 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
6926 N->getOperand(0), LHS, RHS);
6929 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
6930 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
6931 unsigned ElemBits = ElemTy.getSizeInBits();
6933 int64_t ShiftAmount;
6934 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
6935 APInt SplatValue, SplatUndef;
6936 unsigned SplatBitSize;
6938 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
6939 HasAnyUndefs, ElemBits) ||
6940 SplatBitSize != ElemBits)
6943 ShiftAmount = SplatValue.getSExtValue();
6944 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
6945 ShiftAmount = CVN->getSExtValue();
6953 llvm_unreachable("Unknown shift intrinsic");
6954 case Intrinsic::arm64_neon_sqshl:
6955 Opcode = ARM64ISD::SQSHL_I;
6956 IsRightShift = false;
6958 case Intrinsic::arm64_neon_uqshl:
6959 Opcode = ARM64ISD::UQSHL_I;
6960 IsRightShift = false;
6962 case Intrinsic::arm64_neon_srshl:
6963 Opcode = ARM64ISD::SRSHR_I;
6964 IsRightShift = true;
6966 case Intrinsic::arm64_neon_urshl:
6967 Opcode = ARM64ISD::URSHR_I;
6968 IsRightShift = true;
6970 case Intrinsic::arm64_neon_sqshlu:
6971 Opcode = ARM64ISD::SQSHLU_I;
6972 IsRightShift = false;
6976 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
6977 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
6978 DAG.getConstant(-ShiftAmount, MVT::i32));
6979 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount <= ElemBits)
6980 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
6981 DAG.getConstant(ShiftAmount, MVT::i32));
6986 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
6987 // the intrinsics must be legal and take an i32, this means there's almost
6988 // certainly going to be a zext in the DAG which we can eliminate.
6989 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
6990 SDValue AndN = N->getOperand(2);
6991 if (AndN.getOpcode() != ISD::AND)
6994 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
6995 if (!CMask || CMask->getZExtValue() != Mask)
6998 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
6999 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7002 static SDValue performIntrinsicCombine(SDNode *N,
7003 TargetLowering::DAGCombinerInfo &DCI,
7004 const ARM64Subtarget *Subtarget) {
7005 SelectionDAG &DAG = DCI.DAG;
7006 unsigned IID = getIntrinsicID(N);
7010 case Intrinsic::arm64_neon_vcvtfxs2fp:
7011 case Intrinsic::arm64_neon_vcvtfxu2fp:
7012 return tryCombineFixedPointConvert(N, DCI, DAG);
7014 case Intrinsic::arm64_neon_fmax:
7015 return DAG.getNode(ARM64ISD::FMAX, SDLoc(N), N->getValueType(0),
7016 N->getOperand(1), N->getOperand(2));
7017 case Intrinsic::arm64_neon_fmin:
7018 return DAG.getNode(ARM64ISD::FMIN, SDLoc(N), N->getValueType(0),
7019 N->getOperand(1), N->getOperand(2));
7020 case Intrinsic::arm64_neon_smull:
7021 case Intrinsic::arm64_neon_umull:
7022 case Intrinsic::arm64_neon_pmull:
7023 case Intrinsic::arm64_neon_sqdmull:
7024 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7025 case Intrinsic::arm64_neon_sqshl:
7026 case Intrinsic::arm64_neon_uqshl:
7027 case Intrinsic::arm64_neon_sqshlu:
7028 case Intrinsic::arm64_neon_srshl:
7029 case Intrinsic::arm64_neon_urshl:
7030 return tryCombineShiftImm(IID, N, DAG);
7031 case Intrinsic::arm64_crc32b:
7032 case Intrinsic::arm64_crc32cb:
7033 return tryCombineCRC32(0xff, N, DAG);
7034 case Intrinsic::arm64_crc32h:
7035 case Intrinsic::arm64_crc32ch:
7036 return tryCombineCRC32(0xffff, N, DAG);
7041 static SDValue performExtendCombine(SDNode *N,
7042 TargetLowering::DAGCombinerInfo &DCI,
7043 SelectionDAG &DAG) {
7044 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7045 // we can convert that DUP into another extract_high (of a bigger DUP), which
7046 // helps the backend to decide that an sabdl2 would be useful, saving a real
7047 // extract_high operation.
7048 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7049 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7050 SDNode *ABDNode = N->getOperand(0).getNode();
7051 unsigned IID = getIntrinsicID(ABDNode);
7052 if (IID == Intrinsic::arm64_neon_sabd ||
7053 IID == Intrinsic::arm64_neon_uabd) {
7054 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7055 if (!NewABD.getNode())
7058 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7063 // This is effectively a custom type legalization for ARM64.
7065 // Type legalization will split an extend of a small, legal, type to a larger
7066 // illegal type by first splitting the destination type, often creating
7067 // illegal source types, which then get legalized in isel-confusing ways,
7068 // leading to really terrible codegen. E.g.,
7069 // %result = v8i32 sext v8i8 %value
7071 // %losrc = extract_subreg %value, ...
7072 // %hisrc = extract_subreg %value, ...
7073 // %lo = v4i32 sext v4i8 %losrc
7074 // %hi = v4i32 sext v4i8 %hisrc
7075 // Things go rapidly downhill from there.
7077 // For ARM64, the [sz]ext vector instructions can only go up one element
7078 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7079 // take two instructions.
7081 // This implies that the most efficient way to do the extend from v8i8
7082 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7083 // the normal splitting to happen for the v8i16->v8i32.
7085 // This is pre-legalization to catch some cases where the default
7086 // type legalization will create ill-tempered code.
7087 if (!DCI.isBeforeLegalizeOps())
7090 // We're only interested in cleaning things up for non-legal vector types
7091 // here. If both the source and destination are legal, things will just
7092 // work naturally without any fiddling.
7093 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7094 EVT ResVT = N->getValueType(0);
7095 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7097 // If the vector type isn't a simple VT, it's beyond the scope of what
7098 // we're worried about here. Let legalization do its thing and hope for
7100 if (!ResVT.isSimple())
7103 SDValue Src = N->getOperand(0);
7104 MVT SrcVT = Src->getValueType(0).getSimpleVT();
7105 // If the source VT is a 64-bit vector, we can play games and get the
7106 // better results we want.
7107 if (SrcVT.getSizeInBits() != 64)
7110 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7111 unsigned ElementCount = SrcVT.getVectorNumElements();
7112 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7114 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7116 // Now split the rest of the operation into two halves, each with a 64
7120 unsigned NumElements = ResVT.getVectorNumElements();
7121 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7122 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7123 ResVT.getVectorElementType(), NumElements / 2);
7125 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7126 LoVT.getVectorNumElements());
7127 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7128 DAG.getIntPtrConstant(0));
7129 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7130 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
7131 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7132 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7134 // Now combine the parts back together so we still have a single result
7135 // like the combiner expects.
7136 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7139 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7140 /// value. The load store optimizer pass will merge them to store pair stores.
7141 /// This has better performance than a splat of the scalar followed by a split
7142 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7143 /// followed by an ext.b and two stores.
7144 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7145 SDValue StVal = St->getValue();
7146 EVT VT = StVal.getValueType();
7148 // Don't replace floating point stores, they possibly won't be transformed to
7149 // stp because of the store pair suppress pass.
7150 if (VT.isFloatingPoint())
7153 // Check for insert vector elements.
7154 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7157 // We can express a splat as store pair(s) for 2 or 4 elements.
7158 unsigned NumVecElts = VT.getVectorNumElements();
7159 if (NumVecElts != 4 && NumVecElts != 2)
7161 SDValue SplatVal = StVal.getOperand(1);
7162 unsigned RemainInsertElts = NumVecElts - 1;
7164 // Check that this is a splat.
7165 while (--RemainInsertElts) {
7166 SDValue NextInsertElt = StVal.getOperand(0);
7167 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7169 if (NextInsertElt.getOperand(1) != SplatVal)
7171 StVal = NextInsertElt;
7173 unsigned OrigAlignment = St->getAlignment();
7174 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7175 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7177 // Create scalar stores. This is at least as good as the code sequence for a
7178 // split unaligned store wich is a dup.s, ext.b, and two stores.
7179 // Most of the time the three stores should be replaced by store pair
7180 // instructions (stp).
7182 SDValue BasePtr = St->getBasePtr();
7184 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7185 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7187 unsigned Offset = EltOffset;
7188 while (--NumVecElts) {
7189 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7190 DAG.getConstant(Offset, MVT::i64));
7191 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7192 St->getPointerInfo(), St->isVolatile(),
7193 St->isNonTemporal(), Alignment);
7194 Offset += EltOffset;
7199 static SDValue performSTORECombine(SDNode *N,
7200 TargetLowering::DAGCombinerInfo &DCI,
7202 const ARM64Subtarget *Subtarget) {
7203 if (!DCI.isBeforeLegalize())
7206 StoreSDNode *S = cast<StoreSDNode>(N);
7207 if (S->isVolatile())
7210 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7211 // page boundries. We want to split such stores.
7212 if (!Subtarget->isCyclone())
7215 // Don't split at Oz.
7216 MachineFunction &MF = DAG.getMachineFunction();
7217 bool IsMinSize = MF.getFunction()->getAttributes().hasAttribute(
7218 AttributeSet::FunctionIndex, Attribute::MinSize);
7222 SDValue StVal = S->getValue();
7223 EVT VT = StVal.getValueType();
7225 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7226 // those up regresses performance on micro-benchmarks and olden/bh.
7227 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7230 // Split unaligned 16B stores. They are terrible for performance.
7231 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7232 // extensions can use this to mark that it does not want splitting to happen
7233 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7234 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7235 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7236 S->getAlignment() <= 2)
7239 // If we get a splat of a scalar convert this vector store to a store of
7240 // scalars. They will be merged into store pairs thereby removing two
7242 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7243 if (ReplacedSplat != SDValue())
7244 return ReplacedSplat;
7247 unsigned NumElts = VT.getVectorNumElements() / 2;
7248 // Split VT into two.
7250 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7251 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7252 DAG.getIntPtrConstant(0));
7253 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7254 DAG.getIntPtrConstant(NumElts));
7255 SDValue BasePtr = S->getBasePtr();
7257 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7258 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7259 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7260 DAG.getConstant(8, MVT::i64));
7261 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
7262 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
7266 /// Target-specific DAG combine function for post-increment LD1 (lane) and
7267 /// post-increment LD1R.
7268 static SDValue performPostLD1Combine(SDNode *N,
7269 TargetLowering::DAGCombinerInfo &DCI,
7271 if (DCI.isBeforeLegalizeOps())
7274 SelectionDAG &DAG = DCI.DAG;
7275 EVT VT = N->getValueType(0);
7277 unsigned LoadIdx = IsLaneOp ? 1 : 0;
7278 SDNode *LD = N->getOperand(LoadIdx).getNode();
7279 // If it is not LOAD, can not do such combine.
7280 if (LD->getOpcode() != ISD::LOAD)
7283 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
7284 EVT MemVT = LoadSDN->getMemoryVT();
7285 // Check if memory operand is the same type as the vector element.
7286 if (MemVT != VT.getVectorElementType())
7289 // Check if there are other uses. If so, do not combine as it will introduce
7291 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
7293 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
7299 SDValue Addr = LD->getOperand(1);
7300 SDValue Vector = N->getOperand(0);
7301 // Search for a use of the address operand that is an increment.
7302 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
7303 Addr.getNode()->use_end(); UI != UE; ++UI) {
7305 if (User->getOpcode() != ISD::ADD
7306 || UI.getUse().getResNo() != Addr.getResNo())
7309 // Check that the add is independent of the load. Otherwise, folding it
7310 // would create a cycle.
7311 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
7313 // Also check that add is not used in the vector operand. This would also
7315 if (User->isPredecessorOf(Vector.getNode()))
7318 // If the increment is a constant, it must match the memory ref size.
7319 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7320 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7321 uint32_t IncVal = CInc->getZExtValue();
7322 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
7323 if (IncVal != NumBytes)
7325 Inc = DAG.getRegister(ARM64::XZR, MVT::i64);
7328 SmallVector<SDValue, 8> Ops;
7329 Ops.push_back(LD->getOperand(0)); // Chain
7331 Ops.push_back(Vector); // The vector to be inserted
7332 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
7334 Ops.push_back(Addr);
7337 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
7338 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, 3));
7339 unsigned NewOp = IsLaneOp ? ARM64ISD::LD1LANEpost : ARM64ISD::LD1DUPpost;
7340 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
7342 LoadSDN->getMemOperand());
7345 std::vector<SDValue> NewResults;
7346 NewResults.push_back(SDValue(LD, 0)); // The result of load
7347 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
7348 DCI.CombineTo(LD, NewResults);
7349 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
7350 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
7357 /// Target-specific DAG combine function for NEON load/store intrinsics
7358 /// to merge base address updates.
7359 static SDValue performNEONPostLDSTCombine(SDNode *N,
7360 TargetLowering::DAGCombinerInfo &DCI,
7361 SelectionDAG &DAG) {
7362 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7365 unsigned AddrOpIdx = N->getNumOperands() - 1;
7366 SDValue Addr = N->getOperand(AddrOpIdx);
7368 // Search for a use of the address operand that is an increment.
7369 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7370 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
7372 if (User->getOpcode() != ISD::ADD ||
7373 UI.getUse().getResNo() != Addr.getResNo())
7376 // Check that the add is independent of the load/store. Otherwise, folding
7377 // it would create a cycle.
7378 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
7381 // Find the new opcode for the updating load/store.
7382 bool IsStore = false;
7383 bool IsLaneOp = false;
7384 bool IsDupOp = false;
7385 unsigned NewOpc = 0;
7386 unsigned NumVecs = 0;
7387 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7389 default: llvm_unreachable("unexpected intrinsic for Neon base update");
7390 case Intrinsic::arm64_neon_ld2: NewOpc = ARM64ISD::LD2post;
7392 case Intrinsic::arm64_neon_ld3: NewOpc = ARM64ISD::LD3post;
7394 case Intrinsic::arm64_neon_ld4: NewOpc = ARM64ISD::LD4post;
7396 case Intrinsic::arm64_neon_st2: NewOpc = ARM64ISD::ST2post;
7397 NumVecs = 2; IsStore = true; break;
7398 case Intrinsic::arm64_neon_st3: NewOpc = ARM64ISD::ST3post;
7399 NumVecs = 3; IsStore = true; break;
7400 case Intrinsic::arm64_neon_st4: NewOpc = ARM64ISD::ST4post;
7401 NumVecs = 4; IsStore = true; break;
7402 case Intrinsic::arm64_neon_ld1x2: NewOpc = ARM64ISD::LD1x2post;
7404 case Intrinsic::arm64_neon_ld1x3: NewOpc = ARM64ISD::LD1x3post;
7406 case Intrinsic::arm64_neon_ld1x4: NewOpc = ARM64ISD::LD1x4post;
7408 case Intrinsic::arm64_neon_st1x2: NewOpc = ARM64ISD::ST1x2post;
7409 NumVecs = 2; IsStore = true; break;
7410 case Intrinsic::arm64_neon_st1x3: NewOpc = ARM64ISD::ST1x3post;
7411 NumVecs = 3; IsStore = true; break;
7412 case Intrinsic::arm64_neon_st1x4: NewOpc = ARM64ISD::ST1x4post;
7413 NumVecs = 4; IsStore = true; break;
7414 case Intrinsic::arm64_neon_ld2r: NewOpc = ARM64ISD::LD2DUPpost;
7415 NumVecs = 2; IsDupOp = true; break;
7416 case Intrinsic::arm64_neon_ld3r: NewOpc = ARM64ISD::LD3DUPpost;
7417 NumVecs = 3; IsDupOp = true; break;
7418 case Intrinsic::arm64_neon_ld4r: NewOpc = ARM64ISD::LD4DUPpost;
7419 NumVecs = 4; IsDupOp = true; break;
7420 case Intrinsic::arm64_neon_ld2lane: NewOpc = ARM64ISD::LD2LANEpost;
7421 NumVecs = 2; IsLaneOp = true; break;
7422 case Intrinsic::arm64_neon_ld3lane: NewOpc = ARM64ISD::LD3LANEpost;
7423 NumVecs = 3; IsLaneOp = true; break;
7424 case Intrinsic::arm64_neon_ld4lane: NewOpc = ARM64ISD::LD4LANEpost;
7425 NumVecs = 4; IsLaneOp = true; break;
7426 case Intrinsic::arm64_neon_st2lane: NewOpc = ARM64ISD::ST2LANEpost;
7427 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
7428 case Intrinsic::arm64_neon_st3lane: NewOpc = ARM64ISD::ST3LANEpost;
7429 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
7430 case Intrinsic::arm64_neon_st4lane: NewOpc = ARM64ISD::ST4LANEpost;
7431 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
7436 VecTy = N->getOperand(2).getValueType();
7438 VecTy = N->getValueType(0);
7440 // If the increment is a constant, it must match the memory ref size.
7441 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7442 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7443 uint32_t IncVal = CInc->getZExtValue();
7444 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
7445 if (IsLaneOp || IsDupOp)
7446 NumBytes /= VecTy.getVectorNumElements();
7447 if (IncVal != NumBytes)
7449 Inc = DAG.getRegister(ARM64::XZR, MVT::i64);
7451 SmallVector<SDValue, 8> Ops;
7452 Ops.push_back(N->getOperand(0)); // Incoming chain
7453 // Load lane and store have vector list as input.
7454 if (IsLaneOp || IsStore)
7455 for (unsigned i = 2; i < AddrOpIdx; ++i)
7456 Ops.push_back(N->getOperand(i));
7457 Ops.push_back(Addr); // Base register
7462 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
7464 for (n = 0; n < NumResultVecs; ++n)
7466 Tys[n++] = MVT::i64; // Type of write back register
7467 Tys[n] = MVT::Other; // Type of the chain
7468 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, NumResultVecs + 2));
7470 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
7471 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
7472 MemInt->getMemoryVT(),
7473 MemInt->getMemOperand());
7476 std::vector<SDValue> NewResults;
7477 for (unsigned i = 0; i < NumResultVecs; ++i) {
7478 NewResults.push_back(SDValue(UpdN.getNode(), i));
7480 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
7481 DCI.CombineTo(N, NewResults);
7482 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
7489 // Optimize compare with zero and branch.
7490 static SDValue performBRCONDCombine(SDNode *N,
7491 TargetLowering::DAGCombinerInfo &DCI,
7492 SelectionDAG &DAG) {
7493 SDValue Chain = N->getOperand(0);
7494 SDValue Dest = N->getOperand(1);
7495 SDValue CCVal = N->getOperand(2);
7496 SDValue Cmp = N->getOperand(3);
7498 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
7499 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
7500 if (CC != ARM64CC::EQ && CC != ARM64CC::NE)
7503 unsigned CmpOpc = Cmp.getOpcode();
7504 if (CmpOpc != ARM64ISD::ADDS && CmpOpc != ARM64ISD::SUBS)
7507 // Only attempt folding if there is only one use of the flag and no use of the
7509 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
7512 SDValue LHS = Cmp.getOperand(0);
7513 SDValue RHS = Cmp.getOperand(1);
7515 assert(LHS.getValueType() == RHS.getValueType() &&
7516 "Expected the value type to be the same for both operands!");
7517 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
7520 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
7521 std::swap(LHS, RHS);
7523 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
7526 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
7527 LHS.getOpcode() == ISD::SRL)
7530 // Fold the compare into the branch instruction.
7532 if (CC == ARM64CC::EQ)
7533 BR = DAG.getNode(ARM64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7535 BR = DAG.getNode(ARM64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7537 // Do not add new nodes to DAG combiner worklist.
7538 DCI.CombineTo(N, BR, false);
7543 // vselect (v1i1 setcc) ->
7544 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
7545 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
7546 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
7548 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
7549 SDValue N0 = N->getOperand(0);
7550 EVT CCVT = N0.getValueType();
7552 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
7553 CCVT.getVectorElementType() != MVT::i1)
7556 EVT ResVT = N->getValueType(0);
7557 EVT CmpVT = N0.getOperand(0).getValueType();
7558 // Only combine when the result type is of the same size as the compared
7560 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
7563 SDValue IfTrue = N->getOperand(1);
7564 SDValue IfFalse = N->getOperand(2);
7566 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
7567 N0.getOperand(0), N0.getOperand(1),
7568 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7569 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
7573 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
7574 /// the compare-mask instructions rather than going via NZCV, even if LHS and
7575 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
7576 /// with a vector one followed by a DUP shuffle on the result.
7577 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
7578 SDValue N0 = N->getOperand(0);
7579 EVT ResVT = N->getValueType(0);
7581 if (!N->getOperand(1).getValueType().isVector())
7584 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
7589 EVT SrcVT = N0.getOperand(0).getValueType();
7590 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT,
7591 ResVT.getSizeInBits() / SrcVT.getSizeInBits());
7592 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
7594 // First perform a vector comparison, where lane 0 is the one we're interested
7597 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
7599 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
7600 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
7602 // Now duplicate the comparison mask we want across all other lanes.
7603 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
7604 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
7605 Mask = DAG.getNode(ISD::BITCAST, DL, ResVT.changeVectorElementTypeToInteger(),
7608 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
7611 SDValue ARM64TargetLowering::PerformDAGCombine(SDNode *N,
7612 DAGCombinerInfo &DCI) const {
7613 SelectionDAG &DAG = DCI.DAG;
7614 switch (N->getOpcode()) {
7619 return performAddSubLongCombine(N, DCI, DAG);
7621 return performXorCombine(N, DAG, DCI, Subtarget);
7623 return performMulCombine(N, DAG, DCI, Subtarget);
7624 case ISD::SINT_TO_FP:
7625 case ISD::UINT_TO_FP:
7626 return performIntToFpCombine(N, DAG);
7628 return performORCombine(N, DCI, Subtarget);
7629 case ISD::INTRINSIC_WO_CHAIN:
7630 return performIntrinsicCombine(N, DCI, Subtarget);
7631 case ISD::ANY_EXTEND:
7632 case ISD::ZERO_EXTEND:
7633 case ISD::SIGN_EXTEND:
7634 return performExtendCombine(N, DCI, DAG);
7636 return performBitcastCombine(N, DCI, DAG);
7637 case ISD::CONCAT_VECTORS:
7638 return performConcatVectorsCombine(N, DCI, DAG);
7640 return performSelectCombine(N, DAG);
7642 return performVSelectCombine(N, DCI.DAG);
7644 return performSTORECombine(N, DCI, DAG, Subtarget);
7645 case ARM64ISD::BRCOND:
7646 return performBRCONDCombine(N, DCI, DAG);
7648 return performPostLD1Combine(N, DCI, false);
7649 case ISD::INSERT_VECTOR_ELT:
7650 return performPostLD1Combine(N, DCI, true);
7651 case ISD::INTRINSIC_VOID:
7652 case ISD::INTRINSIC_W_CHAIN:
7653 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7654 case Intrinsic::arm64_neon_ld2:
7655 case Intrinsic::arm64_neon_ld3:
7656 case Intrinsic::arm64_neon_ld4:
7657 case Intrinsic::arm64_neon_ld1x2:
7658 case Intrinsic::arm64_neon_ld1x3:
7659 case Intrinsic::arm64_neon_ld1x4:
7660 case Intrinsic::arm64_neon_ld2lane:
7661 case Intrinsic::arm64_neon_ld3lane:
7662 case Intrinsic::arm64_neon_ld4lane:
7663 case Intrinsic::arm64_neon_ld2r:
7664 case Intrinsic::arm64_neon_ld3r:
7665 case Intrinsic::arm64_neon_ld4r:
7666 case Intrinsic::arm64_neon_st2:
7667 case Intrinsic::arm64_neon_st3:
7668 case Intrinsic::arm64_neon_st4:
7669 case Intrinsic::arm64_neon_st1x2:
7670 case Intrinsic::arm64_neon_st1x3:
7671 case Intrinsic::arm64_neon_st1x4:
7672 case Intrinsic::arm64_neon_st2lane:
7673 case Intrinsic::arm64_neon_st3lane:
7674 case Intrinsic::arm64_neon_st4lane:
7675 return performNEONPostLDSTCombine(N, DCI, DAG);
7683 // Check if the return value is used as only a return value, as otherwise
7684 // we can't perform a tail-call. In particular, we need to check for
7685 // target ISD nodes that are returns and any other "odd" constructs
7686 // that the generic analysis code won't necessarily catch.
7687 bool ARM64TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
7688 if (N->getNumValues() != 1)
7690 if (!N->hasNUsesOfValue(1, 0))
7693 SDValue TCChain = Chain;
7694 SDNode *Copy = *N->use_begin();
7695 if (Copy->getOpcode() == ISD::CopyToReg) {
7696 // If the copy has a glue operand, we conservatively assume it isn't safe to
7697 // perform a tail call.
7698 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
7701 TCChain = Copy->getOperand(0);
7702 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
7705 bool HasRet = false;
7706 for (SDNode *Node : Copy->uses()) {
7707 if (Node->getOpcode() != ARM64ISD::RET_FLAG)
7719 // Return whether the an instruction can potentially be optimized to a tail
7720 // call. This will cause the optimizers to attempt to move, or duplicate,
7721 // return instructions to help enable tail call optimizations for this
7723 bool ARM64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
7724 if (!CI->isTailCall())
7730 bool ARM64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
7732 ISD::MemIndexedMode &AM,
7734 SelectionDAG &DAG) const {
7735 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
7738 Base = Op->getOperand(0);
7739 // All of the indexed addressing mode instructions take a signed
7740 // 9 bit immediate offset.
7741 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
7742 int64_t RHSC = (int64_t)RHS->getZExtValue();
7743 if (RHSC >= 256 || RHSC <= -256)
7745 IsInc = (Op->getOpcode() == ISD::ADD);
7746 Offset = Op->getOperand(1);
7752 bool ARM64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
7754 ISD::MemIndexedMode &AM,
7755 SelectionDAG &DAG) const {
7758 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7759 VT = LD->getMemoryVT();
7760 Ptr = LD->getBasePtr();
7761 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7762 VT = ST->getMemoryVT();
7763 Ptr = ST->getBasePtr();
7768 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
7770 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
7774 bool ARM64TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
7777 ISD::MemIndexedMode &AM,
7778 SelectionDAG &DAG) const {
7781 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7782 VT = LD->getMemoryVT();
7783 Ptr = LD->getBasePtr();
7784 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7785 VT = ST->getMemoryVT();
7786 Ptr = ST->getBasePtr();
7791 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
7793 // Post-indexing updates the base, so it's not a valid transform
7794 // if that's not the same as the load's pointer.
7797 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
7801 void ARM64TargetLowering::ReplaceNodeResults(SDNode *N,
7802 SmallVectorImpl<SDValue> &Results,
7803 SelectionDAG &DAG) const {
7804 switch (N->getOpcode()) {
7806 llvm_unreachable("Don't know how to custom expand this");
7807 case ISD::FP_TO_UINT:
7808 case ISD::FP_TO_SINT:
7809 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
7810 // Let normal code take care of it by not adding anything to Results.
7815 bool ARM64TargetLowering::shouldExpandAtomicInIR(Instruction *Inst) const {
7816 // Loads and stores less than 128-bits are already atomic; ones above that
7817 // are doomed anyway, so defer to the default libcall and blame the OS when
7819 if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
7820 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() == 128;
7821 else if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
7822 return LI->getType()->getPrimitiveSizeInBits() == 128;
7824 // For the real atomic operations, we have ldxr/stxr up to 128 bits.
7825 return Inst->getType()->getPrimitiveSizeInBits() <= 128;
7828 Value *ARM64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
7829 AtomicOrdering Ord) const {
7830 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7831 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
7833 Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent;
7835 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
7836 // intrinsic must return {i64, i64} and we have to recombine them into a
7837 // single i128 here.
7838 if (ValTy->getPrimitiveSizeInBits() == 128) {
7840 IsAcquire ? Intrinsic::arm64_ldaxp : Intrinsic::arm64_ldxp;
7841 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
7843 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
7844 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
7846 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
7847 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
7848 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
7849 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
7850 return Builder.CreateOr(
7851 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
7854 Type *Tys[] = { Addr->getType() };
7856 IsAcquire ? Intrinsic::arm64_ldaxr : Intrinsic::arm64_ldxr;
7857 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
7859 return Builder.CreateTruncOrBitCast(
7860 Builder.CreateCall(Ldxr, Addr),
7861 cast<PointerType>(Addr->getType())->getElementType());
7864 Value *ARM64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
7865 Value *Val, Value *Addr,
7866 AtomicOrdering Ord) const {
7867 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7869 Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent;
7871 // Since the intrinsics must have legal type, the i128 intrinsics take two
7872 // parameters: "i64, i64". We must marshal Val into the appropriate form
7874 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
7876 IsRelease ? Intrinsic::arm64_stlxp : Intrinsic::arm64_stxp;
7877 Function *Stxr = Intrinsic::getDeclaration(M, Int);
7878 Type *Int64Ty = Type::getInt64Ty(M->getContext());
7880 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
7881 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
7882 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
7883 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
7887 IsRelease ? Intrinsic::arm64_stlxr : Intrinsic::arm64_stxr;
7888 Type *Tys[] = { Addr->getType() };
7889 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
7891 return Builder.CreateCall2(
7892 Stxr, Builder.CreateZExtOrBitCast(
7893 Val, Stxr->getFunctionType()->getParamType(0)),