1 //===-- ARM64ISelDAGToDAG.cpp - A dag to dag inst selector for ARM64 ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM64 target.
12 //===----------------------------------------------------------------------===//
14 #include "ARM64TargetMachine.h"
15 #include "MCTargetDesc/ARM64AddressingModes.h"
16 #include "llvm/ADT/APSInt.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/IR/Function.h" // To access function attributes.
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/IR/Intrinsics.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "arm64-isel"
30 //===--------------------------------------------------------------------===//
31 /// ARM64DAGToDAGISel - ARM64 specific code to select ARM64 machine
32 /// instructions for SelectionDAG operations.
36 class ARM64DAGToDAGISel : public SelectionDAGISel {
37 ARM64TargetMachine &TM;
39 /// Subtarget - Keep a pointer to the ARM64Subtarget around so that we can
40 /// make the right decision when generating code for different targets.
41 const ARM64Subtarget *Subtarget;
46 explicit ARM64DAGToDAGISel(ARM64TargetMachine &tm, CodeGenOpt::Level OptLevel)
47 : SelectionDAGISel(tm, OptLevel), TM(tm),
48 Subtarget(nullptr), ForCodeSize(false) {}
50 const char *getPassName() const override {
51 return "ARM64 Instruction Selection";
54 bool runOnMachineFunction(MachineFunction &MF) override {
55 AttributeSet FnAttrs = MF.getFunction()->getAttributes();
57 FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
58 Attribute::OptimizeForSize) ||
59 FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
60 Subtarget = &TM.getSubtarget<ARM64Subtarget>();
61 return SelectionDAGISel::runOnMachineFunction(MF);
64 SDNode *Select(SDNode *Node) override;
66 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
67 /// inline asm expressions.
68 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
70 std::vector<SDValue> &OutOps) override;
72 SDNode *SelectMLAV64LaneV128(SDNode *N);
73 SDNode *SelectMULLV64LaneV128(unsigned IntNo, SDNode *N);
74 bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift);
75 bool SelectArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
76 bool SelectNegArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
77 bool SelectArithShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
78 return SelectShiftedRegister(N, false, Reg, Shift);
80 bool SelectLogicalShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
81 return SelectShiftedRegister(N, true, Reg, Shift);
83 bool SelectAddrModeIndexed8(SDValue N, SDValue &Base, SDValue &OffImm) {
84 return SelectAddrModeIndexed(N, 1, Base, OffImm);
86 bool SelectAddrModeIndexed16(SDValue N, SDValue &Base, SDValue &OffImm) {
87 return SelectAddrModeIndexed(N, 2, Base, OffImm);
89 bool SelectAddrModeIndexed32(SDValue N, SDValue &Base, SDValue &OffImm) {
90 return SelectAddrModeIndexed(N, 4, Base, OffImm);
92 bool SelectAddrModeIndexed64(SDValue N, SDValue &Base, SDValue &OffImm) {
93 return SelectAddrModeIndexed(N, 8, Base, OffImm);
95 bool SelectAddrModeIndexed128(SDValue N, SDValue &Base, SDValue &OffImm) {
96 return SelectAddrModeIndexed(N, 16, Base, OffImm);
98 bool SelectAddrModeUnscaled8(SDValue N, SDValue &Base, SDValue &OffImm) {
99 return SelectAddrModeUnscaled(N, 1, Base, OffImm);
101 bool SelectAddrModeUnscaled16(SDValue N, SDValue &Base, SDValue &OffImm) {
102 return SelectAddrModeUnscaled(N, 2, Base, OffImm);
104 bool SelectAddrModeUnscaled32(SDValue N, SDValue &Base, SDValue &OffImm) {
105 return SelectAddrModeUnscaled(N, 4, Base, OffImm);
107 bool SelectAddrModeUnscaled64(SDValue N, SDValue &Base, SDValue &OffImm) {
108 return SelectAddrModeUnscaled(N, 8, Base, OffImm);
110 bool SelectAddrModeUnscaled128(SDValue N, SDValue &Base, SDValue &OffImm) {
111 return SelectAddrModeUnscaled(N, 16, Base, OffImm);
115 bool SelectAddrModeWRO(SDValue N, SDValue &Base, SDValue &Offset,
116 SDValue &SignExtend, SDValue &DoShift) {
117 return SelectAddrModeWRO(N, Width / 8, Base, Offset, SignExtend, DoShift);
121 bool SelectAddrModeXRO(SDValue N, SDValue &Base, SDValue &Offset,
122 SDValue &SignExtend, SDValue &DoShift) {
123 return SelectAddrModeXRO(N, Width / 8, Base, Offset, SignExtend, DoShift);
127 /// Form sequences of consecutive 64/128-bit registers for use in NEON
128 /// instructions making use of a vector-list (e.g. ldN, tbl). Vecs must have
129 /// between 1 and 4 elements. If it contains a single element that is returned
130 /// unchanged; otherwise a REG_SEQUENCE value is returned.
131 SDValue createDTuple(ArrayRef<SDValue> Vecs);
132 SDValue createQTuple(ArrayRef<SDValue> Vecs);
134 /// Generic helper for the createDTuple/createQTuple
135 /// functions. Those should almost always be called instead.
136 SDValue createTuple(ArrayRef<SDValue> Vecs, unsigned RegClassIDs[],
139 SDNode *SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
141 SDNode *SelectIndexedLoad(SDNode *N, bool &Done);
143 SDNode *SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
145 SDNode *SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
147 SDNode *SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
148 SDNode *SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
150 SDNode *SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
151 SDNode *SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
152 SDNode *SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
153 SDNode *SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
155 SDNode *SelectSIMDAddSubNarrowing(unsigned IntNo, SDNode *Node);
156 SDNode *SelectSIMDXtnNarrowing(unsigned IntNo, SDNode *Node);
158 SDNode *SelectBitfieldExtractOp(SDNode *N);
159 SDNode *SelectBitfieldInsertOp(SDNode *N);
161 SDNode *SelectLIBM(SDNode *N);
163 // Include the pieces autogenerated from the target description.
164 #include "ARM64GenDAGISel.inc"
167 bool SelectShiftedRegister(SDValue N, bool AllowROR, SDValue &Reg,
169 bool SelectAddrModeIndexed(SDValue N, unsigned Size, SDValue &Base,
171 bool SelectAddrModeUnscaled(SDValue N, unsigned Size, SDValue &Base,
173 bool SelectAddrModeWRO(SDValue N, unsigned Size, SDValue &Base,
174 SDValue &Offset, SDValue &SignExtend,
176 bool SelectAddrModeXRO(SDValue N, unsigned Size, SDValue &Base,
177 SDValue &Offset, SDValue &SignExtend,
179 bool isWorthFolding(SDValue V) const;
180 bool SelectExtendedSHL(SDValue N, unsigned Size, bool WantExtend,
181 SDValue &Offset, SDValue &SignExtend);
183 template<unsigned RegWidth>
184 bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos) {
185 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth);
188 bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos, unsigned Width);
190 } // end anonymous namespace
192 /// isIntImmediate - This method tests to see if the node is a constant
193 /// operand. If so Imm will receive the 32-bit value.
194 static bool isIntImmediate(const SDNode *N, uint64_t &Imm) {
195 if (const ConstantSDNode *C = dyn_cast<const ConstantSDNode>(N)) {
196 Imm = C->getZExtValue();
202 // isIntImmediate - This method tests to see if a constant operand.
203 // If so Imm will receive the value.
204 static bool isIntImmediate(SDValue N, uint64_t &Imm) {
205 return isIntImmediate(N.getNode(), Imm);
208 // isOpcWithIntImmediate - This method tests to see if the node is a specific
209 // opcode and that it has a immediate integer right operand.
210 // If so Imm will receive the 32 bit value.
211 static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc,
213 return N->getOpcode() == Opc &&
214 isIntImmediate(N->getOperand(1).getNode(), Imm);
217 bool ARM64DAGToDAGISel::SelectInlineAsmMemoryOperand(
218 const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) {
219 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
220 // Require the address to be in a register. That is safe for all ARM64
221 // variants and it is hard to do anything much smarter without knowing
222 // how the operand is used.
223 OutOps.push_back(Op);
227 /// SelectArithImmed - Select an immediate value that can be represented as
228 /// a 12-bit value shifted left by either 0 or 12. If so, return true with
229 /// Val set to the 12-bit value and Shift set to the shifter operand.
230 bool ARM64DAGToDAGISel::SelectArithImmed(SDValue N, SDValue &Val,
232 // This function is called from the addsub_shifted_imm ComplexPattern,
233 // which lists [imm] as the list of opcode it's interested in, however
234 // we still need to check whether the operand is actually an immediate
235 // here because the ComplexPattern opcode list is only used in
236 // root-level opcode matching.
237 if (!isa<ConstantSDNode>(N.getNode()))
240 uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
243 if (Immed >> 12 == 0) {
245 } else if ((Immed & 0xfff) == 0 && Immed >> 24 == 0) {
251 unsigned ShVal = ARM64_AM::getShifterImm(ARM64_AM::LSL, ShiftAmt);
252 Val = CurDAG->getTargetConstant(Immed, MVT::i32);
253 Shift = CurDAG->getTargetConstant(ShVal, MVT::i32);
257 /// SelectNegArithImmed - As above, but negates the value before trying to
259 bool ARM64DAGToDAGISel::SelectNegArithImmed(SDValue N, SDValue &Val,
261 // This function is called from the addsub_shifted_imm ComplexPattern,
262 // which lists [imm] as the list of opcode it's interested in, however
263 // we still need to check whether the operand is actually an immediate
264 // here because the ComplexPattern opcode list is only used in
265 // root-level opcode matching.
266 if (!isa<ConstantSDNode>(N.getNode()))
269 // The immediate operand must be a 24-bit zero-extended immediate.
270 uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
272 // This negation is almost always valid, but "cmp wN, #0" and "cmn wN, #0"
273 // have the opposite effect on the C flag, so this pattern mustn't match under
274 // those circumstances.
278 if (N.getValueType() == MVT::i32)
279 Immed = ~((uint32_t)Immed) + 1;
281 Immed = ~Immed + 1ULL;
282 if (Immed & 0xFFFFFFFFFF000000ULL)
285 Immed &= 0xFFFFFFULL;
286 return SelectArithImmed(CurDAG->getConstant(Immed, MVT::i32), Val, Shift);
289 /// getShiftTypeForNode - Translate a shift node to the corresponding
291 static ARM64_AM::ShiftExtendType getShiftTypeForNode(SDValue N) {
292 switch (N.getOpcode()) {
294 return ARM64_AM::InvalidShiftExtend;
296 return ARM64_AM::LSL;
298 return ARM64_AM::LSR;
300 return ARM64_AM::ASR;
302 return ARM64_AM::ROR;
306 /// \brief Determine wether it is worth to fold V into an extended register.
307 bool ARM64DAGToDAGISel::isWorthFolding(SDValue V) const {
308 // it hurts if the a value is used at least twice, unless we are optimizing
310 if (ForCodeSize || V.hasOneUse())
315 /// SelectShiftedRegister - Select a "shifted register" operand. If the value
316 /// is not shifted, set the Shift operand to default of "LSL 0". The logical
317 /// instructions allow the shifted register to be rotated, but the arithmetic
318 /// instructions do not. The AllowROR parameter specifies whether ROR is
320 bool ARM64DAGToDAGISel::SelectShiftedRegister(SDValue N, bool AllowROR,
321 SDValue &Reg, SDValue &Shift) {
322 ARM64_AM::ShiftExtendType ShType = getShiftTypeForNode(N);
323 if (ShType == ARM64_AM::InvalidShiftExtend)
325 if (!AllowROR && ShType == ARM64_AM::ROR)
328 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
329 unsigned BitSize = N.getValueType().getSizeInBits();
330 unsigned Val = RHS->getZExtValue() & (BitSize - 1);
331 unsigned ShVal = ARM64_AM::getShifterImm(ShType, Val);
333 Reg = N.getOperand(0);
334 Shift = CurDAG->getTargetConstant(ShVal, MVT::i32);
335 return isWorthFolding(N);
341 /// getExtendTypeForNode - Translate an extend node to the corresponding
342 /// ExtendType value.
343 static ARM64_AM::ShiftExtendType
344 getExtendTypeForNode(SDValue N, bool IsLoadStore = false) {
345 if (N.getOpcode() == ISD::SIGN_EXTEND ||
346 N.getOpcode() == ISD::SIGN_EXTEND_INREG) {
348 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG)
349 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT();
351 SrcVT = N.getOperand(0).getValueType();
353 if (!IsLoadStore && SrcVT == MVT::i8)
354 return ARM64_AM::SXTB;
355 else if (!IsLoadStore && SrcVT == MVT::i16)
356 return ARM64_AM::SXTH;
357 else if (SrcVT == MVT::i32)
358 return ARM64_AM::SXTW;
359 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
361 return ARM64_AM::InvalidShiftExtend;
362 } else if (N.getOpcode() == ISD::ZERO_EXTEND ||
363 N.getOpcode() == ISD::ANY_EXTEND) {
364 EVT SrcVT = N.getOperand(0).getValueType();
365 if (!IsLoadStore && SrcVT == MVT::i8)
366 return ARM64_AM::UXTB;
367 else if (!IsLoadStore && SrcVT == MVT::i16)
368 return ARM64_AM::UXTH;
369 else if (SrcVT == MVT::i32)
370 return ARM64_AM::UXTW;
371 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
373 return ARM64_AM::InvalidShiftExtend;
374 } else if (N.getOpcode() == ISD::AND) {
375 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
377 return ARM64_AM::InvalidShiftExtend;
378 uint64_t AndMask = CSD->getZExtValue();
382 return ARM64_AM::InvalidShiftExtend;
384 return !IsLoadStore ? ARM64_AM::UXTB : ARM64_AM::InvalidShiftExtend;
386 return !IsLoadStore ? ARM64_AM::UXTH : ARM64_AM::InvalidShiftExtend;
388 return ARM64_AM::UXTW;
392 return ARM64_AM::InvalidShiftExtend;
395 // Helper for SelectMLAV64LaneV128 - Recognize high lane extracts.
396 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) {
397 if (DL->getOpcode() != ARM64ISD::DUPLANE16 &&
398 DL->getOpcode() != ARM64ISD::DUPLANE32)
401 SDValue SV = DL->getOperand(0);
402 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR)
405 SDValue EV = SV.getOperand(1);
406 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR)
409 ConstantSDNode *DLidx = cast<ConstantSDNode>(DL->getOperand(1).getNode());
410 ConstantSDNode *EVidx = cast<ConstantSDNode>(EV.getOperand(1).getNode());
411 LaneIdx = DLidx->getSExtValue() + EVidx->getSExtValue();
412 LaneOp = EV.getOperand(0);
417 // Helper for SelectOpcV64LaneV128 - Recogzine operatinos where one operand is a
418 // high lane extract.
419 static bool checkV64LaneV128(SDValue Op0, SDValue Op1, SDValue &StdOp,
420 SDValue &LaneOp, int &LaneIdx) {
422 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) {
424 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx))
431 /// SelectMLAV64LaneV128 - ARM64 supports vector MLAs where one multiplicand is
432 /// a lane in the upper half of a 128-bit vector. Recognize and select this so
433 /// that we don't emit unnecessary lane extracts.
434 SDNode *ARM64DAGToDAGISel::SelectMLAV64LaneV128(SDNode *N) {
435 SDValue Op0 = N->getOperand(0);
436 SDValue Op1 = N->getOperand(1);
437 SDValue MLAOp1; // Will hold ordinary multiplicand for MLA.
438 SDValue MLAOp2; // Will hold lane-accessed multiplicand for MLA.
439 int LaneIdx = -1; // Will hold the lane index.
441 if (Op1.getOpcode() != ISD::MUL ||
442 !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
445 if (Op1.getOpcode() != ISD::MUL ||
446 !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
451 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, MVT::i64);
453 SDValue Ops[] = { Op0, MLAOp1, MLAOp2, LaneIdxVal };
455 unsigned MLAOpc = ~0U;
457 switch (N->getSimpleValueType(0).SimpleTy) {
459 llvm_unreachable("Unrecognized MLA.");
461 MLAOpc = ARM64::MLAv4i16_indexed;
464 MLAOpc = ARM64::MLAv8i16_indexed;
467 MLAOpc = ARM64::MLAv2i32_indexed;
470 MLAOpc = ARM64::MLAv4i32_indexed;
474 return CurDAG->getMachineNode(MLAOpc, SDLoc(N), N->getValueType(0), Ops);
477 SDNode *ARM64DAGToDAGISel::SelectMULLV64LaneV128(unsigned IntNo, SDNode *N) {
482 if (!checkV64LaneV128(N->getOperand(1), N->getOperand(2), SMULLOp0, SMULLOp1,
486 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, MVT::i64);
488 SDValue Ops[] = { SMULLOp0, SMULLOp1, LaneIdxVal };
490 unsigned SMULLOpc = ~0U;
492 if (IntNo == Intrinsic::arm64_neon_smull) {
493 switch (N->getSimpleValueType(0).SimpleTy) {
495 llvm_unreachable("Unrecognized SMULL.");
497 SMULLOpc = ARM64::SMULLv4i16_indexed;
500 SMULLOpc = ARM64::SMULLv2i32_indexed;
503 } else if (IntNo == Intrinsic::arm64_neon_umull) {
504 switch (N->getSimpleValueType(0).SimpleTy) {
506 llvm_unreachable("Unrecognized SMULL.");
508 SMULLOpc = ARM64::UMULLv4i16_indexed;
511 SMULLOpc = ARM64::UMULLv2i32_indexed;
515 llvm_unreachable("Unrecognized intrinsic.");
517 return CurDAG->getMachineNode(SMULLOpc, SDLoc(N), N->getValueType(0), Ops);
520 /// SelectArithExtendedRegister - Select a "extended register" operand. This
521 /// operand folds in an extend followed by an optional left shift.
522 bool ARM64DAGToDAGISel::SelectArithExtendedRegister(SDValue N, SDValue &Reg,
524 unsigned ShiftVal = 0;
525 ARM64_AM::ShiftExtendType Ext;
527 if (N.getOpcode() == ISD::SHL) {
528 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
531 ShiftVal = CSD->getZExtValue();
535 Ext = getExtendTypeForNode(N.getOperand(0));
536 if (Ext == ARM64_AM::InvalidShiftExtend)
539 Reg = N.getOperand(0).getOperand(0);
541 Ext = getExtendTypeForNode(N);
542 if (Ext == ARM64_AM::InvalidShiftExtend)
545 Reg = N.getOperand(0);
548 // ARM64 mandates that the RHS of the operation must use the smallest
549 // register classs that could contain the size being extended from. Thus,
550 // if we're folding a (sext i8), we need the RHS to be a GPR32, even though
551 // there might not be an actual 32-bit value in the program. We can
552 // (harmlessly) synthesize one by injected an EXTRACT_SUBREG here.
553 assert(Ext != ARM64_AM::UXTX && Ext != ARM64_AM::SXTX);
554 if (Reg.getValueType() == MVT::i64) {
555 SDValue SubReg = CurDAG->getTargetConstant(ARM64::sub_32, MVT::i32);
556 MachineSDNode *Node = CurDAG->getMachineNode(
557 TargetOpcode::EXTRACT_SUBREG, SDLoc(N), MVT::i32, Reg, SubReg);
558 Reg = SDValue(Node, 0);
561 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), MVT::i32);
562 return isWorthFolding(N);
565 /// SelectAddrModeIndexed - Select a "register plus scaled unsigned 12-bit
566 /// immediate" address. The "Size" argument is the size in bytes of the memory
567 /// reference, which determines the scale.
568 bool ARM64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size,
569 SDValue &Base, SDValue &OffImm) {
570 const TargetLowering *TLI = getTargetLowering();
571 if (N.getOpcode() == ISD::FrameIndex) {
572 int FI = cast<FrameIndexSDNode>(N)->getIndex();
573 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
574 OffImm = CurDAG->getTargetConstant(0, MVT::i64);
578 if (N.getOpcode() == ARM64ISD::ADDlow) {
579 GlobalAddressSDNode *GAN =
580 dyn_cast<GlobalAddressSDNode>(N.getOperand(1).getNode());
581 Base = N.getOperand(0);
582 OffImm = N.getOperand(1);
586 const GlobalValue *GV = GAN->getGlobal();
587 unsigned Alignment = GV->getAlignment();
588 const DataLayout *DL = TLI->getDataLayout();
589 if (Alignment == 0 && !Subtarget->isTargetDarwin())
590 Alignment = DL->getABITypeAlignment(GV->getType()->getElementType());
592 if (Alignment >= Size)
596 if (CurDAG->isBaseWithConstantOffset(N)) {
597 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
598 int64_t RHSC = (int64_t)RHS->getZExtValue();
599 unsigned Scale = Log2_32(Size);
600 if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 && RHSC < (0x1000 << Scale)) {
601 Base = N.getOperand(0);
602 if (Base.getOpcode() == ISD::FrameIndex) {
603 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
604 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
606 OffImm = CurDAG->getTargetConstant(RHSC >> Scale, MVT::i64);
612 // Before falling back to our general case, check if the unscaled
613 // instructions can handle this. If so, that's preferable.
614 if (SelectAddrModeUnscaled(N, Size, Base, OffImm))
617 // Base only. The address will be materialized into a register before
618 // the memory is accessed.
619 // add x0, Xbase, #offset
622 OffImm = CurDAG->getTargetConstant(0, MVT::i64);
626 /// SelectAddrModeUnscaled - Select a "register plus unscaled signed 9-bit
627 /// immediate" address. This should only match when there is an offset that
628 /// is not valid for a scaled immediate addressing mode. The "Size" argument
629 /// is the size in bytes of the memory reference, which is needed here to know
630 /// what is valid for a scaled immediate.
631 bool ARM64DAGToDAGISel::SelectAddrModeUnscaled(SDValue N, unsigned Size,
632 SDValue &Base, SDValue &OffImm) {
633 if (!CurDAG->isBaseWithConstantOffset(N))
635 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
636 int64_t RHSC = RHS->getSExtValue();
637 // If the offset is valid as a scaled immediate, don't match here.
638 if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 &&
639 RHSC < (0x1000 << Log2_32(Size)))
641 if (RHSC >= -256 && RHSC < 256) {
642 Base = N.getOperand(0);
643 if (Base.getOpcode() == ISD::FrameIndex) {
644 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
645 const TargetLowering *TLI = getTargetLowering();
646 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
648 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i64);
655 static SDValue Widen(SelectionDAG *CurDAG, SDValue N) {
656 SDValue SubReg = CurDAG->getTargetConstant(ARM64::sub_32, MVT::i32);
657 SDValue ImpDef = SDValue(
658 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, SDLoc(N), MVT::i64),
660 MachineSDNode *Node = CurDAG->getMachineNode(
661 TargetOpcode::INSERT_SUBREG, SDLoc(N), MVT::i64, ImpDef, N, SubReg);
662 return SDValue(Node, 0);
665 /// \brief Check if the given SHL node (\p N), can be used to form an
666 /// extended register for an addressing mode.
667 bool ARM64DAGToDAGISel::SelectExtendedSHL(SDValue N, unsigned Size,
668 bool WantExtend, SDValue &Offset,
669 SDValue &SignExtend) {
670 assert(N.getOpcode() == ISD::SHL && "Invalid opcode.");
671 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
672 if (!CSD || (CSD->getZExtValue() & 0x7) != CSD->getZExtValue())
676 ARM64_AM::ShiftExtendType Ext = getExtendTypeForNode(N.getOperand(0), true);
677 if (Ext == ARM64_AM::InvalidShiftExtend)
680 Offset = N.getOperand(0).getOperand(0);
681 SignExtend = CurDAG->getTargetConstant(Ext == ARM64_AM::SXTW, MVT::i32);
683 Offset = N.getOperand(0);
684 SignExtend = CurDAG->getTargetConstant(0, MVT::i32);
687 unsigned LegalShiftVal = Log2_32(Size);
688 unsigned ShiftVal = CSD->getZExtValue();
690 if (ShiftVal != 0 && ShiftVal != LegalShiftVal)
693 if (isWorthFolding(N))
699 bool ARM64DAGToDAGISel::SelectAddrModeWRO(SDValue N, unsigned Size,
700 SDValue &Base, SDValue &Offset,
703 if (N.getOpcode() != ISD::ADD)
705 SDValue LHS = N.getOperand(0);
706 SDValue RHS = N.getOperand(1);
708 // We don't want to match immediate adds here, because they are better lowered
709 // to the register-immediate addressing modes.
710 if (isa<ConstantSDNode>(LHS) || isa<ConstantSDNode>(RHS))
713 // Check if this particular node is reused in any non-memory related
714 // operation. If yes, do not try to fold this node into the address
715 // computation, since the computation will be kept.
716 const SDNode *Node = N.getNode();
717 for (SDNode *UI : Node->uses()) {
718 if (!isa<MemSDNode>(*UI))
722 // Remember if it is worth folding N when it produces extended register.
723 bool IsExtendedRegisterWorthFolding = isWorthFolding(N);
725 // Try to match a shifted extend on the RHS.
726 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
727 SelectExtendedSHL(RHS, Size, true, Offset, SignExtend)) {
729 DoShift = CurDAG->getTargetConstant(true, MVT::i32);
733 // Try to match a shifted extend on the LHS.
734 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
735 SelectExtendedSHL(LHS, Size, true, Offset, SignExtend)) {
737 DoShift = CurDAG->getTargetConstant(true, MVT::i32);
741 // There was no shift, whatever else we find.
742 DoShift = CurDAG->getTargetConstant(false, MVT::i32);
744 ARM64_AM::ShiftExtendType Ext = ARM64_AM::InvalidShiftExtend;
745 // Try to match an unshifted extend on the LHS.
746 if (IsExtendedRegisterWorthFolding &&
747 (Ext = getExtendTypeForNode(LHS, true)) != ARM64_AM::InvalidShiftExtend) {
749 Offset = LHS.getOperand(0);
750 SignExtend = CurDAG->getTargetConstant(Ext == ARM64_AM::SXTW, MVT::i32);
751 if (isWorthFolding(LHS))
755 // Try to match an unshifted extend on the RHS.
756 if (IsExtendedRegisterWorthFolding &&
757 (Ext = getExtendTypeForNode(RHS, true)) != ARM64_AM::InvalidShiftExtend) {
759 Offset = RHS.getOperand(0);
760 SignExtend = CurDAG->getTargetConstant(Ext == ARM64_AM::SXTW, MVT::i32);
761 if (isWorthFolding(RHS))
768 bool ARM64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
769 SDValue &Base, SDValue &Offset,
772 if (N.getOpcode() != ISD::ADD)
774 SDValue LHS = N.getOperand(0);
775 SDValue RHS = N.getOperand(1);
777 // We don't want to match immediate adds here, because they are better lowered
778 // to the register-immediate addressing modes.
779 if (isa<ConstantSDNode>(LHS) || isa<ConstantSDNode>(RHS))
782 // Check if this particular node is reused in any non-memory related
783 // operation. If yes, do not try to fold this node into the address
784 // computation, since the computation will be kept.
785 const SDNode *Node = N.getNode();
786 for (SDNode *UI : Node->uses()) {
787 if (!isa<MemSDNode>(*UI))
791 // Remember if it is worth folding N when it produces extended register.
792 bool IsExtendedRegisterWorthFolding = isWorthFolding(N);
794 // Try to match a shifted extend on the RHS.
795 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
796 SelectExtendedSHL(RHS, Size, false, Offset, SignExtend)) {
798 DoShift = CurDAG->getTargetConstant(true, MVT::i32);
802 // Try to match a shifted extend on the LHS.
803 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
804 SelectExtendedSHL(LHS, Size, false, Offset, SignExtend)) {
806 DoShift = CurDAG->getTargetConstant(true, MVT::i32);
810 // Match any non-shifted, non-extend, non-immediate add expression.
813 SignExtend = CurDAG->getTargetConstant(false, MVT::i32);
814 DoShift = CurDAG->getTargetConstant(false, MVT::i32);
815 // Reg1 + Reg2 is free: no check needed.
819 SDValue ARM64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) {
820 static unsigned RegClassIDs[] = { ARM64::DDRegClassID, ARM64::DDDRegClassID,
821 ARM64::DDDDRegClassID };
822 static unsigned SubRegs[] = { ARM64::dsub0, ARM64::dsub1,
823 ARM64::dsub2, ARM64::dsub3 };
825 return createTuple(Regs, RegClassIDs, SubRegs);
828 SDValue ARM64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) {
829 static unsigned RegClassIDs[] = { ARM64::QQRegClassID, ARM64::QQQRegClassID,
830 ARM64::QQQQRegClassID };
831 static unsigned SubRegs[] = { ARM64::qsub0, ARM64::qsub1,
832 ARM64::qsub2, ARM64::qsub3 };
834 return createTuple(Regs, RegClassIDs, SubRegs);
837 SDValue ARM64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs,
838 unsigned RegClassIDs[],
839 unsigned SubRegs[]) {
840 // There's no special register-class for a vector-list of 1 element: it's just
842 if (Regs.size() == 1)
845 assert(Regs.size() >= 2 && Regs.size() <= 4);
847 SDLoc DL(Regs[0].getNode());
849 SmallVector<SDValue, 4> Ops;
851 // First operand of REG_SEQUENCE is the desired RegClass.
853 CurDAG->getTargetConstant(RegClassIDs[Regs.size() - 2], MVT::i32));
855 // Then we get pairs of source & subregister-position for the components.
856 for (unsigned i = 0; i < Regs.size(); ++i) {
857 Ops.push_back(Regs[i]);
858 Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], MVT::i32));
862 CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::Untyped, Ops);
863 return SDValue(N, 0);
866 SDNode *ARM64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs,
867 unsigned Opc, bool isExt) {
869 EVT VT = N->getValueType(0);
871 unsigned ExtOff = isExt;
873 // Form a REG_SEQUENCE to force register allocation.
874 unsigned Vec0Off = ExtOff + 1;
875 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off,
876 N->op_begin() + Vec0Off + NumVecs);
877 SDValue RegSeq = createQTuple(Regs);
879 SmallVector<SDValue, 6> Ops;
881 Ops.push_back(N->getOperand(1));
882 Ops.push_back(RegSeq);
883 Ops.push_back(N->getOperand(NumVecs + ExtOff + 1));
884 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
887 SDNode *ARM64DAGToDAGISel::SelectIndexedLoad(SDNode *N, bool &Done) {
888 LoadSDNode *LD = cast<LoadSDNode>(N);
889 if (LD->isUnindexed())
891 EVT VT = LD->getMemoryVT();
892 EVT DstVT = N->getValueType(0);
893 ISD::MemIndexedMode AM = LD->getAddressingMode();
894 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
896 // We're not doing validity checking here. That was done when checking
897 // if we should mark the load as indexed or not. We're just selecting
898 // the right instruction.
901 ISD::LoadExtType ExtType = LD->getExtensionType();
902 bool InsertTo64 = false;
904 Opcode = IsPre ? ARM64::LDRXpre_isel : ARM64::LDRXpost_isel;
905 else if (VT == MVT::i32) {
906 if (ExtType == ISD::NON_EXTLOAD)
907 Opcode = IsPre ? ARM64::LDRWpre_isel : ARM64::LDRWpost_isel;
908 else if (ExtType == ISD::SEXTLOAD)
909 Opcode = IsPre ? ARM64::LDRSWpre_isel : ARM64::LDRSWpost_isel;
911 Opcode = IsPre ? ARM64::LDRWpre_isel : ARM64::LDRWpost_isel;
913 // The result of the load is only i32. It's the subreg_to_reg that makes
917 } else if (VT == MVT::i16) {
918 if (ExtType == ISD::SEXTLOAD) {
919 if (DstVT == MVT::i64)
920 Opcode = IsPre ? ARM64::LDRSHXpre_isel : ARM64::LDRSHXpost_isel;
922 Opcode = IsPre ? ARM64::LDRSHWpre_isel : ARM64::LDRSHWpost_isel;
924 Opcode = IsPre ? ARM64::LDRHHpre_isel : ARM64::LDRHHpost_isel;
925 InsertTo64 = DstVT == MVT::i64;
926 // The result of the load is only i32. It's the subreg_to_reg that makes
930 } else if (VT == MVT::i8) {
931 if (ExtType == ISD::SEXTLOAD) {
932 if (DstVT == MVT::i64)
933 Opcode = IsPre ? ARM64::LDRSBXpre_isel : ARM64::LDRSBXpost_isel;
935 Opcode = IsPre ? ARM64::LDRSBWpre_isel : ARM64::LDRSBWpost_isel;
937 Opcode = IsPre ? ARM64::LDRBBpre_isel : ARM64::LDRBBpost_isel;
938 InsertTo64 = DstVT == MVT::i64;
939 // The result of the load is only i32. It's the subreg_to_reg that makes
943 } else if (VT == MVT::f32) {
944 Opcode = IsPre ? ARM64::LDRSpre_isel : ARM64::LDRSpost_isel;
945 } else if (VT == MVT::f64 || VT.is64BitVector()) {
946 Opcode = IsPre ? ARM64::LDRDpre_isel : ARM64::LDRDpost_isel;
947 } else if (VT.is128BitVector()) {
948 Opcode = IsPre ? ARM64::LDRQpre_isel : ARM64::LDRQpost_isel;
951 SDValue Chain = LD->getChain();
952 SDValue Base = LD->getBasePtr();
953 ConstantSDNode *OffsetOp = cast<ConstantSDNode>(LD->getOffset());
954 int OffsetVal = (int)OffsetOp->getZExtValue();
955 SDValue Offset = CurDAG->getTargetConstant(OffsetVal, MVT::i64);
956 SDValue Ops[] = { Base, Offset, Chain };
957 SDNode *Res = CurDAG->getMachineNode(Opcode, SDLoc(N), DstVT, MVT::i64,
959 // Either way, we're replacing the node, so tell the caller that.
962 SDValue SubReg = CurDAG->getTargetConstant(ARM64::sub_32, MVT::i32);
963 SDNode *Sub = CurDAG->getMachineNode(
964 ARM64::SUBREG_TO_REG, SDLoc(N), MVT::i64,
965 CurDAG->getTargetConstant(0, MVT::i64), SDValue(Res, 0), SubReg);
966 ReplaceUses(SDValue(N, 0), SDValue(Sub, 0));
967 ReplaceUses(SDValue(N, 1), SDValue(Res, 1));
968 ReplaceUses(SDValue(N, 2), SDValue(Res, 2));
974 SDNode *ARM64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
975 unsigned SubRegIdx) {
977 EVT VT = N->getValueType(0);
978 SDValue Chain = N->getOperand(0);
980 SmallVector<SDValue, 6> Ops;
981 Ops.push_back(N->getOperand(2)); // Mem operand;
982 Ops.push_back(Chain);
984 std::vector<EVT> ResTys;
985 ResTys.push_back(MVT::Untyped);
986 ResTys.push_back(MVT::Other);
988 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
989 SDValue SuperReg = SDValue(Ld, 0);
990 for (unsigned i = 0; i < NumVecs; ++i)
991 ReplaceUses(SDValue(N, i),
992 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
994 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
998 SDNode *ARM64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs,
999 unsigned Opc, unsigned SubRegIdx) {
1001 EVT VT = N->getValueType(0);
1002 SDValue Chain = N->getOperand(0);
1004 SmallVector<SDValue, 6> Ops;
1005 Ops.push_back(N->getOperand(1)); // Mem operand
1006 Ops.push_back(N->getOperand(2)); // Incremental
1007 Ops.push_back(Chain);
1009 std::vector<EVT> ResTys;
1010 ResTys.push_back(MVT::i64); // Type of the write back register
1011 ResTys.push_back(MVT::Untyped);
1012 ResTys.push_back(MVT::Other);
1014 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1016 // Update uses of write back register
1017 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1019 // Update uses of vector list
1020 SDValue SuperReg = SDValue(Ld, 1);
1022 ReplaceUses(SDValue(N, 0), SuperReg);
1024 for (unsigned i = 0; i < NumVecs; ++i)
1025 ReplaceUses(SDValue(N, i),
1026 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
1029 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1033 SDNode *ARM64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
1036 EVT VT = N->getOperand(2)->getValueType(0);
1038 // Form a REG_SEQUENCE to force register allocation.
1039 bool Is128Bit = VT.getSizeInBits() == 128;
1040 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1041 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1043 SmallVector<SDValue, 6> Ops;
1044 Ops.push_back(RegSeq);
1045 Ops.push_back(N->getOperand(NumVecs + 2));
1046 Ops.push_back(N->getOperand(0));
1047 SDNode *St = CurDAG->getMachineNode(Opc, dl, N->getValueType(0), Ops);
1052 SDNode *ARM64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs,
1055 EVT VT = N->getOperand(2)->getValueType(0);
1056 SmallVector<EVT, 2> ResTys;
1057 ResTys.push_back(MVT::i64); // Type of the write back register
1058 ResTys.push_back(MVT::Other); // Type for the Chain
1060 // Form a REG_SEQUENCE to force register allocation.
1061 bool Is128Bit = VT.getSizeInBits() == 128;
1062 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1063 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1065 SmallVector<SDValue, 6> Ops;
1066 Ops.push_back(RegSeq);
1067 Ops.push_back(N->getOperand(NumVecs + 1)); // base register
1068 Ops.push_back(N->getOperand(NumVecs + 2)); // Incremental
1069 Ops.push_back(N->getOperand(0)); // Chain
1070 SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1075 /// WidenVector - Given a value in the V64 register class, produce the
1076 /// equivalent value in the V128 register class.
1081 WidenVector(SelectionDAG &DAG) : DAG(DAG) {}
1083 SDValue operator()(SDValue V64Reg) {
1084 EVT VT = V64Reg.getValueType();
1085 unsigned NarrowSize = VT.getVectorNumElements();
1086 MVT EltTy = VT.getVectorElementType().getSimpleVT();
1087 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
1091 SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, WideTy), 0);
1092 return DAG.getTargetInsertSubreg(ARM64::dsub, DL, WideTy, Undef, V64Reg);
1096 /// NarrowVector - Given a value in the V128 register class, produce the
1097 /// equivalent value in the V64 register class.
1098 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
1099 EVT VT = V128Reg.getValueType();
1100 unsigned WideSize = VT.getVectorNumElements();
1101 MVT EltTy = VT.getVectorElementType().getSimpleVT();
1102 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
1104 return DAG.getTargetExtractSubreg(ARM64::dsub, SDLoc(V128Reg), NarrowTy,
1108 SDNode *ARM64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,
1111 EVT VT = N->getValueType(0);
1112 bool Narrow = VT.getSizeInBits() == 64;
1114 // Form a REG_SEQUENCE to force register allocation.
1115 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1118 std::transform(Regs.begin(), Regs.end(), Regs.begin(),
1119 WidenVector(*CurDAG));
1121 SDValue RegSeq = createQTuple(Regs);
1123 std::vector<EVT> ResTys;
1124 ResTys.push_back(MVT::Untyped);
1125 ResTys.push_back(MVT::Other);
1128 cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1130 SmallVector<SDValue, 6> Ops;
1131 Ops.push_back(RegSeq);
1132 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
1133 Ops.push_back(N->getOperand(NumVecs + 3));
1134 Ops.push_back(N->getOperand(0));
1135 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1136 SDValue SuperReg = SDValue(Ld, 0);
1138 EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
1139 static unsigned QSubs[] = { ARM64::qsub0, ARM64::qsub1, ARM64::qsub2,
1141 for (unsigned i = 0; i < NumVecs; ++i) {
1142 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg);
1144 NV = NarrowVector(NV, *CurDAG);
1145 ReplaceUses(SDValue(N, i), NV);
1148 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1153 SDNode *ARM64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,
1156 EVT VT = N->getValueType(0);
1157 bool Narrow = VT.getSizeInBits() == 64;
1159 // Form a REG_SEQUENCE to force register allocation.
1160 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1163 std::transform(Regs.begin(), Regs.end(), Regs.begin(),
1164 WidenVector(*CurDAG));
1166 SDValue RegSeq = createQTuple(Regs);
1168 std::vector<EVT> ResTys;
1169 ResTys.push_back(MVT::i64); // Type of the write back register
1170 ResTys.push_back(MVT::Untyped);
1171 ResTys.push_back(MVT::Other);
1174 cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
1176 SmallVector<SDValue, 6> Ops;
1177 Ops.push_back(RegSeq);
1178 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64)); // Lane Number
1179 Ops.push_back(N->getOperand(NumVecs + 2)); // Base register
1180 Ops.push_back(N->getOperand(NumVecs + 3)); // Incremental
1181 Ops.push_back(N->getOperand(0));
1182 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1184 // Update uses of the write back register
1185 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1187 // Update uses of the vector list
1188 SDValue SuperReg = SDValue(Ld, 1);
1190 ReplaceUses(SDValue(N, 0),
1191 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg);
1193 EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
1194 static unsigned QSubs[] = { ARM64::qsub0, ARM64::qsub1, ARM64::qsub2,
1196 for (unsigned i = 0; i < NumVecs; ++i) {
1197 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT,
1200 NV = NarrowVector(NV, *CurDAG);
1201 ReplaceUses(SDValue(N, i), NV);
1206 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1211 SDNode *ARM64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,
1214 EVT VT = N->getOperand(2)->getValueType(0);
1215 bool Narrow = VT.getSizeInBits() == 64;
1217 // Form a REG_SEQUENCE to force register allocation.
1218 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1221 std::transform(Regs.begin(), Regs.end(), Regs.begin(),
1222 WidenVector(*CurDAG));
1224 SDValue RegSeq = createQTuple(Regs);
1227 cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1229 SmallVector<SDValue, 6> Ops;
1230 Ops.push_back(RegSeq);
1231 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
1232 Ops.push_back(N->getOperand(NumVecs + 3));
1233 Ops.push_back(N->getOperand(0));
1234 SDNode *St = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops);
1236 // Transfer memoperands.
1237 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1238 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1239 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
1244 SDNode *ARM64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
1247 EVT VT = N->getOperand(2)->getValueType(0);
1248 bool Narrow = VT.getSizeInBits() == 64;
1250 // Form a REG_SEQUENCE to force register allocation.
1251 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1254 std::transform(Regs.begin(), Regs.end(), Regs.begin(),
1255 WidenVector(*CurDAG));
1257 SDValue RegSeq = createQTuple(Regs);
1259 SmallVector<EVT, 2> ResTys;
1260 ResTys.push_back(MVT::i64); // Type of the write back register
1261 ResTys.push_back(MVT::Other);
1264 cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
1266 SmallVector<SDValue, 6> Ops;
1267 Ops.push_back(RegSeq);
1268 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
1269 Ops.push_back(N->getOperand(NumVecs + 2)); // Base Register
1270 Ops.push_back(N->getOperand(NumVecs + 3)); // Incremental
1271 Ops.push_back(N->getOperand(0));
1272 SDNode *St = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1274 // Transfer memoperands.
1275 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1276 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1277 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
1282 static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,
1283 unsigned &Opc, SDValue &Opd0,
1284 unsigned &LSB, unsigned &MSB,
1285 unsigned NumberOfIgnoredLowBits,
1286 bool BiggerPattern) {
1287 assert(N->getOpcode() == ISD::AND &&
1288 "N must be a AND operation to call this function");
1290 EVT VT = N->getValueType(0);
1292 // Here we can test the type of VT and return false when the type does not
1293 // match, but since it is done prior to that call in the current context
1294 // we turned that into an assert to avoid redundant code.
1295 assert((VT == MVT::i32 || VT == MVT::i64) &&
1296 "Type checking must have been done before calling this function");
1298 // FIXME: simplify-demanded-bits in DAGCombine will probably have
1299 // changed the AND node to a 32-bit mask operation. We'll have to
1300 // undo that as part of the transform here if we want to catch all
1301 // the opportunities.
1302 // Currently the NumberOfIgnoredLowBits argument helps to recover
1303 // form these situations when matching bigger pattern (bitfield insert).
1305 // For unsigned extracts, check for a shift right and mask
1306 uint64_t And_imm = 0;
1307 if (!isOpcWithIntImmediate(N, ISD::AND, And_imm))
1310 const SDNode *Op0 = N->getOperand(0).getNode();
1312 // Because of simplify-demanded-bits in DAGCombine, the mask may have been
1313 // simplified. Try to undo that
1314 And_imm |= (1 << NumberOfIgnoredLowBits) - 1;
1316 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1317 if (And_imm & (And_imm + 1))
1320 bool ClampMSB = false;
1321 uint64_t Srl_imm = 0;
1322 // Handle the SRL + ANY_EXTEND case.
1323 if (VT == MVT::i64 && Op0->getOpcode() == ISD::ANY_EXTEND &&
1324 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, Srl_imm)) {
1325 // Extend the incoming operand of the SRL to 64-bit.
1326 Opd0 = Widen(CurDAG, Op0->getOperand(0).getOperand(0));
1327 // Make sure to clamp the MSB so that we preserve the semantics of the
1328 // original operations.
1330 } else if (VT == MVT::i32 && Op0->getOpcode() == ISD::TRUNCATE &&
1331 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL,
1333 // If the shift result was truncated, we can still combine them.
1334 Opd0 = Op0->getOperand(0).getOperand(0);
1336 // Use the type of SRL node.
1337 VT = Opd0->getValueType(0);
1338 } else if (isOpcWithIntImmediate(Op0, ISD::SRL, Srl_imm)) {
1339 Opd0 = Op0->getOperand(0);
1340 } else if (BiggerPattern) {
1341 // Let's pretend a 0 shift right has been performed.
1342 // The resulting code will be at least as good as the original one
1343 // plus it may expose more opportunities for bitfield insert pattern.
1344 // FIXME: Currently we limit this to the bigger pattern, because
1345 // some optimizations expect AND and not UBFM
1346 Opd0 = N->getOperand(0);
1350 assert((BiggerPattern || (Srl_imm > 0 && Srl_imm < VT.getSizeInBits())) &&
1351 "bad amount in shift node!");
1354 MSB = Srl_imm + (VT == MVT::i32 ? CountTrailingOnes_32(And_imm)
1355 : CountTrailingOnes_64(And_imm)) -
1358 // Since we're moving the extend before the right shift operation, we need
1359 // to clamp the MSB to make sure we don't shift in undefined bits instead of
1360 // the zeros which would get shifted in with the original right shift
1362 MSB = MSB > 31 ? 31 : MSB;
1364 Opc = VT == MVT::i32 ? ARM64::UBFMWri : ARM64::UBFMXri;
1368 static bool isOneBitExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0,
1369 unsigned &LSB, unsigned &MSB) {
1370 // We are looking for the following pattern which basically extracts a single
1371 // bit from the source value and places it in the LSB of the destination
1372 // value, all other bits of the destination value or set to zero:
1374 // Value2 = AND Value, MaskImm
1375 // SRL Value2, ShiftImm
1377 // with MaskImm >> ShiftImm == 1.
1379 // This gets selected into a single UBFM:
1381 // UBFM Value, ShiftImm, ShiftImm
1384 if (N->getOpcode() != ISD::SRL)
1387 uint64_t And_mask = 0;
1388 if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, And_mask))
1391 Opd0 = N->getOperand(0).getOperand(0);
1393 uint64_t Srl_imm = 0;
1394 if (!isIntImmediate(N->getOperand(1), Srl_imm))
1397 // Check whether we really have a one bit extract here.
1398 if (And_mask >> Srl_imm == 0x1) {
1399 if (N->getValueType(0) == MVT::i32)
1400 Opc = ARM64::UBFMWri;
1402 Opc = ARM64::UBFMXri;
1404 LSB = MSB = Srl_imm;
1412 static bool isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0,
1413 unsigned &LSB, unsigned &MSB,
1414 bool BiggerPattern) {
1415 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
1416 "N must be a SHR/SRA operation to call this function");
1418 EVT VT = N->getValueType(0);
1420 // Here we can test the type of VT and return false when the type does not
1421 // match, but since it is done prior to that call in the current context
1422 // we turned that into an assert to avoid redundant code.
1423 assert((VT == MVT::i32 || VT == MVT::i64) &&
1424 "Type checking must have been done before calling this function");
1426 // Check for AND + SRL doing a one bit extract.
1427 if (isOneBitExtractOpFromShr(N, Opc, Opd0, LSB, MSB))
1430 // we're looking for a shift of a shift
1431 uint64_t Shl_imm = 0;
1432 uint64_t Trunc_bits = 0;
1433 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1434 Opd0 = N->getOperand(0).getOperand(0);
1435 } else if (VT == MVT::i32 && N->getOpcode() == ISD::SRL &&
1436 N->getOperand(0).getNode()->getOpcode() == ISD::TRUNCATE) {
1437 // We are looking for a shift of truncate. Truncate from i64 to i32 could
1438 // be considered as setting high 32 bits as zero. Our strategy here is to
1439 // always generate 64bit UBFM. This consistency will help the CSE pass
1440 // later find more redundancy.
1441 Opd0 = N->getOperand(0).getOperand(0);
1442 Trunc_bits = Opd0->getValueType(0).getSizeInBits() - VT.getSizeInBits();
1443 VT = Opd0->getValueType(0);
1444 assert(VT == MVT::i64 && "the promoted type should be i64");
1445 } else if (BiggerPattern) {
1446 // Let's pretend a 0 shift left has been performed.
1447 // FIXME: Currently we limit this to the bigger pattern case,
1448 // because some optimizations expect AND and not UBFM
1449 Opd0 = N->getOperand(0);
1453 assert(Shl_imm < VT.getSizeInBits() && "bad amount in shift node!");
1454 uint64_t Srl_imm = 0;
1455 if (!isIntImmediate(N->getOperand(1), Srl_imm))
1458 assert(Srl_imm > 0 && Srl_imm < VT.getSizeInBits() &&
1459 "bad amount in shift node!");
1460 // Note: The width operand is encoded as width-1.
1461 unsigned Width = VT.getSizeInBits() - Trunc_bits - Srl_imm - 1;
1462 int sLSB = Srl_imm - Shl_imm;
1467 // SRA requires a signed extraction
1469 Opc = N->getOpcode() == ISD::SRA ? ARM64::SBFMWri : ARM64::UBFMWri;
1471 Opc = N->getOpcode() == ISD::SRA ? ARM64::SBFMXri : ARM64::UBFMXri;
1475 static bool isBitfieldExtractOp(SelectionDAG *CurDAG, SDNode *N, unsigned &Opc,
1476 SDValue &Opd0, unsigned &LSB, unsigned &MSB,
1477 unsigned NumberOfIgnoredLowBits = 0,
1478 bool BiggerPattern = false) {
1479 if (N->getValueType(0) != MVT::i32 && N->getValueType(0) != MVT::i64)
1482 switch (N->getOpcode()) {
1484 if (!N->isMachineOpcode())
1488 return isBitfieldExtractOpFromAnd(CurDAG, N, Opc, Opd0, LSB, MSB,
1489 NumberOfIgnoredLowBits, BiggerPattern);
1492 return isBitfieldExtractOpFromShr(N, Opc, Opd0, LSB, MSB, BiggerPattern);
1495 unsigned NOpc = N->getMachineOpcode();
1499 case ARM64::SBFMWri:
1500 case ARM64::UBFMWri:
1501 case ARM64::SBFMXri:
1502 case ARM64::UBFMXri:
1504 Opd0 = N->getOperand(0);
1505 LSB = cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
1506 MSB = cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
1513 SDNode *ARM64DAGToDAGISel::SelectBitfieldExtractOp(SDNode *N) {
1514 unsigned Opc, LSB, MSB;
1516 if (!isBitfieldExtractOp(CurDAG, N, Opc, Opd0, LSB, MSB))
1519 EVT VT = N->getValueType(0);
1521 // If the bit extract operation is 64bit but the original type is 32bit, we
1522 // need to add one EXTRACT_SUBREG.
1523 if ((Opc == ARM64::SBFMXri || Opc == ARM64::UBFMXri) && VT == MVT::i32) {
1524 SDValue Ops64[] = {Opd0, CurDAG->getTargetConstant(LSB, MVT::i64),
1525 CurDAG->getTargetConstant(MSB, MVT::i64)};
1527 SDNode *BFM = CurDAG->getMachineNode(Opc, SDLoc(N), MVT::i64, Ops64);
1528 SDValue SubReg = CurDAG->getTargetConstant(ARM64::sub_32, MVT::i32);
1529 MachineSDNode *Node =
1530 CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, SDLoc(N), MVT::i32,
1531 SDValue(BFM, 0), SubReg);
1535 SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(LSB, VT),
1536 CurDAG->getTargetConstant(MSB, VT)};
1537 return CurDAG->SelectNodeTo(N, Opc, VT, Ops);
1540 /// Does DstMask form a complementary pair with the mask provided by
1541 /// BitsToBeInserted, suitable for use in a BFI instruction. Roughly speaking,
1542 /// this asks whether DstMask zeroes precisely those bits that will be set by
1544 static bool isBitfieldDstMask(uint64_t DstMask, APInt BitsToBeInserted,
1545 unsigned NumberOfIgnoredHighBits, EVT VT) {
1546 assert((VT == MVT::i32 || VT == MVT::i64) &&
1547 "i32 or i64 mask type expected!");
1548 unsigned BitWidth = VT.getSizeInBits() - NumberOfIgnoredHighBits;
1550 APInt SignificantDstMask = APInt(BitWidth, DstMask);
1551 APInt SignificantBitsToBeInserted = BitsToBeInserted.zextOrTrunc(BitWidth);
1553 return (SignificantDstMask & SignificantBitsToBeInserted) == 0 &&
1554 (SignificantDstMask | SignificantBitsToBeInserted).isAllOnesValue();
1557 // Look for bits that will be useful for later uses.
1558 // A bit is consider useless as soon as it is dropped and never used
1559 // before it as been dropped.
1560 // E.g., looking for useful bit of x
1563 // After #1, x useful bits are 0x7, then the useful bits of x, live through
1565 // After #2, the useful bits of x are 0x4.
1566 // However, if x is used on an unpredicatable instruction, then all its bits
1572 static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth = 0);
1574 static void getUsefulBitsFromAndWithImmediate(SDValue Op, APInt &UsefulBits,
1577 cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
1578 Imm = ARM64_AM::decodeLogicalImmediate(Imm, UsefulBits.getBitWidth());
1579 UsefulBits &= APInt(UsefulBits.getBitWidth(), Imm);
1580 getUsefulBits(Op, UsefulBits, Depth + 1);
1583 static void getUsefulBitsFromBitfieldMoveOpd(SDValue Op, APInt &UsefulBits,
1584 uint64_t Imm, uint64_t MSB,
1586 // inherit the bitwidth value
1587 APInt OpUsefulBits(UsefulBits);
1591 OpUsefulBits = OpUsefulBits.shl(MSB - Imm + 1);
1593 // The interesting part will be in the lower part of the result
1594 getUsefulBits(Op, OpUsefulBits, Depth + 1);
1595 // The interesting part was starting at Imm in the argument
1596 OpUsefulBits = OpUsefulBits.shl(Imm);
1598 OpUsefulBits = OpUsefulBits.shl(MSB + 1);
1600 // The interesting part will be shifted in the result
1601 OpUsefulBits = OpUsefulBits.shl(OpUsefulBits.getBitWidth() - Imm);
1602 getUsefulBits(Op, OpUsefulBits, Depth + 1);
1603 // The interesting part was at zero in the argument
1604 OpUsefulBits = OpUsefulBits.lshr(OpUsefulBits.getBitWidth() - Imm);
1607 UsefulBits &= OpUsefulBits;
1610 static void getUsefulBitsFromUBFM(SDValue Op, APInt &UsefulBits,
1613 cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
1615 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1617 getUsefulBitsFromBitfieldMoveOpd(Op, UsefulBits, Imm, MSB, Depth);
1620 static void getUsefulBitsFromOrWithShiftedReg(SDValue Op, APInt &UsefulBits,
1622 uint64_t ShiftTypeAndValue =
1623 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1624 APInt Mask(UsefulBits);
1625 Mask.clearAllBits();
1628 if (ARM64_AM::getShiftType(ShiftTypeAndValue) == ARM64_AM::LSL) {
1630 uint64_t ShiftAmt = ARM64_AM::getShiftValue(ShiftTypeAndValue);
1631 Mask = Mask.shl(ShiftAmt);
1632 getUsefulBits(Op, Mask, Depth + 1);
1633 Mask = Mask.lshr(ShiftAmt);
1634 } else if (ARM64_AM::getShiftType(ShiftTypeAndValue) == ARM64_AM::LSR) {
1636 // We do not handle ARM64_AM::ASR, because the sign will change the
1637 // number of useful bits
1638 uint64_t ShiftAmt = ARM64_AM::getShiftValue(ShiftTypeAndValue);
1639 Mask = Mask.lshr(ShiftAmt);
1640 getUsefulBits(Op, Mask, Depth + 1);
1641 Mask = Mask.shl(ShiftAmt);
1648 static void getUsefulBitsFromBFM(SDValue Op, SDValue Orig, APInt &UsefulBits,
1651 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1653 cast<const ConstantSDNode>(Op.getOperand(3).getNode())->getZExtValue();
1655 if (Op.getOperand(1) == Orig)
1656 return getUsefulBitsFromBitfieldMoveOpd(Op, UsefulBits, Imm, MSB, Depth);
1658 APInt OpUsefulBits(UsefulBits);
1662 OpUsefulBits = OpUsefulBits.shl(MSB - Imm + 1);
1664 UsefulBits &= ~OpUsefulBits;
1665 getUsefulBits(Op, UsefulBits, Depth + 1);
1667 OpUsefulBits = OpUsefulBits.shl(MSB + 1);
1669 UsefulBits = ~(OpUsefulBits.shl(OpUsefulBits.getBitWidth() - Imm));
1670 getUsefulBits(Op, UsefulBits, Depth + 1);
1674 static void getUsefulBitsForUse(SDNode *UserNode, APInt &UsefulBits,
1675 SDValue Orig, unsigned Depth) {
1677 // Users of this node should have already been instruction selected
1678 // FIXME: Can we turn that into an assert?
1679 if (!UserNode->isMachineOpcode())
1682 switch (UserNode->getMachineOpcode()) {
1685 case ARM64::ANDSWri:
1686 case ARM64::ANDSXri:
1689 // We increment Depth only when we call the getUsefulBits
1690 return getUsefulBitsFromAndWithImmediate(SDValue(UserNode, 0), UsefulBits,
1692 case ARM64::UBFMWri:
1693 case ARM64::UBFMXri:
1694 return getUsefulBitsFromUBFM(SDValue(UserNode, 0), UsefulBits, Depth);
1698 if (UserNode->getOperand(1) != Orig)
1700 return getUsefulBitsFromOrWithShiftedReg(SDValue(UserNode, 0), UsefulBits,
1704 return getUsefulBitsFromBFM(SDValue(UserNode, 0), Orig, UsefulBits, Depth);
1708 static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth) {
1711 // Initialize UsefulBits
1713 unsigned Bitwidth = Op.getValueType().getScalarType().getSizeInBits();
1714 // At the beginning, assume every produced bits is useful
1715 UsefulBits = APInt(Bitwidth, 0);
1716 UsefulBits.flipAllBits();
1718 APInt UsersUsefulBits(UsefulBits.getBitWidth(), 0);
1720 for (SDNode *Node : Op.getNode()->uses()) {
1721 // A use cannot produce useful bits
1722 APInt UsefulBitsForUse = APInt(UsefulBits);
1723 getUsefulBitsForUse(Node, UsefulBitsForUse, Op, Depth);
1724 UsersUsefulBits |= UsefulBitsForUse;
1726 // UsefulBits contains the produced bits that are meaningful for the
1727 // current definition, thus a user cannot make a bit meaningful at
1729 UsefulBits &= UsersUsefulBits;
1732 /// Create a machine node performing a notional SHL of Op by ShlAmount. If
1733 /// ShlAmount is negative, do a (logical) right-shift instead. If ShlAmount is
1734 /// 0, return Op unchanged.
1735 static SDValue getLeftShift(SelectionDAG *CurDAG, SDValue Op, int ShlAmount) {
1739 EVT VT = Op.getValueType();
1740 unsigned BitWidth = VT.getSizeInBits();
1741 unsigned UBFMOpc = BitWidth == 32 ? ARM64::UBFMWri : ARM64::UBFMXri;
1744 if (ShlAmount > 0) {
1745 // LSL wD, wN, #Amt == UBFM wD, wN, #32-Amt, #31-Amt
1746 ShiftNode = CurDAG->getMachineNode(
1747 UBFMOpc, SDLoc(Op), VT, Op,
1748 CurDAG->getTargetConstant(BitWidth - ShlAmount, VT),
1749 CurDAG->getTargetConstant(BitWidth - 1 - ShlAmount, VT));
1751 // LSR wD, wN, #Amt == UBFM wD, wN, #Amt, #32-1
1752 assert(ShlAmount < 0 && "expected right shift");
1753 int ShrAmount = -ShlAmount;
1754 ShiftNode = CurDAG->getMachineNode(
1755 UBFMOpc, SDLoc(Op), VT, Op, CurDAG->getTargetConstant(ShrAmount, VT),
1756 CurDAG->getTargetConstant(BitWidth - 1, VT));
1759 return SDValue(ShiftNode, 0);
1762 /// Does this tree qualify as an attempt to move a bitfield into position,
1763 /// essentially "(and (shl VAL, N), Mask)".
1764 static bool isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op,
1765 SDValue &Src, int &ShiftAmount,
1767 EVT VT = Op.getValueType();
1768 unsigned BitWidth = VT.getSizeInBits();
1770 assert(BitWidth == 32 || BitWidth == 64);
1772 APInt KnownZero, KnownOne;
1773 CurDAG->computeKnownBits(Op, KnownZero, KnownOne);
1775 // Non-zero in the sense that they're not provably zero, which is the key
1776 // point if we want to use this value
1777 uint64_t NonZeroBits = (~KnownZero).getZExtValue();
1779 // Discard a constant AND mask if present. It's safe because the node will
1780 // already have been factored into the computeKnownBits calculation above.
1782 if (isOpcWithIntImmediate(Op.getNode(), ISD::AND, AndImm)) {
1783 assert((~APInt(BitWidth, AndImm) & ~KnownZero) == 0);
1784 Op = Op.getOperand(0);
1788 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SHL, ShlImm))
1790 Op = Op.getOperand(0);
1792 if (!isShiftedMask_64(NonZeroBits))
1795 ShiftAmount = countTrailingZeros(NonZeroBits);
1796 MaskWidth = CountTrailingOnes_64(NonZeroBits >> ShiftAmount);
1798 // BFI encompasses sufficiently many nodes that it's worth inserting an extra
1799 // LSL/LSR if the mask in NonZeroBits doesn't quite match up with the ISD::SHL
1801 Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount);
1806 // Given a OR operation, check if we have the following pattern
1807 // ubfm c, b, imm, imm2 (or something that does the same jobs, see
1808 // isBitfieldExtractOp)
1809 // d = e & mask2 ; where mask is a binary sequence of 1..10..0 and
1810 // countTrailingZeros(mask2) == imm2 - imm + 1
1812 // if yes, given reference arguments will be update so that one can replace
1813 // the OR instruction with:
1814 // f = Opc Opd0, Opd1, LSB, MSB ; where Opc is a BFM, LSB = imm, and MSB = imm2
1815 static bool isBitfieldInsertOpFromOr(SDNode *N, unsigned &Opc, SDValue &Dst,
1816 SDValue &Src, unsigned &ImmR,
1817 unsigned &ImmS, SelectionDAG *CurDAG) {
1818 assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
1821 EVT VT = N->getValueType(0);
1823 Opc = ARM64::BFMWri;
1824 else if (VT == MVT::i64)
1825 Opc = ARM64::BFMXri;
1829 // Because of simplify-demanded-bits in DAGCombine, involved masks may not
1830 // have the expected shape. Try to undo that.
1832 getUsefulBits(SDValue(N, 0), UsefulBits);
1834 unsigned NumberOfIgnoredLowBits = UsefulBits.countTrailingZeros();
1835 unsigned NumberOfIgnoredHighBits = UsefulBits.countLeadingZeros();
1837 // OR is commutative, check both possibilities (does llvm provide a
1838 // way to do that directely, e.g., via code matcher?)
1839 SDValue OrOpd1Val = N->getOperand(1);
1840 SDNode *OrOpd0 = N->getOperand(0).getNode();
1841 SDNode *OrOpd1 = N->getOperand(1).getNode();
1842 for (int i = 0; i < 2;
1843 ++i, std::swap(OrOpd0, OrOpd1), OrOpd1Val = N->getOperand(0)) {
1846 if (isBitfieldExtractOp(CurDAG, OrOpd0, BFXOpc, Src, ImmR, ImmS,
1847 NumberOfIgnoredLowBits, true)) {
1848 // Check that the returned opcode is compatible with the pattern,
1849 // i.e., same type and zero extended (U and not S)
1850 if ((BFXOpc != ARM64::UBFMXri && VT == MVT::i64) ||
1851 (BFXOpc != ARM64::UBFMWri && VT == MVT::i32))
1854 // Compute the width of the bitfield insertion
1856 Width = ImmS - ImmR + 1;
1857 // FIXME: This constraint is to catch bitfield insertion we may
1858 // want to widen the pattern if we want to grab general bitfied
1863 // If the mask on the insertee is correct, we have a BFXIL operation. We
1864 // can share the ImmR and ImmS values from the already-computed UBFM.
1865 } else if (isBitfieldPositioningOp(CurDAG, SDValue(OrOpd0, 0), Src,
1867 ImmR = (VT.getSizeInBits() - DstLSB) % VT.getSizeInBits();
1872 // Check the second part of the pattern
1873 EVT VT = OrOpd1->getValueType(0);
1874 assert((VT == MVT::i32 || VT == MVT::i64) && "unexpected OR operand");
1876 // Compute the Known Zero for the candidate of the first operand.
1877 // This allows to catch more general case than just looking for
1878 // AND with imm. Indeed, simplify-demanded-bits may have removed
1879 // the AND instruction because it proves it was useless.
1880 APInt KnownZero, KnownOne;
1881 CurDAG->computeKnownBits(OrOpd1Val, KnownZero, KnownOne);
1883 // Check if there is enough room for the second operand to appear
1885 APInt BitsToBeInserted =
1886 APInt::getBitsSet(KnownZero.getBitWidth(), DstLSB, DstLSB + Width);
1888 if ((BitsToBeInserted & ~KnownZero) != 0)
1891 // Set the first operand
1893 if (isOpcWithIntImmediate(OrOpd1, ISD::AND, Imm) &&
1894 isBitfieldDstMask(Imm, BitsToBeInserted, NumberOfIgnoredHighBits, VT))
1895 // In that case, we can eliminate the AND
1896 Dst = OrOpd1->getOperand(0);
1898 // Maybe the AND has been removed by simplify-demanded-bits
1899 // or is useful because it discards more bits
1909 SDNode *ARM64DAGToDAGISel::SelectBitfieldInsertOp(SDNode *N) {
1910 if (N->getOpcode() != ISD::OR)
1917 if (!isBitfieldInsertOpFromOr(N, Opc, Opd0, Opd1, LSB, MSB, CurDAG))
1920 EVT VT = N->getValueType(0);
1921 SDValue Ops[] = { Opd0,
1923 CurDAG->getTargetConstant(LSB, VT),
1924 CurDAG->getTargetConstant(MSB, VT) };
1925 return CurDAG->SelectNodeTo(N, Opc, VT, Ops);
1928 SDNode *ARM64DAGToDAGISel::SelectLIBM(SDNode *N) {
1929 EVT VT = N->getValueType(0);
1932 unsigned FRINTXOpcs[] = { ARM64::FRINTXSr, ARM64::FRINTXDr };
1934 if (VT == MVT::f32) {
1936 } else if (VT == MVT::f64) {
1939 return nullptr; // Unrecognized argument type. Fall back on default codegen.
1941 // Pick the FRINTX variant needed to set the flags.
1942 unsigned FRINTXOpc = FRINTXOpcs[Variant];
1944 switch (N->getOpcode()) {
1946 return nullptr; // Unrecognized libm ISD node. Fall back on default codegen.
1948 unsigned FRINTPOpcs[] = { ARM64::FRINTPSr, ARM64::FRINTPDr };
1949 Opc = FRINTPOpcs[Variant];
1953 unsigned FRINTMOpcs[] = { ARM64::FRINTMSr, ARM64::FRINTMDr };
1954 Opc = FRINTMOpcs[Variant];
1958 unsigned FRINTZOpcs[] = { ARM64::FRINTZSr, ARM64::FRINTZDr };
1959 Opc = FRINTZOpcs[Variant];
1963 unsigned FRINTAOpcs[] = { ARM64::FRINTASr, ARM64::FRINTADr };
1964 Opc = FRINTAOpcs[Variant];
1970 SDValue In = N->getOperand(0);
1971 SmallVector<SDValue, 2> Ops;
1974 if (!TM.Options.UnsafeFPMath) {
1975 SDNode *FRINTX = CurDAG->getMachineNode(FRINTXOpc, dl, VT, MVT::Glue, In);
1976 Ops.push_back(SDValue(FRINTX, 1));
1979 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
1983 ARM64DAGToDAGISel::SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos,
1984 unsigned RegWidth) {
1986 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
1987 FVal = CN->getValueAPF();
1988 else if (LoadSDNode *LN = dyn_cast<LoadSDNode>(N)) {
1989 // Some otherwise illegal constants are allowed in this case.
1990 if (LN->getOperand(1).getOpcode() != ARM64ISD::ADDlow ||
1991 !isa<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1)))
1994 ConstantPoolSDNode *CN =
1995 dyn_cast<ConstantPoolSDNode>(LN->getOperand(1)->getOperand(1));
1996 FVal = cast<ConstantFP>(CN->getConstVal())->getValueAPF();
2000 // An FCVT[SU] instruction performs: convertToInt(Val * 2^fbits) where fbits
2001 // is between 1 and 32 for a destination w-register, or 1 and 64 for an
2004 // By this stage, we've detected (fp_to_[su]int (fmul Val, THIS_NODE)) so we
2005 // want THIS_NODE to be 2^fbits. This is much easier to deal with using
2009 // fbits is between 1 and 64 in the worst-case, which means the fmul
2010 // could have 2^64 as an actual operand. Need 65 bits of precision.
2011 APSInt IntVal(65, true);
2012 FVal.convertToInteger(IntVal, APFloat::rmTowardZero, &IsExact);
2014 // N.b. isPowerOf2 also checks for > 0.
2015 if (!IsExact || !IntVal.isPowerOf2()) return false;
2016 unsigned FBits = IntVal.logBase2();
2018 // Checks above should have guaranteed that we haven't lost information in
2019 // finding FBits, but it must still be in range.
2020 if (FBits == 0 || FBits > RegWidth) return false;
2022 FixedPos = CurDAG->getTargetConstant(FBits, MVT::i32);
2026 SDNode *ARM64DAGToDAGISel::Select(SDNode *Node) {
2027 // Dump information about the Node being selected
2028 DEBUG(errs() << "Selecting: ");
2029 DEBUG(Node->dump(CurDAG));
2030 DEBUG(errs() << "\n");
2032 // If we have a custom node, we already have selected!
2033 if (Node->isMachineOpcode()) {
2034 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
2035 Node->setNodeId(-1);
2039 // Few custom selection stuff.
2040 SDNode *ResNode = nullptr;
2041 EVT VT = Node->getValueType(0);
2043 switch (Node->getOpcode()) {
2048 if (SDNode *I = SelectMLAV64LaneV128(Node))
2053 // Try to select as an indexed load. Fall through to normal processing
2056 SDNode *I = SelectIndexedLoad(Node, Done);
2065 if (SDNode *I = SelectBitfieldExtractOp(Node))
2070 if (SDNode *I = SelectBitfieldInsertOp(Node))
2074 case ISD::EXTRACT_VECTOR_ELT: {
2075 // Extracting lane zero is a special case where we can just use a plain
2076 // EXTRACT_SUBREG instruction, which will become FMOV. This is easier for
2077 // the rest of the compiler, especially the register allocator and copyi
2078 // propagation, to reason about, so is preferred when it's possible to
2080 ConstantSDNode *LaneNode = cast<ConstantSDNode>(Node->getOperand(1));
2081 // Bail and use the default Select() for non-zero lanes.
2082 if (LaneNode->getZExtValue() != 0)
2084 // If the element type is not the same as the result type, likewise
2085 // bail and use the default Select(), as there's more to do than just
2086 // a cross-class COPY. This catches extracts of i8 and i16 elements
2087 // since they will need an explicit zext.
2088 if (VT != Node->getOperand(0).getValueType().getVectorElementType())
2091 switch (Node->getOperand(0)
2093 .getVectorElementType()
2096 assert(0 && "Unexpected vector element type!");
2098 SubReg = ARM64::dsub;
2101 SubReg = ARM64::ssub;
2103 case 16: // FALLTHROUGH
2105 llvm_unreachable("unexpected zext-requiring extract element!");
2107 SDValue Extract = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(Node), VT,
2108 Node->getOperand(0));
2109 DEBUG(dbgs() << "ISEL: Custom selection!\n=> ");
2110 DEBUG(Extract->dumpr(CurDAG));
2111 DEBUG(dbgs() << "\n");
2112 return Extract.getNode();
2114 case ISD::Constant: {
2115 // Materialize zero constants as copies from WZR/XZR. This allows
2116 // the coalescer to propagate these into other instructions.
2117 ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);
2118 if (ConstNode->isNullValue()) {
2120 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),
2121 ARM64::WZR, MVT::i32).getNode();
2122 else if (VT == MVT::i64)
2123 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),
2124 ARM64::XZR, MVT::i64).getNode();
2129 case ISD::FrameIndex: {
2130 // Selects to ADDXri FI, 0 which in turn will become ADDXri SP, imm.
2131 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
2132 unsigned Shifter = ARM64_AM::getShifterImm(ARM64_AM::LSL, 0);
2133 const TargetLowering *TLI = getTargetLowering();
2134 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
2135 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2136 CurDAG->getTargetConstant(Shifter, MVT::i32) };
2137 return CurDAG->SelectNodeTo(Node, ARM64::ADDXri, MVT::i64, Ops);
2139 case ISD::INTRINSIC_W_CHAIN: {
2140 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2144 case Intrinsic::arm64_ldaxp:
2145 case Intrinsic::arm64_ldxp: {
2147 IntNo == Intrinsic::arm64_ldaxp ? ARM64::LDAXPX : ARM64::LDXPX;
2148 SDValue MemAddr = Node->getOperand(2);
2150 SDValue Chain = Node->getOperand(0);
2152 SDNode *Ld = CurDAG->getMachineNode(Op, DL, MVT::i64, MVT::i64,
2153 MVT::Other, MemAddr, Chain);
2155 // Transfer memoperands.
2156 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2157 MemOp[0] = cast<MemIntrinsicSDNode>(Node)->getMemOperand();
2158 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
2161 case Intrinsic::arm64_stlxp:
2162 case Intrinsic::arm64_stxp: {
2164 IntNo == Intrinsic::arm64_stlxp ? ARM64::STLXPX : ARM64::STXPX;
2166 SDValue Chain = Node->getOperand(0);
2167 SDValue ValLo = Node->getOperand(2);
2168 SDValue ValHi = Node->getOperand(3);
2169 SDValue MemAddr = Node->getOperand(4);
2171 // Place arguments in the right order.
2172 SmallVector<SDValue, 7> Ops;
2173 Ops.push_back(ValLo);
2174 Ops.push_back(ValHi);
2175 Ops.push_back(MemAddr);
2176 Ops.push_back(Chain);
2178 SDNode *St = CurDAG->getMachineNode(Op, DL, MVT::i32, MVT::Other, Ops);
2179 // Transfer memoperands.
2180 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2181 MemOp[0] = cast<MemIntrinsicSDNode>(Node)->getMemOperand();
2182 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
2186 case Intrinsic::arm64_neon_ld1x2:
2187 if (VT == MVT::v8i8)
2188 return SelectLoad(Node, 2, ARM64::LD1Twov8b, ARM64::dsub0);
2189 else if (VT == MVT::v16i8)
2190 return SelectLoad(Node, 2, ARM64::LD1Twov16b, ARM64::qsub0);
2191 else if (VT == MVT::v4i16)
2192 return SelectLoad(Node, 2, ARM64::LD1Twov4h, ARM64::dsub0);
2193 else if (VT == MVT::v8i16)
2194 return SelectLoad(Node, 2, ARM64::LD1Twov8h, ARM64::qsub0);
2195 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2196 return SelectLoad(Node, 2, ARM64::LD1Twov2s, ARM64::dsub0);
2197 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2198 return SelectLoad(Node, 2, ARM64::LD1Twov4s, ARM64::qsub0);
2199 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2200 return SelectLoad(Node, 2, ARM64::LD1Twov1d, ARM64::dsub0);
2201 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2202 return SelectLoad(Node, 2, ARM64::LD1Twov2d, ARM64::qsub0);
2204 case Intrinsic::arm64_neon_ld1x3:
2205 if (VT == MVT::v8i8)
2206 return SelectLoad(Node, 3, ARM64::LD1Threev8b, ARM64::dsub0);
2207 else if (VT == MVT::v16i8)
2208 return SelectLoad(Node, 3, ARM64::LD1Threev16b, ARM64::qsub0);
2209 else if (VT == MVT::v4i16)
2210 return SelectLoad(Node, 3, ARM64::LD1Threev4h, ARM64::dsub0);
2211 else if (VT == MVT::v8i16)
2212 return SelectLoad(Node, 3, ARM64::LD1Threev8h, ARM64::qsub0);
2213 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2214 return SelectLoad(Node, 3, ARM64::LD1Threev2s, ARM64::dsub0);
2215 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2216 return SelectLoad(Node, 3, ARM64::LD1Threev4s, ARM64::qsub0);
2217 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2218 return SelectLoad(Node, 3, ARM64::LD1Threev1d, ARM64::dsub0);
2219 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2220 return SelectLoad(Node, 3, ARM64::LD1Threev2d, ARM64::qsub0);
2222 case Intrinsic::arm64_neon_ld1x4:
2223 if (VT == MVT::v8i8)
2224 return SelectLoad(Node, 4, ARM64::LD1Fourv8b, ARM64::dsub0);
2225 else if (VT == MVT::v16i8)
2226 return SelectLoad(Node, 4, ARM64::LD1Fourv16b, ARM64::qsub0);
2227 else if (VT == MVT::v4i16)
2228 return SelectLoad(Node, 4, ARM64::LD1Fourv4h, ARM64::dsub0);
2229 else if (VT == MVT::v8i16)
2230 return SelectLoad(Node, 4, ARM64::LD1Fourv8h, ARM64::qsub0);
2231 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2232 return SelectLoad(Node, 4, ARM64::LD1Fourv2s, ARM64::dsub0);
2233 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2234 return SelectLoad(Node, 4, ARM64::LD1Fourv4s, ARM64::qsub0);
2235 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2236 return SelectLoad(Node, 4, ARM64::LD1Fourv1d, ARM64::dsub0);
2237 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2238 return SelectLoad(Node, 4, ARM64::LD1Fourv2d, ARM64::qsub0);
2240 case Intrinsic::arm64_neon_ld2:
2241 if (VT == MVT::v8i8)
2242 return SelectLoad(Node, 2, ARM64::LD2Twov8b, ARM64::dsub0);
2243 else if (VT == MVT::v16i8)
2244 return SelectLoad(Node, 2, ARM64::LD2Twov16b, ARM64::qsub0);
2245 else if (VT == MVT::v4i16)
2246 return SelectLoad(Node, 2, ARM64::LD2Twov4h, ARM64::dsub0);
2247 else if (VT == MVT::v8i16)
2248 return SelectLoad(Node, 2, ARM64::LD2Twov8h, ARM64::qsub0);
2249 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2250 return SelectLoad(Node, 2, ARM64::LD2Twov2s, ARM64::dsub0);
2251 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2252 return SelectLoad(Node, 2, ARM64::LD2Twov4s, ARM64::qsub0);
2253 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2254 return SelectLoad(Node, 2, ARM64::LD1Twov1d, ARM64::dsub0);
2255 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2256 return SelectLoad(Node, 2, ARM64::LD2Twov2d, ARM64::qsub0);
2258 case Intrinsic::arm64_neon_ld3:
2259 if (VT == MVT::v8i8)
2260 return SelectLoad(Node, 3, ARM64::LD3Threev8b, ARM64::dsub0);
2261 else if (VT == MVT::v16i8)
2262 return SelectLoad(Node, 3, ARM64::LD3Threev16b, ARM64::qsub0);
2263 else if (VT == MVT::v4i16)
2264 return SelectLoad(Node, 3, ARM64::LD3Threev4h, ARM64::dsub0);
2265 else if (VT == MVT::v8i16)
2266 return SelectLoad(Node, 3, ARM64::LD3Threev8h, ARM64::qsub0);
2267 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2268 return SelectLoad(Node, 3, ARM64::LD3Threev2s, ARM64::dsub0);
2269 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2270 return SelectLoad(Node, 3, ARM64::LD3Threev4s, ARM64::qsub0);
2271 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2272 return SelectLoad(Node, 3, ARM64::LD1Threev1d, ARM64::dsub0);
2273 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2274 return SelectLoad(Node, 3, ARM64::LD3Threev2d, ARM64::qsub0);
2276 case Intrinsic::arm64_neon_ld4:
2277 if (VT == MVT::v8i8)
2278 return SelectLoad(Node, 4, ARM64::LD4Fourv8b, ARM64::dsub0);
2279 else if (VT == MVT::v16i8)
2280 return SelectLoad(Node, 4, ARM64::LD4Fourv16b, ARM64::qsub0);
2281 else if (VT == MVT::v4i16)
2282 return SelectLoad(Node, 4, ARM64::LD4Fourv4h, ARM64::dsub0);
2283 else if (VT == MVT::v8i16)
2284 return SelectLoad(Node, 4, ARM64::LD4Fourv8h, ARM64::qsub0);
2285 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2286 return SelectLoad(Node, 4, ARM64::LD4Fourv2s, ARM64::dsub0);
2287 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2288 return SelectLoad(Node, 4, ARM64::LD4Fourv4s, ARM64::qsub0);
2289 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2290 return SelectLoad(Node, 4, ARM64::LD1Fourv1d, ARM64::dsub0);
2291 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2292 return SelectLoad(Node, 4, ARM64::LD4Fourv2d, ARM64::qsub0);
2294 case Intrinsic::arm64_neon_ld2r:
2295 if (VT == MVT::v8i8)
2296 return SelectLoad(Node, 2, ARM64::LD2Rv8b, ARM64::dsub0);
2297 else if (VT == MVT::v16i8)
2298 return SelectLoad(Node, 2, ARM64::LD2Rv16b, ARM64::qsub0);
2299 else if (VT == MVT::v4i16)
2300 return SelectLoad(Node, 2, ARM64::LD2Rv4h, ARM64::dsub0);
2301 else if (VT == MVT::v8i16)
2302 return SelectLoad(Node, 2, ARM64::LD2Rv8h, ARM64::qsub0);
2303 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2304 return SelectLoad(Node, 2, ARM64::LD2Rv2s, ARM64::dsub0);
2305 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2306 return SelectLoad(Node, 2, ARM64::LD2Rv4s, ARM64::qsub0);
2307 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2308 return SelectLoad(Node, 2, ARM64::LD2Rv1d, ARM64::dsub0);
2309 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2310 return SelectLoad(Node, 2, ARM64::LD2Rv2d, ARM64::qsub0);
2312 case Intrinsic::arm64_neon_ld3r:
2313 if (VT == MVT::v8i8)
2314 return SelectLoad(Node, 3, ARM64::LD3Rv8b, ARM64::dsub0);
2315 else if (VT == MVT::v16i8)
2316 return SelectLoad(Node, 3, ARM64::LD3Rv16b, ARM64::qsub0);
2317 else if (VT == MVT::v4i16)
2318 return SelectLoad(Node, 3, ARM64::LD3Rv4h, ARM64::dsub0);
2319 else if (VT == MVT::v8i16)
2320 return SelectLoad(Node, 3, ARM64::LD3Rv8h, ARM64::qsub0);
2321 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2322 return SelectLoad(Node, 3, ARM64::LD3Rv2s, ARM64::dsub0);
2323 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2324 return SelectLoad(Node, 3, ARM64::LD3Rv4s, ARM64::qsub0);
2325 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2326 return SelectLoad(Node, 3, ARM64::LD3Rv1d, ARM64::dsub0);
2327 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2328 return SelectLoad(Node, 3, ARM64::LD3Rv2d, ARM64::qsub0);
2330 case Intrinsic::arm64_neon_ld4r:
2331 if (VT == MVT::v8i8)
2332 return SelectLoad(Node, 4, ARM64::LD4Rv8b, ARM64::dsub0);
2333 else if (VT == MVT::v16i8)
2334 return SelectLoad(Node, 4, ARM64::LD4Rv16b, ARM64::qsub0);
2335 else if (VT == MVT::v4i16)
2336 return SelectLoad(Node, 4, ARM64::LD4Rv4h, ARM64::dsub0);
2337 else if (VT == MVT::v8i16)
2338 return SelectLoad(Node, 4, ARM64::LD4Rv8h, ARM64::qsub0);
2339 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2340 return SelectLoad(Node, 4, ARM64::LD4Rv2s, ARM64::dsub0);
2341 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2342 return SelectLoad(Node, 4, ARM64::LD4Rv4s, ARM64::qsub0);
2343 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2344 return SelectLoad(Node, 4, ARM64::LD4Rv1d, ARM64::dsub0);
2345 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2346 return SelectLoad(Node, 4, ARM64::LD4Rv2d, ARM64::qsub0);
2348 case Intrinsic::arm64_neon_ld2lane:
2349 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2350 return SelectLoadLane(Node, 2, ARM64::LD2i8);
2351 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2352 return SelectLoadLane(Node, 2, ARM64::LD2i16);
2353 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2355 return SelectLoadLane(Node, 2, ARM64::LD2i32);
2356 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2358 return SelectLoadLane(Node, 2, ARM64::LD2i64);
2360 case Intrinsic::arm64_neon_ld3lane:
2361 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2362 return SelectLoadLane(Node, 3, ARM64::LD3i8);
2363 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2364 return SelectLoadLane(Node, 3, ARM64::LD3i16);
2365 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2367 return SelectLoadLane(Node, 3, ARM64::LD3i32);
2368 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2370 return SelectLoadLane(Node, 3, ARM64::LD3i64);
2372 case Intrinsic::arm64_neon_ld4lane:
2373 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2374 return SelectLoadLane(Node, 4, ARM64::LD4i8);
2375 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2376 return SelectLoadLane(Node, 4, ARM64::LD4i16);
2377 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2379 return SelectLoadLane(Node, 4, ARM64::LD4i32);
2380 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2382 return SelectLoadLane(Node, 4, ARM64::LD4i64);
2386 case ISD::INTRINSIC_WO_CHAIN: {
2387 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
2391 case Intrinsic::arm64_neon_tbl2:
2392 return SelectTable(Node, 2, VT == MVT::v8i8 ? ARM64::TBLv8i8Two
2393 : ARM64::TBLv16i8Two,
2395 case Intrinsic::arm64_neon_tbl3:
2396 return SelectTable(Node, 3, VT == MVT::v8i8 ? ARM64::TBLv8i8Three
2397 : ARM64::TBLv16i8Three,
2399 case Intrinsic::arm64_neon_tbl4:
2400 return SelectTable(Node, 4, VT == MVT::v8i8 ? ARM64::TBLv8i8Four
2401 : ARM64::TBLv16i8Four,
2403 case Intrinsic::arm64_neon_tbx2:
2404 return SelectTable(Node, 2, VT == MVT::v8i8 ? ARM64::TBXv8i8Two
2405 : ARM64::TBXv16i8Two,
2407 case Intrinsic::arm64_neon_tbx3:
2408 return SelectTable(Node, 3, VT == MVT::v8i8 ? ARM64::TBXv8i8Three
2409 : ARM64::TBXv16i8Three,
2411 case Intrinsic::arm64_neon_tbx4:
2412 return SelectTable(Node, 4, VT == MVT::v8i8 ? ARM64::TBXv8i8Four
2413 : ARM64::TBXv16i8Four,
2415 case Intrinsic::arm64_neon_smull:
2416 case Intrinsic::arm64_neon_umull:
2417 if (SDNode *N = SelectMULLV64LaneV128(IntNo, Node))
2423 case ISD::INTRINSIC_VOID: {
2424 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2425 if (Node->getNumOperands() >= 3)
2426 VT = Node->getOperand(2)->getValueType(0);
2430 case Intrinsic::arm64_neon_st1x2: {
2431 if (VT == MVT::v8i8)
2432 return SelectStore(Node, 2, ARM64::ST1Twov8b);
2433 else if (VT == MVT::v16i8)
2434 return SelectStore(Node, 2, ARM64::ST1Twov16b);
2435 else if (VT == MVT::v4i16)
2436 return SelectStore(Node, 2, ARM64::ST1Twov4h);
2437 else if (VT == MVT::v8i16)
2438 return SelectStore(Node, 2, ARM64::ST1Twov8h);
2439 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2440 return SelectStore(Node, 2, ARM64::ST1Twov2s);
2441 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2442 return SelectStore(Node, 2, ARM64::ST1Twov4s);
2443 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2444 return SelectStore(Node, 2, ARM64::ST1Twov2d);
2445 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2446 return SelectStore(Node, 2, ARM64::ST1Twov1d);
2449 case Intrinsic::arm64_neon_st1x3: {
2450 if (VT == MVT::v8i8)
2451 return SelectStore(Node, 3, ARM64::ST1Threev8b);
2452 else if (VT == MVT::v16i8)
2453 return SelectStore(Node, 3, ARM64::ST1Threev16b);
2454 else if (VT == MVT::v4i16)
2455 return SelectStore(Node, 3, ARM64::ST1Threev4h);
2456 else if (VT == MVT::v8i16)
2457 return SelectStore(Node, 3, ARM64::ST1Threev8h);
2458 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2459 return SelectStore(Node, 3, ARM64::ST1Threev2s);
2460 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2461 return SelectStore(Node, 3, ARM64::ST1Threev4s);
2462 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2463 return SelectStore(Node, 3, ARM64::ST1Threev2d);
2464 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2465 return SelectStore(Node, 3, ARM64::ST1Threev1d);
2468 case Intrinsic::arm64_neon_st1x4: {
2469 if (VT == MVT::v8i8)
2470 return SelectStore(Node, 4, ARM64::ST1Fourv8b);
2471 else if (VT == MVT::v16i8)
2472 return SelectStore(Node, 4, ARM64::ST1Fourv16b);
2473 else if (VT == MVT::v4i16)
2474 return SelectStore(Node, 4, ARM64::ST1Fourv4h);
2475 else if (VT == MVT::v8i16)
2476 return SelectStore(Node, 4, ARM64::ST1Fourv8h);
2477 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2478 return SelectStore(Node, 4, ARM64::ST1Fourv2s);
2479 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2480 return SelectStore(Node, 4, ARM64::ST1Fourv4s);
2481 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2482 return SelectStore(Node, 4, ARM64::ST1Fourv2d);
2483 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2484 return SelectStore(Node, 4, ARM64::ST1Fourv1d);
2487 case Intrinsic::arm64_neon_st2: {
2488 if (VT == MVT::v8i8)
2489 return SelectStore(Node, 2, ARM64::ST2Twov8b);
2490 else if (VT == MVT::v16i8)
2491 return SelectStore(Node, 2, ARM64::ST2Twov16b);
2492 else if (VT == MVT::v4i16)
2493 return SelectStore(Node, 2, ARM64::ST2Twov4h);
2494 else if (VT == MVT::v8i16)
2495 return SelectStore(Node, 2, ARM64::ST2Twov8h);
2496 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2497 return SelectStore(Node, 2, ARM64::ST2Twov2s);
2498 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2499 return SelectStore(Node, 2, ARM64::ST2Twov4s);
2500 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2501 return SelectStore(Node, 2, ARM64::ST2Twov2d);
2502 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2503 return SelectStore(Node, 2, ARM64::ST1Twov1d);
2506 case Intrinsic::arm64_neon_st3: {
2507 if (VT == MVT::v8i8)
2508 return SelectStore(Node, 3, ARM64::ST3Threev8b);
2509 else if (VT == MVT::v16i8)
2510 return SelectStore(Node, 3, ARM64::ST3Threev16b);
2511 else if (VT == MVT::v4i16)
2512 return SelectStore(Node, 3, ARM64::ST3Threev4h);
2513 else if (VT == MVT::v8i16)
2514 return SelectStore(Node, 3, ARM64::ST3Threev8h);
2515 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2516 return SelectStore(Node, 3, ARM64::ST3Threev2s);
2517 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2518 return SelectStore(Node, 3, ARM64::ST3Threev4s);
2519 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2520 return SelectStore(Node, 3, ARM64::ST3Threev2d);
2521 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2522 return SelectStore(Node, 3, ARM64::ST1Threev1d);
2525 case Intrinsic::arm64_neon_st4: {
2526 if (VT == MVT::v8i8)
2527 return SelectStore(Node, 4, ARM64::ST4Fourv8b);
2528 else if (VT == MVT::v16i8)
2529 return SelectStore(Node, 4, ARM64::ST4Fourv16b);
2530 else if (VT == MVT::v4i16)
2531 return SelectStore(Node, 4, ARM64::ST4Fourv4h);
2532 else if (VT == MVT::v8i16)
2533 return SelectStore(Node, 4, ARM64::ST4Fourv8h);
2534 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2535 return SelectStore(Node, 4, ARM64::ST4Fourv2s);
2536 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2537 return SelectStore(Node, 4, ARM64::ST4Fourv4s);
2538 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2539 return SelectStore(Node, 4, ARM64::ST4Fourv2d);
2540 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2541 return SelectStore(Node, 4, ARM64::ST1Fourv1d);
2544 case Intrinsic::arm64_neon_st2lane: {
2545 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2546 return SelectStoreLane(Node, 2, ARM64::ST2i8);
2547 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2548 return SelectStoreLane(Node, 2, ARM64::ST2i16);
2549 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2551 return SelectStoreLane(Node, 2, ARM64::ST2i32);
2552 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2554 return SelectStoreLane(Node, 2, ARM64::ST2i64);
2557 case Intrinsic::arm64_neon_st3lane: {
2558 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2559 return SelectStoreLane(Node, 3, ARM64::ST3i8);
2560 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2561 return SelectStoreLane(Node, 3, ARM64::ST3i16);
2562 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2564 return SelectStoreLane(Node, 3, ARM64::ST3i32);
2565 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2567 return SelectStoreLane(Node, 3, ARM64::ST3i64);
2570 case Intrinsic::arm64_neon_st4lane: {
2571 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2572 return SelectStoreLane(Node, 4, ARM64::ST4i8);
2573 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2574 return SelectStoreLane(Node, 4, ARM64::ST4i16);
2575 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2577 return SelectStoreLane(Node, 4, ARM64::ST4i32);
2578 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2580 return SelectStoreLane(Node, 4, ARM64::ST4i64);
2585 case ARM64ISD::LD2post: {
2586 if (VT == MVT::v8i8)
2587 return SelectPostLoad(Node, 2, ARM64::LD2Twov8b_POST, ARM64::dsub0);
2588 else if (VT == MVT::v16i8)
2589 return SelectPostLoad(Node, 2, ARM64::LD2Twov16b_POST, ARM64::qsub0);
2590 else if (VT == MVT::v4i16)
2591 return SelectPostLoad(Node, 2, ARM64::LD2Twov4h_POST, ARM64::dsub0);
2592 else if (VT == MVT::v8i16)
2593 return SelectPostLoad(Node, 2, ARM64::LD2Twov8h_POST, ARM64::qsub0);
2594 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2595 return SelectPostLoad(Node, 2, ARM64::LD2Twov2s_POST, ARM64::dsub0);
2596 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2597 return SelectPostLoad(Node, 2, ARM64::LD2Twov4s_POST, ARM64::qsub0);
2598 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2599 return SelectPostLoad(Node, 2, ARM64::LD1Twov1d_POST, ARM64::dsub0);
2600 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2601 return SelectPostLoad(Node, 2, ARM64::LD2Twov2d_POST, ARM64::qsub0);
2604 case ARM64ISD::LD3post: {
2605 if (VT == MVT::v8i8)
2606 return SelectPostLoad(Node, 3, ARM64::LD3Threev8b_POST, ARM64::dsub0);
2607 else if (VT == MVT::v16i8)
2608 return SelectPostLoad(Node, 3, ARM64::LD3Threev16b_POST, ARM64::qsub0);
2609 else if (VT == MVT::v4i16)
2610 return SelectPostLoad(Node, 3, ARM64::LD3Threev4h_POST, ARM64::dsub0);
2611 else if (VT == MVT::v8i16)
2612 return SelectPostLoad(Node, 3, ARM64::LD3Threev8h_POST, ARM64::qsub0);
2613 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2614 return SelectPostLoad(Node, 3, ARM64::LD3Threev2s_POST, ARM64::dsub0);
2615 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2616 return SelectPostLoad(Node, 3, ARM64::LD3Threev4s_POST, ARM64::qsub0);
2617 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2618 return SelectPostLoad(Node, 3, ARM64::LD1Threev1d_POST, ARM64::dsub0);
2619 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2620 return SelectPostLoad(Node, 3, ARM64::LD3Threev2d_POST, ARM64::qsub0);
2623 case ARM64ISD::LD4post: {
2624 if (VT == MVT::v8i8)
2625 return SelectPostLoad(Node, 4, ARM64::LD4Fourv8b_POST, ARM64::dsub0);
2626 else if (VT == MVT::v16i8)
2627 return SelectPostLoad(Node, 4, ARM64::LD4Fourv16b_POST, ARM64::qsub0);
2628 else if (VT == MVT::v4i16)
2629 return SelectPostLoad(Node, 4, ARM64::LD4Fourv4h_POST, ARM64::dsub0);
2630 else if (VT == MVT::v8i16)
2631 return SelectPostLoad(Node, 4, ARM64::LD4Fourv8h_POST, ARM64::qsub0);
2632 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2633 return SelectPostLoad(Node, 4, ARM64::LD4Fourv2s_POST, ARM64::dsub0);
2634 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2635 return SelectPostLoad(Node, 4, ARM64::LD4Fourv4s_POST, ARM64::qsub0);
2636 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2637 return SelectPostLoad(Node, 4, ARM64::LD1Fourv1d_POST, ARM64::dsub0);
2638 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2639 return SelectPostLoad(Node, 4, ARM64::LD4Fourv2d_POST, ARM64::qsub0);
2642 case ARM64ISD::LD1x2post: {
2643 if (VT == MVT::v8i8)
2644 return SelectPostLoad(Node, 2, ARM64::LD1Twov8b_POST, ARM64::dsub0);
2645 else if (VT == MVT::v16i8)
2646 return SelectPostLoad(Node, 2, ARM64::LD1Twov16b_POST, ARM64::qsub0);
2647 else if (VT == MVT::v4i16)
2648 return SelectPostLoad(Node, 2, ARM64::LD1Twov4h_POST, ARM64::dsub0);
2649 else if (VT == MVT::v8i16)
2650 return SelectPostLoad(Node, 2, ARM64::LD1Twov8h_POST, ARM64::qsub0);
2651 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2652 return SelectPostLoad(Node, 2, ARM64::LD1Twov2s_POST, ARM64::dsub0);
2653 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2654 return SelectPostLoad(Node, 2, ARM64::LD1Twov4s_POST, ARM64::qsub0);
2655 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2656 return SelectPostLoad(Node, 2, ARM64::LD1Twov1d_POST, ARM64::dsub0);
2657 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2658 return SelectPostLoad(Node, 2, ARM64::LD1Twov2d_POST, ARM64::qsub0);
2661 case ARM64ISD::LD1x3post: {
2662 if (VT == MVT::v8i8)
2663 return SelectPostLoad(Node, 3, ARM64::LD1Threev8b_POST, ARM64::dsub0);
2664 else if (VT == MVT::v16i8)
2665 return SelectPostLoad(Node, 3, ARM64::LD1Threev16b_POST, ARM64::qsub0);
2666 else if (VT == MVT::v4i16)
2667 return SelectPostLoad(Node, 3, ARM64::LD1Threev4h_POST, ARM64::dsub0);
2668 else if (VT == MVT::v8i16)
2669 return SelectPostLoad(Node, 3, ARM64::LD1Threev8h_POST, ARM64::qsub0);
2670 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2671 return SelectPostLoad(Node, 3, ARM64::LD1Threev2s_POST, ARM64::dsub0);
2672 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2673 return SelectPostLoad(Node, 3, ARM64::LD1Threev4s_POST, ARM64::qsub0);
2674 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2675 return SelectPostLoad(Node, 3, ARM64::LD1Threev1d_POST, ARM64::dsub0);
2676 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2677 return SelectPostLoad(Node, 3, ARM64::LD1Threev2d_POST, ARM64::qsub0);
2680 case ARM64ISD::LD1x4post: {
2681 if (VT == MVT::v8i8)
2682 return SelectPostLoad(Node, 4, ARM64::LD1Fourv8b_POST, ARM64::dsub0);
2683 else if (VT == MVT::v16i8)
2684 return SelectPostLoad(Node, 4, ARM64::LD1Fourv16b_POST, ARM64::qsub0);
2685 else if (VT == MVT::v4i16)
2686 return SelectPostLoad(Node, 4, ARM64::LD1Fourv4h_POST, ARM64::dsub0);
2687 else if (VT == MVT::v8i16)
2688 return SelectPostLoad(Node, 4, ARM64::LD1Fourv8h_POST, ARM64::qsub0);
2689 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2690 return SelectPostLoad(Node, 4, ARM64::LD1Fourv2s_POST, ARM64::dsub0);
2691 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2692 return SelectPostLoad(Node, 4, ARM64::LD1Fourv4s_POST, ARM64::qsub0);
2693 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2694 return SelectPostLoad(Node, 4, ARM64::LD1Fourv1d_POST, ARM64::dsub0);
2695 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2696 return SelectPostLoad(Node, 4, ARM64::LD1Fourv2d_POST, ARM64::qsub0);
2699 case ARM64ISD::LD1DUPpost: {
2700 if (VT == MVT::v8i8)
2701 return SelectPostLoad(Node, 1, ARM64::LD1Rv8b_POST, ARM64::dsub0);
2702 else if (VT == MVT::v16i8)
2703 return SelectPostLoad(Node, 1, ARM64::LD1Rv16b_POST, ARM64::qsub0);
2704 else if (VT == MVT::v4i16)
2705 return SelectPostLoad(Node, 1, ARM64::LD1Rv4h_POST, ARM64::dsub0);
2706 else if (VT == MVT::v8i16)
2707 return SelectPostLoad(Node, 1, ARM64::LD1Rv8h_POST, ARM64::qsub0);
2708 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2709 return SelectPostLoad(Node, 1, ARM64::LD1Rv2s_POST, ARM64::dsub0);
2710 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2711 return SelectPostLoad(Node, 1, ARM64::LD1Rv4s_POST, ARM64::qsub0);
2712 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2713 return SelectPostLoad(Node, 1, ARM64::LD1Rv1d_POST, ARM64::dsub0);
2714 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2715 return SelectPostLoad(Node, 1, ARM64::LD1Rv2d_POST, ARM64::qsub0);
2718 case ARM64ISD::LD2DUPpost: {
2719 if (VT == MVT::v8i8)
2720 return SelectPostLoad(Node, 2, ARM64::LD2Rv8b_POST, ARM64::dsub0);
2721 else if (VT == MVT::v16i8)
2722 return SelectPostLoad(Node, 2, ARM64::LD2Rv16b_POST, ARM64::qsub0);
2723 else if (VT == MVT::v4i16)
2724 return SelectPostLoad(Node, 2, ARM64::LD2Rv4h_POST, ARM64::dsub0);
2725 else if (VT == MVT::v8i16)
2726 return SelectPostLoad(Node, 2, ARM64::LD2Rv8h_POST, ARM64::qsub0);
2727 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2728 return SelectPostLoad(Node, 2, ARM64::LD2Rv2s_POST, ARM64::dsub0);
2729 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2730 return SelectPostLoad(Node, 2, ARM64::LD2Rv4s_POST, ARM64::qsub0);
2731 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2732 return SelectPostLoad(Node, 2, ARM64::LD2Rv1d_POST, ARM64::dsub0);
2733 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2734 return SelectPostLoad(Node, 2, ARM64::LD2Rv2d_POST, ARM64::qsub0);
2737 case ARM64ISD::LD3DUPpost: {
2738 if (VT == MVT::v8i8)
2739 return SelectPostLoad(Node, 3, ARM64::LD3Rv8b_POST, ARM64::dsub0);
2740 else if (VT == MVT::v16i8)
2741 return SelectPostLoad(Node, 3, ARM64::LD3Rv16b_POST, ARM64::qsub0);
2742 else if (VT == MVT::v4i16)
2743 return SelectPostLoad(Node, 3, ARM64::LD3Rv4h_POST, ARM64::dsub0);
2744 else if (VT == MVT::v8i16)
2745 return SelectPostLoad(Node, 3, ARM64::LD3Rv8h_POST, ARM64::qsub0);
2746 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2747 return SelectPostLoad(Node, 3, ARM64::LD3Rv2s_POST, ARM64::dsub0);
2748 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2749 return SelectPostLoad(Node, 3, ARM64::LD3Rv4s_POST, ARM64::qsub0);
2750 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2751 return SelectPostLoad(Node, 3, ARM64::LD3Rv1d_POST, ARM64::dsub0);
2752 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2753 return SelectPostLoad(Node, 3, ARM64::LD3Rv2d_POST, ARM64::qsub0);
2756 case ARM64ISD::LD4DUPpost: {
2757 if (VT == MVT::v8i8)
2758 return SelectPostLoad(Node, 4, ARM64::LD4Rv8b_POST, ARM64::dsub0);
2759 else if (VT == MVT::v16i8)
2760 return SelectPostLoad(Node, 4, ARM64::LD4Rv16b_POST, ARM64::qsub0);
2761 else if (VT == MVT::v4i16)
2762 return SelectPostLoad(Node, 4, ARM64::LD4Rv4h_POST, ARM64::dsub0);
2763 else if (VT == MVT::v8i16)
2764 return SelectPostLoad(Node, 4, ARM64::LD4Rv8h_POST, ARM64::qsub0);
2765 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2766 return SelectPostLoad(Node, 4, ARM64::LD4Rv2s_POST, ARM64::dsub0);
2767 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2768 return SelectPostLoad(Node, 4, ARM64::LD4Rv4s_POST, ARM64::qsub0);
2769 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2770 return SelectPostLoad(Node, 4, ARM64::LD4Rv1d_POST, ARM64::dsub0);
2771 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2772 return SelectPostLoad(Node, 4, ARM64::LD4Rv2d_POST, ARM64::qsub0);
2775 case ARM64ISD::LD1LANEpost: {
2776 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2777 return SelectPostLoadLane(Node, 1, ARM64::LD1i8_POST);
2778 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2779 return SelectPostLoadLane(Node, 1, ARM64::LD1i16_POST);
2780 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2782 return SelectPostLoadLane(Node, 1, ARM64::LD1i32_POST);
2783 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2785 return SelectPostLoadLane(Node, 1, ARM64::LD1i64_POST);
2788 case ARM64ISD::LD2LANEpost: {
2789 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2790 return SelectPostLoadLane(Node, 2, ARM64::LD2i8_POST);
2791 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2792 return SelectPostLoadLane(Node, 2, ARM64::LD2i16_POST);
2793 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2795 return SelectPostLoadLane(Node, 2, ARM64::LD2i32_POST);
2796 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2798 return SelectPostLoadLane(Node, 2, ARM64::LD2i64_POST);
2801 case ARM64ISD::LD3LANEpost: {
2802 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2803 return SelectPostLoadLane(Node, 3, ARM64::LD3i8_POST);
2804 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2805 return SelectPostLoadLane(Node, 3, ARM64::LD3i16_POST);
2806 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2808 return SelectPostLoadLane(Node, 3, ARM64::LD3i32_POST);
2809 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2811 return SelectPostLoadLane(Node, 3, ARM64::LD3i64_POST);
2814 case ARM64ISD::LD4LANEpost: {
2815 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2816 return SelectPostLoadLane(Node, 4, ARM64::LD4i8_POST);
2817 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2818 return SelectPostLoadLane(Node, 4, ARM64::LD4i16_POST);
2819 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2821 return SelectPostLoadLane(Node, 4, ARM64::LD4i32_POST);
2822 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2824 return SelectPostLoadLane(Node, 4, ARM64::LD4i64_POST);
2827 case ARM64ISD::ST2post: {
2828 VT = Node->getOperand(1).getValueType();
2829 if (VT == MVT::v8i8)
2830 return SelectPostStore(Node, 2, ARM64::ST2Twov8b_POST);
2831 else if (VT == MVT::v16i8)
2832 return SelectPostStore(Node, 2, ARM64::ST2Twov16b_POST);
2833 else if (VT == MVT::v4i16)
2834 return SelectPostStore(Node, 2, ARM64::ST2Twov4h_POST);
2835 else if (VT == MVT::v8i16)
2836 return SelectPostStore(Node, 2, ARM64::ST2Twov8h_POST);
2837 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2838 return SelectPostStore(Node, 2, ARM64::ST2Twov2s_POST);
2839 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2840 return SelectPostStore(Node, 2, ARM64::ST2Twov4s_POST);
2841 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2842 return SelectPostStore(Node, 2, ARM64::ST2Twov2d_POST);
2843 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2844 return SelectPostStore(Node, 2, ARM64::ST1Twov1d_POST);
2847 case ARM64ISD::ST3post: {
2848 VT = Node->getOperand(1).getValueType();
2849 if (VT == MVT::v8i8)
2850 return SelectPostStore(Node, 3, ARM64::ST3Threev8b_POST);
2851 else if (VT == MVT::v16i8)
2852 return SelectPostStore(Node, 3, ARM64::ST3Threev16b_POST);
2853 else if (VT == MVT::v4i16)
2854 return SelectPostStore(Node, 3, ARM64::ST3Threev4h_POST);
2855 else if (VT == MVT::v8i16)
2856 return SelectPostStore(Node, 3, ARM64::ST3Threev8h_POST);
2857 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2858 return SelectPostStore(Node, 3, ARM64::ST3Threev2s_POST);
2859 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2860 return SelectPostStore(Node, 3, ARM64::ST3Threev4s_POST);
2861 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2862 return SelectPostStore(Node, 3, ARM64::ST3Threev2d_POST);
2863 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2864 return SelectPostStore(Node, 3, ARM64::ST1Threev1d_POST);
2867 case ARM64ISD::ST4post: {
2868 VT = Node->getOperand(1).getValueType();
2869 if (VT == MVT::v8i8)
2870 return SelectPostStore(Node, 4, ARM64::ST4Fourv8b_POST);
2871 else if (VT == MVT::v16i8)
2872 return SelectPostStore(Node, 4, ARM64::ST4Fourv16b_POST);
2873 else if (VT == MVT::v4i16)
2874 return SelectPostStore(Node, 4, ARM64::ST4Fourv4h_POST);
2875 else if (VT == MVT::v8i16)
2876 return SelectPostStore(Node, 4, ARM64::ST4Fourv8h_POST);
2877 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2878 return SelectPostStore(Node, 4, ARM64::ST4Fourv2s_POST);
2879 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2880 return SelectPostStore(Node, 4, ARM64::ST4Fourv4s_POST);
2881 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2882 return SelectPostStore(Node, 4, ARM64::ST4Fourv2d_POST);
2883 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2884 return SelectPostStore(Node, 4, ARM64::ST1Fourv1d_POST);
2887 case ARM64ISD::ST1x2post: {
2888 VT = Node->getOperand(1).getValueType();
2889 if (VT == MVT::v8i8)
2890 return SelectPostStore(Node, 2, ARM64::ST1Twov8b_POST);
2891 else if (VT == MVT::v16i8)
2892 return SelectPostStore(Node, 2, ARM64::ST1Twov16b_POST);
2893 else if (VT == MVT::v4i16)
2894 return SelectPostStore(Node, 2, ARM64::ST1Twov4h_POST);
2895 else if (VT == MVT::v8i16)
2896 return SelectPostStore(Node, 2, ARM64::ST1Twov8h_POST);
2897 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2898 return SelectPostStore(Node, 2, ARM64::ST1Twov2s_POST);
2899 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2900 return SelectPostStore(Node, 2, ARM64::ST1Twov4s_POST);
2901 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2902 return SelectPostStore(Node, 2, ARM64::ST1Twov1d_POST);
2903 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2904 return SelectPostStore(Node, 2, ARM64::ST1Twov2d_POST);
2907 case ARM64ISD::ST1x3post: {
2908 VT = Node->getOperand(1).getValueType();
2909 if (VT == MVT::v8i8)
2910 return SelectPostStore(Node, 3, ARM64::ST1Threev8b_POST);
2911 else if (VT == MVT::v16i8)
2912 return SelectPostStore(Node, 3, ARM64::ST1Threev16b_POST);
2913 else if (VT == MVT::v4i16)
2914 return SelectPostStore(Node, 3, ARM64::ST1Threev4h_POST);
2915 else if (VT == MVT::v8i16)
2916 return SelectPostStore(Node, 3, ARM64::ST1Threev8h_POST);
2917 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2918 return SelectPostStore(Node, 3, ARM64::ST1Threev2s_POST);
2919 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2920 return SelectPostStore(Node, 3, ARM64::ST1Threev4s_POST);
2921 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2922 return SelectPostStore(Node, 3, ARM64::ST1Threev1d_POST);
2923 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2924 return SelectPostStore(Node, 3, ARM64::ST1Threev2d_POST);
2927 case ARM64ISD::ST1x4post: {
2928 VT = Node->getOperand(1).getValueType();
2929 if (VT == MVT::v8i8)
2930 return SelectPostStore(Node, 4, ARM64::ST1Fourv8b_POST);
2931 else if (VT == MVT::v16i8)
2932 return SelectPostStore(Node, 4, ARM64::ST1Fourv16b_POST);
2933 else if (VT == MVT::v4i16)
2934 return SelectPostStore(Node, 4, ARM64::ST1Fourv4h_POST);
2935 else if (VT == MVT::v8i16)
2936 return SelectPostStore(Node, 4, ARM64::ST1Fourv8h_POST);
2937 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2938 return SelectPostStore(Node, 4, ARM64::ST1Fourv2s_POST);
2939 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2940 return SelectPostStore(Node, 4, ARM64::ST1Fourv4s_POST);
2941 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2942 return SelectPostStore(Node, 4, ARM64::ST1Fourv1d_POST);
2943 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2944 return SelectPostStore(Node, 4, ARM64::ST1Fourv2d_POST);
2947 case ARM64ISD::ST2LANEpost: {
2948 VT = Node->getOperand(1).getValueType();
2949 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2950 return SelectPostStoreLane(Node, 2, ARM64::ST2i8_POST);
2951 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2952 return SelectPostStoreLane(Node, 2, ARM64::ST2i16_POST);
2953 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2955 return SelectPostStoreLane(Node, 2, ARM64::ST2i32_POST);
2956 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2958 return SelectPostStoreLane(Node, 2, ARM64::ST2i64_POST);
2961 case ARM64ISD::ST3LANEpost: {
2962 VT = Node->getOperand(1).getValueType();
2963 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2964 return SelectPostStoreLane(Node, 3, ARM64::ST3i8_POST);
2965 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2966 return SelectPostStoreLane(Node, 3, ARM64::ST3i16_POST);
2967 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2969 return SelectPostStoreLane(Node, 3, ARM64::ST3i32_POST);
2970 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2972 return SelectPostStoreLane(Node, 3, ARM64::ST3i64_POST);
2975 case ARM64ISD::ST4LANEpost: {
2976 VT = Node->getOperand(1).getValueType();
2977 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2978 return SelectPostStoreLane(Node, 4, ARM64::ST4i8_POST);
2979 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2980 return SelectPostStoreLane(Node, 4, ARM64::ST4i16_POST);
2981 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2983 return SelectPostStoreLane(Node, 4, ARM64::ST4i32_POST);
2984 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2986 return SelectPostStoreLane(Node, 4, ARM64::ST4i64_POST);
2994 if (SDNode *I = SelectLIBM(Node))
2999 // Select the default instruction
3000 ResNode = SelectCode(Node);
3002 DEBUG(errs() << "=> ");
3003 if (ResNode == nullptr || ResNode == Node)
3004 DEBUG(Node->dump(CurDAG));
3006 DEBUG(ResNode->dump(CurDAG));
3007 DEBUG(errs() << "\n");
3012 /// createARM64ISelDag - This pass converts a legalized DAG into a
3013 /// ARM64-specific DAG, ready for instruction scheduling.
3014 FunctionPass *llvm::createARM64ISelDag(ARM64TargetMachine &TM,
3015 CodeGenOpt::Level OptLevel) {
3016 return new ARM64DAGToDAGISel(TM, OptLevel);