1 //===-- ARM64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // When allowed by the instruction, replace a dead definition of a GPR with
10 // the zero register. This makes the code a bit friendlier towards the
11 // hardware's register renamer.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm64-dead-defs"
16 #include "ARM64RegisterInfo.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
25 STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
28 class ARM64DeadRegisterDefinitions : public MachineFunctionPass {
30 const TargetRegisterInfo *TRI;
31 bool implicitlyDefinesSubReg(unsigned Reg, const MachineInstr &MI);
32 bool processMachineBasicBlock(MachineBasicBlock &MBB);
33 bool usesFrameIndex(const MachineInstr &MI);
35 static char ID; // Pass identification, replacement for typeid.
36 explicit ARM64DeadRegisterDefinitions() : MachineFunctionPass(ID) {}
38 virtual bool runOnMachineFunction(MachineFunction &F);
40 const char *getPassName() const { return "Dead register definitions"; }
42 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
44 MachineFunctionPass::getAnalysisUsage(AU);
47 char ARM64DeadRegisterDefinitions::ID = 0;
48 } // end anonymous namespace
51 ARM64DeadRegisterDefinitions::implicitlyDefinesSubReg(unsigned Reg,
52 const MachineInstr &MI) {
53 for (const MachineOperand &MO : MI.implicit_operands())
54 if (MO.isReg() && MO.isDef())
55 if (TRI->isSubRegister(Reg, MO.getReg()))
60 bool ARM64DeadRegisterDefinitions::usesFrameIndex(const MachineInstr &MI) {
61 for (const MachineOperand &Op : MI.uses())
68 ARM64DeadRegisterDefinitions::processMachineBasicBlock(MachineBasicBlock &MBB) {
70 for (MachineInstr &MI : MBB) {
71 if (usesFrameIndex(MI)) {
72 // We need to skip this instruction because while it appears to have a
73 // dead def it uses a frame index which might expand into a multi
74 // instruction sequence during EPI.
75 DEBUG(dbgs() << " Ignoring, operand is frame index\n");
78 for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) {
79 MachineOperand &MO = MI.getOperand(i);
80 if (MO.isReg() && MO.isDead() && MO.isDef()) {
81 assert(!MO.isImplicit() && "Unexpected implicit def!");
82 DEBUG(dbgs() << " Dead def operand #" << i << " in:\n ";
84 // Be careful not to change the register if it's a tied operand.
85 if (MI.isRegTiedToUseOperand(i)) {
86 DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
89 // Don't change the register if there's an implicit def of a subreg.
90 if (implicitlyDefinesSubReg(MO.getReg(), MI)) {
91 DEBUG(dbgs() << " Ignoring, implicitly defines subregister.\n");
94 // Make sure the instruction take a register class that contains
95 // the zero register and replace it if so.
97 switch (MI.getDesc().OpInfo[i].RegClass) {
99 DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
101 case ARM64::GPR32RegClassID:
104 case ARM64::GPR64RegClassID:
108 DEBUG(dbgs() << " Replacing with zero register. New:\n ");
110 DEBUG(MI.print(dbgs()));
111 ++NumDeadDefsReplaced;
118 // Scan the function for instructions that have a dead definition of a
119 // register. Replace that register with the zero register when possible.
120 bool ARM64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
121 TRI = MF.getTarget().getRegisterInfo();
122 bool Changed = false;
123 DEBUG(dbgs() << "***** ARM64DeadRegisterDefinitions *****\n");
126 if (processMachineBasicBlock(MBB))
131 FunctionPass *llvm::createARM64DeadRegisterDefinitions() {
132 return new ARM64DeadRegisterDefinitions();