1 //===-- Thumb2SizeReduction.cpp - Thumb2 code size reduction pass -*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "t2-reduce-size"
12 #include "ARMAddressingModes.h"
13 #include "ARMBaseRegisterInfo.h"
14 #include "ARMBaseInstrInfo.h"
15 #include "ARMSubtarget.h"
16 #include "Thumb2InstrInfo.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/Statistic.h"
27 STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones");
28 STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones");
29 STATISTIC(NumLdSts, "Number of 32-bit load / store reduced to 16-bit ones");
31 static cl::opt<int> ReduceLimit("t2-reduce-limit",
32 cl::init(-1), cl::Hidden);
33 static cl::opt<int> ReduceLimit2Addr("t2-reduce-limit2",
34 cl::init(-1), cl::Hidden);
35 static cl::opt<int> ReduceLimitLdSt("t2-reduce-limit3",
36 cl::init(-1), cl::Hidden);
39 /// ReduceTable - A static table with information on mapping from wide
42 unsigned WideOpc; // Wide opcode
43 unsigned NarrowOpc1; // Narrow opcode to transform to
44 unsigned NarrowOpc2; // Narrow opcode when it's two-address
45 uint8_t Imm1Limit; // Limit of immediate field (bits)
46 uint8_t Imm2Limit; // Limit of immediate field when it's two-address
47 unsigned LowRegs1 : 1; // Only possible if low-registers are used
48 unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr)
49 unsigned PredCC1 : 2; // 0 - If predicated, cc is on and vice versa.
51 // 2 - Always set CPSR.
53 unsigned PartFlag : 1; // 16-bit instruction does partial flag update
54 unsigned Special : 1; // Needs to be dealt with specially
57 static const ReduceEntry ReduceTable[] = {
58 // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C, PF, S
59 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0 },
60 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1 },
61 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0 },
62 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1 },
63 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1 },
64 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0 },
65 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0 },
66 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0 },
67 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0 },
68 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
69 //{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0,0 },
70 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0 },
71 { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0,1 },
72 { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 1,0 },
73 // FIXME: adr.n immediate offset must be multiple of 4.
74 //{ ARM::t2LEApcrelJT,ARM::tLEApcrelJT, 0, 0, 0, 1, 0, 1,0, 0,0 },
75 { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 1,0 },
76 { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 1,0 },
77 { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 1,0 },
78 { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 1,0 },
79 // FIXME: tMOVi8 and tMVN also partially update CPSR but they are less
80 // likely to cause issue in the loop. As a size / performance workaround,
81 // they are not marked as such.
82 { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0,0 },
83 { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0,1 },
84 // FIXME: Do we need the 16-bit 'S' variant?
85 { ARM::t2MOVr,ARM::tMOVr, 0, 0, 0, 0, 0, 1,0, 0,0 },
86 { ARM::t2MOVCCr,0, ARM::tMOVCCr, 0, 0, 0, 0, 0,1, 0,0 },
87 { ARM::t2MOVCCi,0, ARM::tMOVCCi, 0, 8, 0, 1, 0,1, 0,0 },
88 { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 1,0 },
89 { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0,0 },
90 { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 1,0 },
91 { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0,0 },
92 { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0,0 },
93 { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0,0 },
94 { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 1,0 },
95 { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 0,1 },
96 { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 0,1 },
97 { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0,0 },
98 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0 },
99 { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0,0 },
100 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0 },
101 { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0,0 },
102 { ARM::t2SXTBr, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,0 },
103 { ARM::t2SXTHr, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,0 },
104 { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0,0 },
105 { ARM::t2UXTBr, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,0 },
106 { ARM::t2UXTHr, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,0 },
108 // FIXME: Clean this up after splitting each Thumb load / store opcode
109 // into multiple ones.
110 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1 },
111 { ARM::t2LDRs, ARM::tLDRr, 0, 0, 0, 1, 0, 0,0, 0,1 },
112 { ARM::t2LDRBi12,ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 0,1 },
113 { ARM::t2LDRBs, ARM::tLDRBr, 0, 0, 0, 1, 0, 0,0, 0,1 },
114 { ARM::t2LDRHi12,ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 0,1 },
115 { ARM::t2LDRHs, ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1 },
116 { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 0,1 },
117 { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 0,1 },
118 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1 },
119 { ARM::t2STRs, ARM::tSTRr, 0, 0, 0, 1, 0, 0,0, 0,1 },
120 { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 0,1 },
121 { ARM::t2STRBs, ARM::tSTRBr, 0, 0, 0, 1, 0, 0,0, 0,1 },
122 { ARM::t2STRHi12,ARM::tSTRHi, 0, 5, 0, 1, 0, 0,0, 0,1 },
123 { ARM::t2STRHs, ARM::tSTRHr, 0, 0, 0, 1, 0, 0,0, 0,1 },
125 { ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 0,1 },
126 { ARM::t2LDMIA_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 0,1 },
127 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1 },
128 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent
129 { ARM::t2STMIA_UPD,ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1 },
130 { ARM::t2STMDB_UPD, 0, ARM::tPUSH, 0, 0, 1, 1, 1,1, 0,1 },
133 class Thumb2SizeReduce : public MachineFunctionPass {
138 const Thumb2InstrInfo *TII;
139 const ARMSubtarget *STI;
141 virtual bool runOnMachineFunction(MachineFunction &MF);
143 virtual const char *getPassName() const {
144 return "Thumb2 instruction size reduction pass";
148 /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
149 DenseMap<unsigned, unsigned> ReduceOpcodeMap;
151 bool canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use);
153 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
154 bool is2Addr, ARMCC::CondCodes Pred,
155 bool LiveCPSR, bool &HasCC, bool &CCDead);
157 bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
158 const ReduceEntry &Entry);
160 bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
161 const ReduceEntry &Entry, bool LiveCPSR,
162 MachineInstr *CPSRDef);
164 /// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
166 bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
167 const ReduceEntry &Entry,
168 bool LiveCPSR, MachineInstr *CPSRDef);
170 /// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit
171 /// non-two-address instruction.
172 bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
173 const ReduceEntry &Entry,
174 bool LiveCPSR, MachineInstr *CPSRDef);
176 /// ReduceMBB - Reduce width of instructions in the specified basic block.
177 bool ReduceMBB(MachineBasicBlock &MBB);
179 char Thumb2SizeReduce::ID = 0;
182 Thumb2SizeReduce::Thumb2SizeReduce() : MachineFunctionPass(ID) {
183 for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) {
184 unsigned FromOpc = ReduceTable[i].WideOpc;
185 if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
186 assert(false && "Duplicated entries?");
190 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) {
191 for (const unsigned *Regs = MCID.ImplicitDefs; *Regs; ++Regs)
192 if (*Regs == ARM::CPSR)
197 /// canAddPseudoFlagDep - For A9 (and other out-of-order) implementations,
198 /// the 's' 16-bit instruction partially update CPSR. Abort the
199 /// transformation to avoid adding false dependency on last CPSR setting
200 /// instruction which hurts the ability for out-of-order execution engine
201 /// to do register renaming magic.
202 /// This function checks if there is a read-of-write dependency between the
203 /// last instruction that defines the CPSR and the current instruction. If there
204 /// is, then there is no harm done since the instruction cannot be retired
205 /// before the CPSR setting instruction anyway.
206 /// Note, we are not doing full dependency analysis here for the sake of compile
207 /// time. We're not looking for cases like:
209 /// r1 = add.w r0, ...
212 /// In this case it would have been ok to narrow the mul.w to muls since there
213 /// are indirect RAW dependency between the muls and the mul.w
215 Thumb2SizeReduce::canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use) {
216 if (!Def || !STI->avoidCPSRPartialUpdate())
219 SmallSet<unsigned, 2> Defs;
220 for (unsigned i = 0, e = Def->getNumOperands(); i != e; ++i) {
221 const MachineOperand &MO = Def->getOperand(i);
222 if (!MO.isReg() || MO.isUndef() || MO.isUse())
224 unsigned Reg = MO.getReg();
225 if (Reg == 0 || Reg == ARM::CPSR)
230 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
231 const MachineOperand &MO = Use->getOperand(i);
232 if (!MO.isReg() || MO.isUndef() || MO.isDef())
234 unsigned Reg = MO.getReg();
239 // No read-after-write dependency. The narrowing will add false dependency.
244 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
245 bool is2Addr, ARMCC::CondCodes Pred,
246 bool LiveCPSR, bool &HasCC, bool &CCDead) {
247 if ((is2Addr && Entry.PredCC2 == 0) ||
248 (!is2Addr && Entry.PredCC1 == 0)) {
249 if (Pred == ARMCC::AL) {
250 // Not predicated, must set CPSR.
252 // Original instruction was not setting CPSR, but CPSR is not
253 // currently live anyway. It's ok to set it. The CPSR def is
263 // Predicated, must not set CPSR.
267 } else if ((is2Addr && Entry.PredCC2 == 2) ||
268 (!is2Addr && Entry.PredCC1 == 2)) {
269 /// Old opcode has an optional def of CPSR.
272 // If old opcode does not implicitly define CPSR, then it's not ok since
273 // these new opcodes' CPSR def is not meant to be thrown away. e.g. CMP.
274 if (!HasImplicitCPSRDef(MI->getDesc()))
278 // 16-bit instruction does not set CPSR.
286 static bool VerifyLowRegs(MachineInstr *MI) {
287 unsigned Opc = MI->getOpcode();
288 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA ||
289 Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD ||
290 Opc == ARM::t2LDMDB_UPD);
291 bool isLROk = (Opc == ARM::t2STMIA_UPD || Opc == ARM::t2STMDB_UPD);
292 bool isSPOk = isPCOk || isLROk;
293 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
294 const MachineOperand &MO = MI->getOperand(i);
295 if (!MO.isReg() || MO.isImplicit())
297 unsigned Reg = MO.getReg();
298 if (Reg == 0 || Reg == ARM::CPSR)
300 if (isPCOk && Reg == ARM::PC)
302 if (isLROk && Reg == ARM::LR)
304 if (Reg == ARM::SP) {
307 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12))
308 // Special case for these ldr / str with sp as base register.
311 if (!isARMLowRegister(Reg))
318 Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
319 const ReduceEntry &Entry) {
320 if (ReduceLimitLdSt != -1 && ((int)NumLdSts >= ReduceLimitLdSt))
324 bool HasImmOffset = false;
325 bool HasShift = false;
326 bool HasOffReg = true;
327 bool isLdStMul = false;
328 unsigned Opc = Entry.NarrowOpc1;
329 unsigned OpNum = 3; // First 'rest' of operands.
330 uint8_t ImmLimit = Entry.Imm1Limit;
332 switch (Entry.WideOpc) {
334 llvm_unreachable("Unexpected Thumb2 load / store opcode!");
337 if (MI->getOperand(1).getReg() == ARM::SP) {
338 Opc = Entry.NarrowOpc2;
339 ImmLimit = Entry.Imm2Limit;
371 unsigned BaseReg = MI->getOperand(0).getReg();
372 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
375 // For the non-writeback version (this one), the base register must be
376 // one of the registers being loaded.
378 for (unsigned i = 4; i < MI->getNumOperands(); ++i) {
379 if (MI->getOperand(i).getReg() == BaseReg) {
392 case ARM::t2LDMIA_RET: {
393 unsigned BaseReg = MI->getOperand(1).getReg();
394 if (BaseReg != ARM::SP)
396 Opc = Entry.NarrowOpc2; // tPOP_RET
401 case ARM::t2LDMIA_UPD:
402 case ARM::t2LDMDB_UPD:
403 case ARM::t2STMIA_UPD:
404 case ARM::t2STMDB_UPD: {
407 unsigned BaseReg = MI->getOperand(1).getReg();
408 if (BaseReg == ARM::SP &&
409 (Entry.WideOpc == ARM::t2LDMIA_UPD ||
410 Entry.WideOpc == ARM::t2STMDB_UPD)) {
411 Opc = Entry.NarrowOpc2; // tPOP or tPUSH
413 } else if (!isARMLowRegister(BaseReg) ||
414 (Entry.WideOpc != ARM::t2LDMIA_UPD &&
415 Entry.WideOpc != ARM::t2STMIA_UPD)) {
424 unsigned OffsetReg = 0;
425 bool OffsetKill = false;
427 OffsetReg = MI->getOperand(2).getReg();
428 OffsetKill = MI->getOperand(2).isKill();
430 if (MI->getOperand(3).getImm())
431 // Thumb1 addressing mode doesn't support shift.
435 unsigned OffsetImm = 0;
437 OffsetImm = MI->getOperand(2).getImm();
438 unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
440 if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset)
441 // Make sure the immediate field fits.
445 // Add the 16-bit load / store instruction.
446 DebugLoc dl = MI->getDebugLoc();
447 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
449 MIB.addOperand(MI->getOperand(0));
450 MIB.addOperand(MI->getOperand(1));
453 MIB.addImm(OffsetImm / Scale);
455 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
458 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
461 // Transfer the rest of operands.
462 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
463 MIB.addOperand(MI->getOperand(OpNum));
465 // Transfer memoperands.
466 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
468 // Transfer MI flags.
469 MIB.setMIFlags(MI->getFlags());
471 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
479 Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
480 const ReduceEntry &Entry,
481 bool LiveCPSR, MachineInstr *CPSRDef) {
482 unsigned Opc = MI->getOpcode();
483 if (Opc == ARM::t2ADDri) {
484 // If the source register is SP, try to reduce to tADDrSPi, otherwise
485 // it's a normal reduce.
486 if (MI->getOperand(1).getReg() != ARM::SP) {
487 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef))
489 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
491 // Try to reduce to tADDrSPi.
492 unsigned Imm = MI->getOperand(2).getImm();
493 // The immediate must be in range, the destination register must be a low
494 // reg, the predicate must be "always" and the condition flags must not
496 if (Imm & 3 || Imm > 1024)
498 if (!isARMLowRegister(MI->getOperand(0).getReg()))
500 if (MI->getOperand(3).getImm() != ARMCC::AL)
502 const MCInstrDesc &MCID = MI->getDesc();
503 if (MCID.hasOptionalDef() &&
504 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
507 MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(),
508 TII->get(ARM::tADDrSPi))
509 .addOperand(MI->getOperand(0))
510 .addOperand(MI->getOperand(1))
511 .addImm(Imm / 4); // The tADDrSPi has an implied scale by four.
513 // Transfer MI flags.
514 MIB.setMIFlags(MI->getFlags());
516 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB);
523 if (Entry.LowRegs1 && !VerifyLowRegs(MI))
526 const MCInstrDesc &MCID = MI->getDesc();
527 if (MCID.mayLoad() || MCID.mayStore())
528 return ReduceLoadStore(MBB, MI, Entry);
533 case ARM::t2ADDSrr: {
534 unsigned PredReg = 0;
535 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
538 case ARM::t2ADDSri: {
539 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef))
544 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
551 if (MI->getOperand(2).getImm() == 0)
552 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
555 // Can convert only 'pure' immediate operands, not immediates obtained as
556 // globals' addresses.
557 if (MI->getOperand(1).isImm())
558 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
561 // Try to reduce to the lo-reg only version first. Why there are two
562 // versions of the instruction is a mystery.
563 // It would be nice to just have two entries in the master table that
564 // are prioritized, but the table assumes a unique entry for each
565 // source insn opcode. So for now, we hack a local entry record to use.
566 static const ReduceEntry NarrowEntry =
567 { ARM::t2CMPrr,ARM::tCMPr, 0, 0, 0, 1, 1,2, 0, 0,1 };
568 if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, CPSRDef))
570 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
577 Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
578 const ReduceEntry &Entry,
579 bool LiveCPSR, MachineInstr *CPSRDef) {
581 if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
584 unsigned Reg0 = MI->getOperand(0).getReg();
585 unsigned Reg1 = MI->getOperand(1).getReg();
587 // Try to commute the operands to make it a 2-address instruction.
588 unsigned CommOpIdx1, CommOpIdx2;
589 if (!TII->findCommutedOpIndices(MI, CommOpIdx1, CommOpIdx2) ||
590 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0)
592 MachineInstr *CommutedMI = TII->commuteInstruction(MI);
596 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
598 if (Entry.Imm2Limit) {
599 unsigned Imm = MI->getOperand(2).getImm();
600 unsigned Limit = (1 << Entry.Imm2Limit) - 1;
604 unsigned Reg2 = MI->getOperand(2).getReg();
605 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
609 // Check if it's possible / necessary to transfer the predicate.
610 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2);
611 unsigned PredReg = 0;
612 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
613 bool SkipPred = false;
614 if (Pred != ARMCC::AL) {
615 if (!NewMCID.isPredicable())
616 // Can't transfer predicate, fail.
619 SkipPred = !NewMCID.isPredicable();
624 const MCInstrDesc &MCID = MI->getDesc();
625 if (MCID.hasOptionalDef()) {
626 unsigned NumOps = MCID.getNumOperands();
627 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
628 if (HasCC && MI->getOperand(NumOps-1).isDead())
631 if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
634 // Avoid adding a false dependency on partial flag update by some 16-bit
635 // instructions which has the 's' bit set.
636 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
637 canAddPseudoFlagDep(CPSRDef, MI))
640 // Add the 16-bit instruction.
641 DebugLoc dl = MI->getDebugLoc();
642 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewMCID);
643 MIB.addOperand(MI->getOperand(0));
644 if (NewMCID.hasOptionalDef()) {
646 AddDefaultT1CC(MIB, CCDead);
651 // Transfer the rest of operands.
652 unsigned NumOps = MCID.getNumOperands();
653 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
654 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
656 if (SkipPred && MCID.OpInfo[i].isPredicate())
658 MIB.addOperand(MI->getOperand(i));
661 // Transfer MI flags.
662 MIB.setMIFlags(MI->getFlags());
664 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
672 Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
673 const ReduceEntry &Entry,
674 bool LiveCPSR, MachineInstr *CPSRDef) {
675 if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit))
678 unsigned Limit = ~0U;
680 Limit = (1 << Entry.Imm1Limit) - 1;
682 const MCInstrDesc &MCID = MI->getDesc();
683 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
684 if (MCID.OpInfo[i].isPredicate())
686 const MachineOperand &MO = MI->getOperand(i);
688 unsigned Reg = MO.getReg();
689 if (!Reg || Reg == ARM::CPSR)
691 if (Entry.LowRegs1 && !isARMLowRegister(Reg))
693 } else if (MO.isImm() &&
694 !MCID.OpInfo[i].isPredicate()) {
695 if (((unsigned)MO.getImm()) > Limit)
700 // Check if it's possible / necessary to transfer the predicate.
701 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1);
702 unsigned PredReg = 0;
703 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
704 bool SkipPred = false;
705 if (Pred != ARMCC::AL) {
706 if (!NewMCID.isPredicable())
707 // Can't transfer predicate, fail.
710 SkipPred = !NewMCID.isPredicable();
715 if (MCID.hasOptionalDef()) {
716 unsigned NumOps = MCID.getNumOperands();
717 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
718 if (HasCC && MI->getOperand(NumOps-1).isDead())
721 if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
724 // Avoid adding a false dependency on partial flag update by some 16-bit
725 // instructions which has the 's' bit set.
726 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
727 canAddPseudoFlagDep(CPSRDef, MI))
730 // Add the 16-bit instruction.
731 DebugLoc dl = MI->getDebugLoc();
732 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewMCID);
733 MIB.addOperand(MI->getOperand(0));
734 if (NewMCID.hasOptionalDef()) {
736 AddDefaultT1CC(MIB, CCDead);
741 // Transfer the rest of operands.
742 unsigned NumOps = MCID.getNumOperands();
743 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
744 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
746 if ((MCID.getOpcode() == ARM::t2RSBSri ||
747 MCID.getOpcode() == ARM::t2RSBri) && i == 2)
748 // Skip the zero immediate operand, it's now implicit.
750 bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate());
751 if (SkipPred && isPred)
753 const MachineOperand &MO = MI->getOperand(i);
754 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
755 // Skip implicit def of CPSR. Either it's modeled as an optional
756 // def now or it's already an implicit def on the new instruction.
760 if (!MCID.isPredicable() && NewMCID.isPredicable())
763 // Transfer MI flags.
764 MIB.setMIFlags(MI->getFlags());
766 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
773 static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR, bool &DefCPSR) {
775 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
776 const MachineOperand &MO = MI.getOperand(i);
777 if (!MO.isReg() || MO.isUndef() || MO.isUse())
779 if (MO.getReg() != ARM::CPSR)
787 return HasDef || LiveCPSR;
790 static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) {
791 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
792 const MachineOperand &MO = MI.getOperand(i);
793 if (!MO.isReg() || MO.isUndef() || MO.isDef())
795 if (MO.getReg() != ARM::CPSR)
797 assert(LiveCPSR && "CPSR liveness tracking is wrong!");
807 bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
808 bool Modified = false;
810 // Yes, CPSR could be livein.
811 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR);
812 MachineInstr *CPSRDef = 0;
814 MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
815 MachineBasicBlock::iterator NextMII;
816 for (; MII != E; MII = NextMII) {
817 NextMII = llvm::next(MII);
819 MachineInstr *MI = &*MII;
820 LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);
822 unsigned Opcode = MI->getOpcode();
823 DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode);
824 if (OPI != ReduceOpcodeMap.end()) {
825 const ReduceEntry &Entry = ReduceTable[OPI->second];
826 // Ignore "special" cases for now.
828 if (ReduceSpecial(MBB, MI, Entry, LiveCPSR, CPSRDef)) {
830 MachineBasicBlock::iterator I = prior(NextMII);
836 // Try to transform to a 16-bit two-address instruction.
837 if (Entry.NarrowOpc2 &&
838 ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef)) {
840 MachineBasicBlock::iterator I = prior(NextMII);
845 // Try to transform to a 16-bit non-two-address instruction.
846 if (Entry.NarrowOpc1 &&
847 ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef)) {
849 MachineBasicBlock::iterator I = prior(NextMII);
855 bool DefCPSR = false;
856 LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR, DefCPSR);
857 if (MI->getDesc().isCall())
858 // Calls don't really set CPSR.
861 // This is the last CPSR defining instruction.
868 bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
869 const TargetMachine &TM = MF.getTarget();
870 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
871 STI = &TM.getSubtarget<ARMSubtarget>();
873 bool Modified = false;
874 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
875 Modified |= ReduceMBB(*I);
879 /// createThumb2SizeReductionPass - Returns an instance of the Thumb2 size
881 FunctionPass *llvm::createThumb2SizeReductionPass() {
882 return new Thumb2SizeReduce();