1 //===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef THUMB2INSTRUCTIONINFO_H
15 #define THUMB2INSTRUCTIONINFO_H
18 #include "ARMInstrInfo.h"
19 #include "Thumb2RegisterInfo.h"
20 #include "llvm/Target/TargetInstrInfo.h"
24 class ScheduleHazardRecognizer;
26 class Thumb2InstrInfo : public ARMBaseInstrInfo {
27 Thumb2RegisterInfo RI;
29 explicit Thumb2InstrInfo(const ARMSubtarget &STI);
31 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
32 void getNoopForMachoTarget(MCInst &NopInst) const;
34 // Return the non-pre/post incrementing version of 'Opc'. Return 0
35 // if there is not such an opcode.
36 unsigned getUnindexedOpcode(unsigned Opc) const;
38 void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
39 MachineBasicBlock *NewDest) const;
41 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator MBBI) const;
44 void copyPhysReg(MachineBasicBlock &MBB,
45 MachineBasicBlock::iterator I, DebugLoc DL,
46 unsigned DestReg, unsigned SrcReg,
49 void storeRegToStackSlot(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MBBI,
51 unsigned SrcReg, bool isKill, int FrameIndex,
52 const TargetRegisterClass *RC,
53 const TargetRegisterInfo *TRI) const;
55 void loadRegFromStackSlot(MachineBasicBlock &MBB,
56 MachineBasicBlock::iterator MBBI,
57 unsigned DestReg, int FrameIndex,
58 const TargetRegisterClass *RC,
59 const TargetRegisterInfo *TRI) const;
61 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
62 /// two-addrss instruction inserted by two-address pass.
63 void scheduleTwoAddrSource(MachineInstr *SrcMI, MachineInstr *UseMI,
64 const TargetRegisterInfo &TRI) const;
66 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
67 /// such, whenever a client has an instance of instruction info, it should
68 /// always be able to get register info as well (through this method).
70 const Thumb2RegisterInfo &getRegisterInfo() const { return RI; }
73 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
74 /// to llvm::getInstrPredicate except it returns AL for conditional branch
75 /// instructions which are "predicated", but are not in IT blocks.
76 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
81 #endif // THUMB2INSTRUCTIONINFO_H