lib/Target/ARM/Thumb2InstrInfo.h

   1 //===- Thumb2InstrInfo.h - Thumb-2 Instruction Information ----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef THUMB2INSTRUCTIONINFO_H
  15 #define THUMB2INSTRUCTIONINFO_H
  16
  17 #include "llvm/Target/TargetInstrInfo.h"
  18 #include "ARM.h"
  19 #include "ARMInstrInfo.h"
  20 #include "Thumb2RegisterInfo.h"
  21
  22 namespace llvm {
  23   class ARMSubtarget;
  24
  25 class Thumb2InstrInfo : public ARMBaseInstrInfo {
  26   Thumb2RegisterInfo RI;
  27 public:
  28   explicit Thumb2InstrInfo(const ARMSubtarget &STI);
  29
  30   // Return the non-pre/post incrementing version of 'Opc'. Return 0
  31   // if there is not such an opcode.
  32   unsigned getUnindexedOpcode(unsigned Opc) const;
  33
  34   // Return the opcode that implements 'Op', or 0 if no opcode
  35   unsigned getOpcode(ARMII::Op Op) const;
  36
  37   // Return true if the block does not fall through.
  38   bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
  39
  40   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  41   /// such, whenever a client has an instance of instruction info, it should
  42   /// always be able to get register info as well (through this method).
  43   ///
  44   const Thumb2RegisterInfo &getRegisterInfo() const { return RI; }
  45
  46   bool copyRegToReg(MachineBasicBlock &MBB,
  47                             MachineBasicBlock::iterator I,
  48                             unsigned DestReg, unsigned SrcReg,
  49                             const TargetRegisterClass *DestRC,
  50                             const TargetRegisterClass *SrcRC) const;
  51
  52
  53
  54
  55   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
  56                                  MachineBasicBlock::iterator MI,
  57                                  const std::vector<CalleeSavedInfo> &CSI) const;
  58   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
  59                                    MachineBasicBlock::iterator MI,
  60                                    const std::vector<CalleeSavedInfo> &CSI) const;
  61
  62   bool isMoveInstr(const MachineInstr &MI,
  63                            unsigned &SrcReg, unsigned &DstReg,
  64                            unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
  65   unsigned isLoadFromStackSlot(const MachineInstr *MI,
  66                                        int &FrameIndex) const;
  67   unsigned isStoreToStackSlot(const MachineInstr *MI,
  68                                       int &FrameIndex) const;
  69
  70   void storeRegToStackSlot(MachineBasicBlock &MBB,
  71                                    MachineBasicBlock::iterator MBBI,
  72                                    unsigned SrcReg, bool isKill, int FrameIndex,
  73                                    const TargetRegisterClass *RC) const;
  74
  75   void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
  76                               SmallVectorImpl<MachineOperand> &Addr,
  77                               const TargetRegisterClass *RC,
  78                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
  79
  80   void loadRegFromStackSlot(MachineBasicBlock &MBB,
  81                                     MachineBasicBlock::iterator MBBI,
  82                                     unsigned DestReg, int FrameIndex,
  83                                     const TargetRegisterClass *RC) const;
  84
  85   void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
  86                                SmallVectorImpl<MachineOperand> &Addr,
  87                                const TargetRegisterClass *RC,
  88                                SmallVectorImpl<MachineInstr*> &NewMIs) const;
  89
  90   bool canFoldMemoryOperand(const MachineInstr *MI,
  91                                     const SmallVectorImpl<unsigned> &Ops) const;
  92
  93   MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
  94                                       MachineInstr* MI,
  95                                       const SmallVectorImpl<unsigned> &Ops,
  96                                       int FrameIndex) const;
  97
  98   MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
  99                                       MachineInstr* MI,
 100                                       const SmallVectorImpl<unsigned> &Ops,
 101                                       MachineInstr* LoadMI) const {
 102     return 0;
 103   }
 104
 105
 106 };
 107 }
 108
 109 #endif // THUMB2INSTRUCTIONINFO_H