1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "Thumb2InstrInfo.h"
25 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
26 : ARMBaseInstrInfo(STI), RI(*this, STI) {
29 unsigned Thumb2InstrInfo::
30 getUnindexedOpcode(unsigned Opc) const {
35 unsigned Thumb2InstrInfo::
36 getOpcode(ARMII::Op Op) const {
38 case ARMII::ADDri: return ARM::t2ADDri;
39 case ARMII::ADDrs: return ARM::t2ADDrs;
40 case ARMII::ADDrr: return ARM::t2ADDrr;
41 case ARMII::B: return ARM::t2B;
42 case ARMII::Bcc: return ARM::t2Bcc;
43 case ARMII::BR_JTr: return ARM::t2BR_JTr;
44 case ARMII::BR_JTm: return ARM::t2BR_JTm;
45 case ARMII::BR_JTadd: return ARM::t2BR_JTadd;
46 case ARMII::BX_RET: return ARM::t2BX_RET;
47 case ARMII::FCPYS: return ARM::FCPYS;
48 case ARMII::FCPYD: return ARM::FCPYD;
49 case ARMII::FLDD: return ARM::FLDD;
50 case ARMII::FLDS: return ARM::FLDS;
51 case ARMII::FSTD: return ARM::FSTD;
52 case ARMII::FSTS: return ARM::FSTS;
53 case ARMII::LDR: return ARM::LDR; // FIXME
54 case ARMII::MOVr: return ARM::t2MOVr;
55 case ARMII::STR: return ARM::STR; // FIXME
56 case ARMII::SUBri: return ARM::t2SUBri;
57 case ARMII::SUBrs: return ARM::t2SUBrs;
58 case ARMII::SUBrr: return ARM::t2SUBrr;
59 case ARMII::VMOVD: return ARM::VMOVD;
60 case ARMII::VMOVQ: return ARM::VMOVQ;
69 Thumb2InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
70 if (MBB.empty()) return false;
73 switch (MBB.back().getOpcode()) {
76 case ARM::t2B: // Uncond branch.
77 case ARM::t2BR_JTr: // Jumptable branch.
78 case ARM::t2BR_JTm: // Jumptable branch through mem.
79 case ARM::t2BR_JTadd: // Jumptable branch add to pc.
82 case ARM::tBX_RET_vararg:
95 bool Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
96 MachineBasicBlock::iterator I,
97 unsigned DestReg, unsigned SrcReg,
98 const TargetRegisterClass *DestRC,
99 const TargetRegisterClass *SrcRC) const {
100 DebugLoc DL = DebugLoc::getUnknownLoc();
101 if (I != MBB.end()) DL = I->getDebugLoc();
103 if (DestRC == ARM::GPRRegisterClass) {
104 if (SrcRC == ARM::GPRRegisterClass) {
105 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);
106 } else if (SrcRC == ARM::tGPRRegisterClass) {
107 BuildMI(MBB, I, DL, get(ARM::tMOVlor2hir), DestReg).addReg(SrcReg);
110 } else if (DestRC == ARM::tGPRRegisterClass) {
111 if (SrcRC == ARM::GPRRegisterClass) {
112 BuildMI(MBB, I, DL, get(ARM::tMOVhir2lor), DestReg).addReg(SrcReg);
114 } else if (SrcRC == ARM::tGPRRegisterClass) {
115 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
128 bool Thumb2InstrInfo::isMoveInstr(const MachineInstr &MI,
129 unsigned &SrcReg, unsigned &DstReg,
130 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
131 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
133 unsigned oc = MI.getOpcode();
138 case ARM::tMOVhir2lor:
139 case ARM::tMOVlor2hir:
140 case ARM::tMOVhir2hir:
141 assert(MI.getDesc().getNumOperands() >= 2 &&
142 MI.getOperand(0).isReg() &&
143 MI.getOperand(1).isReg() &&
144 "Invalid Thumb MOV instruction");
145 SrcReg = MI.getOperand(1).getReg();
146 DstReg = MI.getOperand(0).getReg();
151 unsigned Thumb2InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
152 int &FrameIndex) const {
153 switch (MI->getOpcode()) {
156 if (MI->getOperand(1).isFI() &&
157 MI->getOperand(2).isImm() &&
158 MI->getOperand(2).getImm() == 0) {
159 FrameIndex = MI->getOperand(1).getIndex();
160 return MI->getOperand(0).getReg();
167 unsigned Thumb2InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
168 int &FrameIndex) const {
169 switch (MI->getOpcode()) {
172 if (MI->getOperand(1).isFI() &&
173 MI->getOperand(2).isImm() &&
174 MI->getOperand(2).getImm() == 0) {
175 FrameIndex = MI->getOperand(1).getIndex();
176 return MI->getOperand(0).getReg();
183 bool Thumb2InstrInfo::
184 canFoldMemoryOperand(const MachineInstr *MI,
185 const SmallVectorImpl<unsigned> &Ops) const {
186 if (Ops.size() != 1) return false;
188 unsigned OpNum = Ops[0];
189 unsigned Opc = MI->getOpcode();
193 case ARM::tMOVlor2hir:
194 case ARM::tMOVhir2lor:
195 case ARM::tMOVhir2hir: {
196 if (OpNum == 0) { // move -> store
197 unsigned SrcReg = MI->getOperand(1).getReg();
198 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
199 // tSpill cannot take a high register operand.
201 } else { // move -> load
202 unsigned DstReg = MI->getOperand(0).getReg();
203 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
204 // tRestore cannot target a high register operand.
214 void Thumb2InstrInfo::
215 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
216 unsigned SrcReg, bool isKill, int FI,
217 const TargetRegisterClass *RC) const {
218 DebugLoc DL = DebugLoc::getUnknownLoc();
219 if (I != MBB.end()) DL = I->getDebugLoc();
221 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
223 if (RC == ARM::tGPRRegisterClass) {
224 BuildMI(MBB, I, DL, get(ARM::tSpill))
225 .addReg(SrcReg, getKillRegState(isKill))
226 .addFrameIndex(FI).addImm(0);
230 void Thumb2InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
232 SmallVectorImpl<MachineOperand> &Addr,
233 const TargetRegisterClass *RC,
234 SmallVectorImpl<MachineInstr*> &NewMIs) const{
235 DebugLoc DL = DebugLoc::getUnknownLoc();
238 assert(RC == ARM::GPRRegisterClass && "Unknown regclass!");
239 if (RC == ARM::GPRRegisterClass) {
240 Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
243 MachineInstrBuilder MIB =
244 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
245 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
246 MIB.addOperand(Addr[i]);
247 NewMIs.push_back(MIB);
251 void Thumb2InstrInfo::
252 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
253 unsigned DestReg, int FI,
254 const TargetRegisterClass *RC) const {
255 DebugLoc DL = DebugLoc::getUnknownLoc();
256 if (I != MBB.end()) DL = I->getDebugLoc();
258 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
260 if (RC == ARM::tGPRRegisterClass) {
261 BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
262 .addFrameIndex(FI).addImm(0);
266 void Thumb2InstrInfo::
267 loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
268 SmallVectorImpl<MachineOperand> &Addr,
269 const TargetRegisterClass *RC,
270 SmallVectorImpl<MachineInstr*> &NewMIs) const {
271 DebugLoc DL = DebugLoc::getUnknownLoc();
274 if (RC == ARM::GPRRegisterClass) {
275 Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
278 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
279 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
280 MIB.addOperand(Addr[i]);
281 NewMIs.push_back(MIB);
285 bool Thumb2InstrInfo::
286 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
287 MachineBasicBlock::iterator MI,
288 const std::vector<CalleeSavedInfo> &CSI) const {
292 DebugLoc DL = DebugLoc::getUnknownLoc();
293 if (MI != MBB.end()) DL = MI->getDebugLoc();
295 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
296 for (unsigned i = CSI.size(); i != 0; --i) {
297 unsigned Reg = CSI[i-1].getReg();
298 // Add the callee-saved register as live-in. It's killed at the spill.
300 MIB.addReg(Reg, RegState::Kill);
305 bool Thumb2InstrInfo::
306 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
307 MachineBasicBlock::iterator MI,
308 const std::vector<CalleeSavedInfo> &CSI) const {
309 MachineFunction &MF = *MBB.getParent();
310 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
314 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
315 MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
316 for (unsigned i = CSI.size(); i != 0; --i) {
317 unsigned Reg = CSI[i-1].getReg();
318 if (Reg == ARM::LR) {
319 // Special epilogue for vararg functions. See emitEpilogue
323 PopMI->setDesc(get(ARM::tPOP_RET));
326 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
329 // It's illegal to emit pop instruction without operands.
330 if (PopMI->getNumOperands() > 0)
331 MBB.insert(MI, PopMI);
336 MachineInstr *Thumb2InstrInfo::
337 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
338 const SmallVectorImpl<unsigned> &Ops, int FI) const {
339 if (Ops.size() != 1) return NULL;
341 unsigned OpNum = Ops[0];
342 unsigned Opc = MI->getOpcode();
343 MachineInstr *NewMI = NULL;
347 case ARM::tMOVlor2hir:
348 case ARM::tMOVhir2lor:
349 case ARM::tMOVhir2hir: {
350 if (OpNum == 0) { // move -> store
351 unsigned SrcReg = MI->getOperand(1).getReg();
352 bool isKill = MI->getOperand(1).isKill();
353 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
354 // tSpill cannot take a high register operand.
356 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
357 .addReg(SrcReg, getKillRegState(isKill))
358 .addFrameIndex(FI).addImm(0);
359 } else { // move -> load
360 unsigned DstReg = MI->getOperand(0).getReg();
361 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
362 // tRestore cannot target a high register operand.
364 bool isDead = MI->getOperand(0).isDead();
365 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
366 .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
367 .addFrameIndex(FI).addImm(0);