1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "Thumb2InstrInfo.h"
25 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
26 : ARMBaseInstrInfo(STI), RI(*this, STI) {
29 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
34 unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const {
36 case ARMII::ADDri: return ARM::t2ADDri;
37 case ARMII::ADDrs: return ARM::t2ADDrs;
38 case ARMII::ADDrr: return ARM::t2ADDrr;
39 case ARMII::B: return ARM::t2B;
40 case ARMII::Bcc: return ARM::t2Bcc;
41 case ARMII::BR_JTr: return ARM::t2BR_JTr;
42 case ARMII::BR_JTm: return ARM::t2BR_JTm;
43 case ARMII::BR_JTadd: return ARM::t2BR_JTadd;
44 case ARMII::BX_RET: return ARM::tBX_RET;
45 case ARMII::FCPYS: return ARM::FCPYS;
46 case ARMII::FCPYD: return ARM::FCPYD;
47 case ARMII::FLDD: return ARM::FLDD;
48 case ARMII::FLDS: return ARM::FLDS;
49 case ARMII::FSTD: return ARM::FSTD;
50 case ARMII::FSTS: return ARM::FSTS;
51 case ARMII::LDR: return ARM::LDR; // FIXME
52 case ARMII::MOVr: return ARM::t2MOVr;
53 case ARMII::STR: return ARM::STR; // FIXME
54 case ARMII::SUBri: return ARM::t2SUBri;
55 case ARMII::SUBrs: return ARM::t2SUBrs;
56 case ARMII::SUBrr: return ARM::t2SUBrr;
57 case ARMII::VMOVD: return ARM::VMOVD;
58 case ARMII::VMOVQ: return ARM::VMOVQ;
67 Thumb2InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
68 if (MBB.empty()) return false;
71 switch (MBB.back().getOpcode()) {
73 case ARM::t2B: // Uncond branch.
74 case ARM::t2BR_JTr: // Jumptable branch.
75 case ARM::t2BR_JTm: // Jumptable branch through mem.
76 case ARM::t2BR_JTadd: // Jumptable branch add to pc.
79 case ARM::tBX_RET_vararg:
92 Thumb2InstrInfo::unsignedOffsetOpcodeToSigned(unsigned opcode,
93 unsigned *NumBits) const
99 case ARM::t2LDRi12: return ARM::t2LDRi8;
100 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
101 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
102 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
103 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
104 case ARM::t2STRi12: return ARM::t2STRi8;
105 case ARM::t2STRBi12: return ARM::t2STRBi8;
106 case ARM::t2STRHi12: return ARM::t2STRHi8;
115 Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
116 MachineBasicBlock::iterator I,
117 unsigned DestReg, unsigned SrcReg,
118 const TargetRegisterClass *DestRC,
119 const TargetRegisterClass *SrcRC) const {
120 DebugLoc DL = DebugLoc::getUnknownLoc();
121 if (I != MBB.end()) DL = I->getDebugLoc();
123 if ((DestRC == ARM::GPRRegisterClass &&
124 SrcRC == ARM::tGPRRegisterClass) ||
125 (DestRC == ARM::tGPRRegisterClass &&
126 SrcRC == ARM::GPRRegisterClass)) {
127 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::MOVr)),
128 DestReg).addReg(SrcReg)));
132 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);