1 //===-- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "MCTargetDesc/ARMAddressingModes.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/Support/CommandLine.h"
29 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
30 cl::desc("Use old-style Thumb2 if-conversion heuristics"),
33 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
34 : ARMBaseInstrInfo(STI), RI(STI) {
37 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
38 void Thumb2InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
39 NopInst.setOpcode(ARM::tHINT);
40 NopInst.addOperand(MCOperand::CreateImm(0));
41 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
42 NopInst.addOperand(MCOperand::CreateReg(0));
45 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
51 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
52 MachineBasicBlock *NewDest) const {
53 MachineBasicBlock *MBB = Tail->getParent();
54 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
55 if (!AFI->hasITBlocks()) {
56 TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
60 // If the first instruction of Tail is predicated, we may have to update
61 // the IT instruction.
63 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
64 MachineBasicBlock::iterator MBBI = Tail;
66 // Expecting at least the t2IT instruction before it.
69 // Actually replace the tail.
70 TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
73 if (CC != ARMCC::AL) {
74 MachineBasicBlock::iterator E = MBB->begin();
75 unsigned Count = 4; // At most 4 instructions in an IT block.
76 while (Count && MBBI != E) {
77 if (MBBI->isDebugValue()) {
81 if (MBBI->getOpcode() == ARM::t2IT) {
82 unsigned Mask = MBBI->getOperand(1).getImm();
84 MBBI->eraseFromParent();
86 unsigned MaskOn = 1 << Count;
87 unsigned MaskOff = ~(MaskOn - 1);
88 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
96 // Ctrl flow can reach here if branch folding is run before IT block
102 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
103 MachineBasicBlock::iterator MBBI) const {
104 while (MBBI->isDebugValue()) {
106 if (MBBI == MBB.end())
110 unsigned PredReg = 0;
111 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
114 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
115 MachineBasicBlock::iterator I, DebugLoc DL,
116 unsigned DestReg, unsigned SrcReg,
117 bool KillSrc) const {
118 // Handle SPR, DPR, and QPR copies.
119 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
120 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
122 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
123 .addReg(SrcReg, getKillRegState(KillSrc)));
126 void Thumb2InstrInfo::
127 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
128 unsigned SrcReg, bool isKill, int FI,
129 const TargetRegisterClass *RC,
130 const TargetRegisterInfo *TRI) const {
132 if (I != MBB.end()) DL = I->getDebugLoc();
134 MachineFunction &MF = *MBB.getParent();
135 MachineFrameInfo &MFI = *MF.getFrameInfo();
136 MachineMemOperand *MMO =
137 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
138 MachineMemOperand::MOStore,
139 MFI.getObjectSize(FI),
140 MFI.getObjectAlignment(FI));
142 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
143 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
144 RC == &ARM::GPRnopcRegClass) {
145 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
146 .addReg(SrcReg, getKillRegState(isKill))
147 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
151 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
152 // Thumb2 STRD expects its dest-registers to be in rGPR. Not a problem for
153 // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
155 MachineRegisterInfo *MRI = &MF.getRegInfo();
156 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
158 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
159 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
160 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
161 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
166 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
169 void Thumb2InstrInfo::
170 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
171 unsigned DestReg, int FI,
172 const TargetRegisterClass *RC,
173 const TargetRegisterInfo *TRI) const {
174 MachineFunction &MF = *MBB.getParent();
175 MachineFrameInfo &MFI = *MF.getFrameInfo();
176 MachineMemOperand *MMO =
177 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
178 MachineMemOperand::MOLoad,
179 MFI.getObjectSize(FI),
180 MFI.getObjectAlignment(FI));
182 if (I != MBB.end()) DL = I->getDebugLoc();
184 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
185 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
186 RC == &ARM::GPRnopcRegClass) {
187 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
188 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
192 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
193 // Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
194 // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
196 MachineRegisterInfo *MRI = &MF.getRegInfo();
197 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
199 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
200 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
201 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
202 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
205 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
206 MIB.addReg(DestReg, RegState::ImplicitDefine);
210 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
213 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
214 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
215 unsigned DestReg, unsigned BaseReg, int NumBytes,
216 ARMCC::CondCodes Pred, unsigned PredReg,
217 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
218 if (NumBytes == 0 && DestReg != BaseReg) {
219 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
220 .addReg(BaseReg, RegState::Kill)
221 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
225 bool isSub = NumBytes < 0;
226 if (isSub) NumBytes = -NumBytes;
228 // If profitable, use a movw or movt to materialize the offset.
229 // FIXME: Use the scavenger to grab a scratch register.
230 if (DestReg != ARM::SP && DestReg != BaseReg &&
232 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
234 if (NumBytes < 65536) {
235 // Use a movw to materialize the 16-bit constant.
236 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
238 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
240 } else if ((NumBytes & 0xffff) == 0) {
241 // Use a movt to materialize the 32-bit constant.
242 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
244 .addImm(NumBytes >> 16)
245 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
251 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
252 .addReg(BaseReg, RegState::Kill)
253 .addReg(DestReg, RegState::Kill)
254 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
255 .setMIFlags(MIFlags);
257 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
258 .addReg(DestReg, RegState::Kill)
259 .addReg(BaseReg, RegState::Kill)
260 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
261 .setMIFlags(MIFlags);
268 unsigned ThisVal = NumBytes;
270 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
271 // mov sp, rn. Note t2MOVr cannot be used.
272 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
273 .addReg(BaseReg).setMIFlags(MIFlags));
278 bool HasCCOut = true;
279 if (BaseReg == ARM::SP) {
281 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
282 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
283 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
284 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
285 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
290 // sub rd, sp, so_imm
291 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
292 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
295 // FIXME: Move this to ARMAddressingModes.h?
296 unsigned RotAmt = countLeadingZeros(ThisVal);
297 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
298 NumBytes &= ~ThisVal;
299 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
300 "Bit extraction didn't work?");
303 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
304 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
305 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
307 } else if (ThisVal < 4096) {
308 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
312 // FIXME: Move this to ARMAddressingModes.h?
313 unsigned RotAmt = countLeadingZeros(ThisVal);
314 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
315 NumBytes &= ~ThisVal;
316 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
317 "Bit extraction didn't work?");
321 // Build the new ADD / SUB.
322 MachineInstrBuilder MIB =
323 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
324 .addReg(BaseReg, RegState::Kill)
325 .addImm(ThisVal)).setMIFlags(MIFlags);
334 negativeOffsetOpcode(unsigned opcode)
337 case ARM::t2LDRi12: return ARM::t2LDRi8;
338 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
339 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
340 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
341 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
342 case ARM::t2STRi12: return ARM::t2STRi8;
343 case ARM::t2STRBi12: return ARM::t2STRBi8;
344 case ARM::t2STRHi12: return ARM::t2STRHi8;
345 case ARM::t2PLDi12: return ARM::t2PLDi8;
366 positiveOffsetOpcode(unsigned opcode)
369 case ARM::t2LDRi8: return ARM::t2LDRi12;
370 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
371 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
372 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
373 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
374 case ARM::t2STRi8: return ARM::t2STRi12;
375 case ARM::t2STRBi8: return ARM::t2STRBi12;
376 case ARM::t2STRHi8: return ARM::t2STRHi12;
377 case ARM::t2PLDi8: return ARM::t2PLDi12;
382 case ARM::t2LDRSHi12:
383 case ARM::t2LDRSBi12:
398 immediateOffsetOpcode(unsigned opcode)
401 case ARM::t2LDRs: return ARM::t2LDRi12;
402 case ARM::t2LDRHs: return ARM::t2LDRHi12;
403 case ARM::t2LDRBs: return ARM::t2LDRBi12;
404 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
405 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
406 case ARM::t2STRs: return ARM::t2STRi12;
407 case ARM::t2STRBs: return ARM::t2STRBi12;
408 case ARM::t2STRHs: return ARM::t2STRHi12;
409 case ARM::t2PLDs: return ARM::t2PLDi12;
414 case ARM::t2LDRSHi12:
415 case ARM::t2LDRSBi12:
438 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
439 unsigned FrameReg, int &Offset,
440 const ARMBaseInstrInfo &TII) {
441 unsigned Opcode = MI.getOpcode();
442 const MCInstrDesc &Desc = MI.getDesc();
443 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
446 // Memory operands in inline assembly always use AddrModeT2_i12.
447 if (Opcode == ARM::INLINEASM)
448 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
450 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
451 Offset += MI.getOperand(FrameRegIdx+1).getImm();
454 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
455 // Turn it into a move.
456 MI.setDesc(TII.get(ARM::tMOVr));
457 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
458 // Remove offset and remaining explicit predicate operands.
459 do MI.RemoveOperand(FrameRegIdx+1);
460 while (MI.getNumOperands() > FrameRegIdx+1);
461 MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
466 bool HasCCOut = Opcode != ARM::t2ADDri12;
471 MI.setDesc(TII.get(ARM::t2SUBri));
473 MI.setDesc(TII.get(ARM::t2ADDri));
476 // Common case: small offset, fits into instruction.
477 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
478 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
479 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
480 // Add cc_out operand if the original instruction did not have one.
482 MI.addOperand(MachineOperand::CreateReg(0, false));
486 // Another common case: imm12.
488 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
489 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
490 MI.setDesc(TII.get(NewOpc));
491 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
492 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
493 // Remove the cc_out operand.
495 MI.RemoveOperand(MI.getNumOperands()-1);
500 // Otherwise, extract 8 adjacent bits from the immediate into this
502 unsigned RotAmt = countLeadingZeros<unsigned>(Offset);
503 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
505 // We will handle these bits from offset, clear them.
506 Offset &= ~ThisImmVal;
508 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
509 "Bit extraction didn't work?");
510 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
511 // Add cc_out operand if the original instruction did not have one.
513 MI.addOperand(MachineOperand::CreateReg(0, false));
517 // AddrMode4 and AddrMode6 cannot handle any offset.
518 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
521 // AddrModeT2_so cannot handle any offset. If there is no offset
522 // register then we change to an immediate version.
523 unsigned NewOpc = Opcode;
524 if (AddrMode == ARMII::AddrModeT2_so) {
525 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
526 if (OffsetReg != 0) {
527 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
531 MI.RemoveOperand(FrameRegIdx+1);
532 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
533 NewOpc = immediateOffsetOpcode(Opcode);
534 AddrMode = ARMII::AddrModeT2_i12;
537 unsigned NumBits = 0;
539 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
540 // i8 supports only negative, and i12 supports only positive, so
541 // based on Offset sign convert Opcode to the appropriate
543 Offset += MI.getOperand(FrameRegIdx+1).getImm();
545 NewOpc = negativeOffsetOpcode(Opcode);
550 NewOpc = positiveOffsetOpcode(Opcode);
553 } else if (AddrMode == ARMII::AddrMode5) {
555 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
556 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
557 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
561 Offset += InstrOffs * 4;
562 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
567 } else if (AddrMode == ARMII::AddrModeT2_i8s4) {
568 Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
570 // MCInst operand has already scaled value.
577 llvm_unreachable("Unsupported addressing mode!");
580 if (NewOpc != Opcode)
581 MI.setDesc(TII.get(NewOpc));
583 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
585 // Attempt to fold address computation
586 // Common case: small offset, fits into instruction.
587 int ImmedOffset = Offset / Scale;
588 unsigned Mask = (1 << NumBits) - 1;
589 if ((unsigned)Offset <= Mask * Scale) {
590 // Replace the FrameIndex with fp/sp
591 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
593 if (AddrMode == ARMII::AddrMode5)
594 // FIXME: Not consistent.
595 ImmedOffset |= 1 << NumBits;
597 ImmedOffset = -ImmedOffset;
599 ImmOp.ChangeToImmediate(ImmedOffset);
604 // Otherwise, offset doesn't fit. Pull in what we can to simplify
605 ImmedOffset = ImmedOffset & Mask;
607 if (AddrMode == ARMII::AddrMode5)
608 // FIXME: Not consistent.
609 ImmedOffset |= 1 << NumBits;
611 ImmedOffset = -ImmedOffset;
612 if (ImmedOffset == 0)
613 // Change the opcode back if the encoded offset is zero.
614 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
617 ImmOp.ChangeToImmediate(ImmedOffset);
618 Offset &= ~(Mask*Scale);
621 Offset = (isSub) ? -Offset : Offset;
626 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
627 unsigned Opc = MI->getOpcode();
628 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
630 return getInstrPredicate(MI, PredReg);