1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "Thumb2InstrInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/Support/CommandLine.h"
30 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
31 cl::desc("Use old-style Thumb2 if-conversion heuristics"),
34 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
35 : ARMBaseInstrInfo(STI), RI(*this, STI) {
38 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
44 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
45 MachineBasicBlock *NewDest) const {
46 MachineBasicBlock *MBB = Tail->getParent();
47 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
48 if (!AFI->hasITBlocks()) {
49 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
53 // If the first instruction of Tail is predicated, we may have to update
54 // the IT instruction.
56 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
57 MachineBasicBlock::iterator MBBI = Tail;
59 // Expecting at least the t2IT instruction before it.
62 // Actually replace the tail.
63 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
66 if (CC != ARMCC::AL) {
67 MachineBasicBlock::iterator E = MBB->begin();
68 unsigned Count = 4; // At most 4 instructions in an IT block.
69 while (Count && MBBI != E) {
70 if (MBBI->isDebugValue()) {
74 if (MBBI->getOpcode() == ARM::t2IT) {
75 unsigned Mask = MBBI->getOperand(1).getImm();
77 MBBI->eraseFromParent();
79 unsigned MaskOn = 1 << Count;
80 unsigned MaskOff = ~(MaskOn - 1);
81 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
89 // Ctrl flow can reach here if branch folding is run before IT block
95 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
96 MachineBasicBlock::iterator MBBI) const {
97 while (MBBI->isDebugValue()) {
99 if (MBBI == MBB.end())
103 unsigned PredReg = 0;
104 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
107 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
108 MachineBasicBlock::iterator I, DebugLoc DL,
109 unsigned DestReg, unsigned SrcReg,
110 bool KillSrc) const {
111 // Handle SPR, DPR, and QPR copies.
112 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
113 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
115 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
116 .addReg(SrcReg, getKillRegState(KillSrc)));
119 void Thumb2InstrInfo::
120 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
121 unsigned SrcReg, bool isKill, int FI,
122 const TargetRegisterClass *RC,
123 const TargetRegisterInfo *TRI) const {
124 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
125 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
127 if (I != MBB.end()) DL = I->getDebugLoc();
129 MachineFunction &MF = *MBB.getParent();
130 MachineFrameInfo &MFI = *MF.getFrameInfo();
131 MachineMemOperand *MMO =
132 MF.getMachineMemOperand(
133 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
134 MachineMemOperand::MOStore,
135 MFI.getObjectSize(FI),
136 MFI.getObjectAlignment(FI));
137 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
138 .addReg(SrcReg, getKillRegState(isKill))
139 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
143 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
146 void Thumb2InstrInfo::
147 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
148 unsigned DestReg, int FI,
149 const TargetRegisterClass *RC,
150 const TargetRegisterInfo *TRI) const {
151 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
152 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
154 if (I != MBB.end()) DL = I->getDebugLoc();
156 MachineFunction &MF = *MBB.getParent();
157 MachineFrameInfo &MFI = *MF.getFrameInfo();
158 MachineMemOperand *MMO =
159 MF.getMachineMemOperand(
160 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
161 MachineMemOperand::MOLoad,
162 MFI.getObjectSize(FI),
163 MFI.getObjectAlignment(FI));
164 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
165 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
169 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
172 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
173 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
174 unsigned DestReg, unsigned BaseReg, int NumBytes,
175 ARMCC::CondCodes Pred, unsigned PredReg,
176 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
177 bool isSub = NumBytes < 0;
178 if (isSub) NumBytes = -NumBytes;
180 // If profitable, use a movw or movt to materialize the offset.
181 // FIXME: Use the scavenger to grab a scratch register.
182 if (DestReg != ARM::SP && DestReg != BaseReg &&
184 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
186 if (NumBytes < 65536) {
187 // Use a movw to materialize the 16-bit constant.
188 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
190 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
192 } else if ((NumBytes & 0xffff) == 0) {
193 // Use a movt to materialize the 32-bit constant.
194 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
196 .addImm(NumBytes >> 16)
197 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
203 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
204 .addReg(BaseReg, RegState::Kill)
205 .addReg(DestReg, RegState::Kill)
206 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
207 .setMIFlags(MIFlags);
209 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
210 .addReg(DestReg, RegState::Kill)
211 .addReg(BaseReg, RegState::Kill)
212 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
213 .setMIFlags(MIFlags);
220 unsigned ThisVal = NumBytes;
222 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
223 // mov sp, rn. Note t2MOVr cannot be used.
224 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
225 .addReg(BaseReg).setMIFlags(MIFlags));
230 bool HasCCOut = true;
231 if (BaseReg == ARM::SP) {
233 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
234 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
235 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
236 // FIXME: Fix Thumb1 immediate encoding.
237 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
238 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags);
243 // sub rd, sp, so_imm
244 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
245 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
248 // FIXME: Move this to ARMAddressingModes.h?
249 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
250 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
251 NumBytes &= ~ThisVal;
252 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
253 "Bit extraction didn't work?");
256 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
257 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
258 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
260 } else if (ThisVal < 4096) {
261 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
265 // FIXME: Move this to ARMAddressingModes.h?
266 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
267 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
268 NumBytes &= ~ThisVal;
269 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
270 "Bit extraction didn't work?");
274 // Build the new ADD / SUB.
275 MachineInstrBuilder MIB =
276 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
277 .addReg(BaseReg, RegState::Kill)
278 .addImm(ThisVal)).setMIFlags(MIFlags);
287 negativeOffsetOpcode(unsigned opcode)
290 case ARM::t2LDRi12: return ARM::t2LDRi8;
291 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
292 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
293 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
294 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
295 case ARM::t2STRi12: return ARM::t2STRi8;
296 case ARM::t2STRBi12: return ARM::t2STRBi8;
297 case ARM::t2STRHi12: return ARM::t2STRHi8;
317 positiveOffsetOpcode(unsigned opcode)
320 case ARM::t2LDRi8: return ARM::t2LDRi12;
321 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
322 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
323 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
324 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
325 case ARM::t2STRi8: return ARM::t2STRi12;
326 case ARM::t2STRBi8: return ARM::t2STRBi12;
327 case ARM::t2STRHi8: return ARM::t2STRHi12;
332 case ARM::t2LDRSHi12:
333 case ARM::t2LDRSBi12:
347 immediateOffsetOpcode(unsigned opcode)
350 case ARM::t2LDRs: return ARM::t2LDRi12;
351 case ARM::t2LDRHs: return ARM::t2LDRHi12;
352 case ARM::t2LDRBs: return ARM::t2LDRBi12;
353 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
354 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
355 case ARM::t2STRs: return ARM::t2STRi12;
356 case ARM::t2STRBs: return ARM::t2STRBi12;
357 case ARM::t2STRHs: return ARM::t2STRHi12;
362 case ARM::t2LDRSHi12:
363 case ARM::t2LDRSBi12:
384 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
385 unsigned FrameReg, int &Offset,
386 const ARMBaseInstrInfo &TII) {
387 unsigned Opcode = MI.getOpcode();
388 const MCInstrDesc &Desc = MI.getDesc();
389 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
392 // Memory operands in inline assembly always use AddrModeT2_i12.
393 if (Opcode == ARM::INLINEASM)
394 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
396 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
397 Offset += MI.getOperand(FrameRegIdx+1).getImm();
400 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
401 // Turn it into a move.
402 MI.setDesc(TII.get(ARM::tMOVr));
403 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
404 // Remove offset and remaining explicit predicate operands.
405 do MI.RemoveOperand(FrameRegIdx+1);
406 while (MI.getNumOperands() > FrameRegIdx+1);
407 MachineInstrBuilder MIB(&MI);
412 bool HasCCOut = Opcode != ARM::t2ADDri12;
417 MI.setDesc(TII.get(ARM::t2SUBri));
419 MI.setDesc(TII.get(ARM::t2ADDri));
422 // Common case: small offset, fits into instruction.
423 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
424 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
425 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
426 // Add cc_out operand if the original instruction did not have one.
428 MI.addOperand(MachineOperand::CreateReg(0, false));
432 // Another common case: imm12.
434 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
435 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
436 MI.setDesc(TII.get(NewOpc));
437 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
438 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
439 // Remove the cc_out operand.
441 MI.RemoveOperand(MI.getNumOperands()-1);
446 // Otherwise, extract 8 adjacent bits from the immediate into this
448 unsigned RotAmt = CountLeadingZeros_32(Offset);
449 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
451 // We will handle these bits from offset, clear them.
452 Offset &= ~ThisImmVal;
454 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
455 "Bit extraction didn't work?");
456 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
457 // Add cc_out operand if the original instruction did not have one.
459 MI.addOperand(MachineOperand::CreateReg(0, false));
463 // AddrMode4 and AddrMode6 cannot handle any offset.
464 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
467 // AddrModeT2_so cannot handle any offset. If there is no offset
468 // register then we change to an immediate version.
469 unsigned NewOpc = Opcode;
470 if (AddrMode == ARMII::AddrModeT2_so) {
471 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
472 if (OffsetReg != 0) {
473 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
477 MI.RemoveOperand(FrameRegIdx+1);
478 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
479 NewOpc = immediateOffsetOpcode(Opcode);
480 AddrMode = ARMII::AddrModeT2_i12;
483 unsigned NumBits = 0;
485 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
486 // i8 supports only negative, and i12 supports only positive, so
487 // based on Offset sign convert Opcode to the appropriate
489 Offset += MI.getOperand(FrameRegIdx+1).getImm();
491 NewOpc = negativeOffsetOpcode(Opcode);
496 NewOpc = positiveOffsetOpcode(Opcode);
499 } else if (AddrMode == ARMII::AddrMode5) {
501 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
502 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
503 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
507 Offset += InstrOffs * 4;
508 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
514 llvm_unreachable("Unsupported addressing mode!");
517 if (NewOpc != Opcode)
518 MI.setDesc(TII.get(NewOpc));
520 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
522 // Attempt to fold address computation
523 // Common case: small offset, fits into instruction.
524 int ImmedOffset = Offset / Scale;
525 unsigned Mask = (1 << NumBits) - 1;
526 if ((unsigned)Offset <= Mask * Scale) {
527 // Replace the FrameIndex with fp/sp
528 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
530 if (AddrMode == ARMII::AddrMode5)
531 // FIXME: Not consistent.
532 ImmedOffset |= 1 << NumBits;
534 ImmedOffset = -ImmedOffset;
536 ImmOp.ChangeToImmediate(ImmedOffset);
541 // Otherwise, offset doesn't fit. Pull in what we can to simplify
542 ImmedOffset = ImmedOffset & Mask;
544 if (AddrMode == ARMII::AddrMode5)
545 // FIXME: Not consistent.
546 ImmedOffset |= 1 << NumBits;
548 ImmedOffset = -ImmedOffset;
549 if (ImmedOffset == 0)
550 // Change the opcode back if the encoded offset is zero.
551 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
554 ImmOp.ChangeToImmediate(ImmedOffset);
555 Offset &= ~(Mask*Scale);
558 Offset = (isSub) ? -Offset : Offset;
562 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
563 /// two-addrss instruction inserted by two-address pass.
565 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
567 const TargetRegisterInfo &TRI) const {
568 if (SrcMI->getOpcode() != ARM::tMOVr || SrcMI->getOperand(1).isKill())
571 unsigned PredReg = 0;
572 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
573 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
576 // Schedule the copy so it doesn't come between previous instructions
577 // and UseMI which can form an IT block.
578 unsigned SrcReg = SrcMI->getOperand(1).getReg();
579 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
580 MachineBasicBlock *MBB = UseMI->getParent();
581 MachineBasicBlock::iterator MBBI = SrcMI;
582 unsigned NumInsts = 0;
583 while (--MBBI != MBB->begin()) {
584 if (MBBI->isDebugValue())
587 MachineInstr *NMI = &*MBBI;
588 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
589 if (!(NCC == CC || NCC == OCC) ||
590 NMI->modifiesRegister(SrcReg, &TRI) ||
591 NMI->definesRegister(ARM::CPSR))
594 // Too many in a row!
600 MBB->insert(++MBBI, SrcMI);
605 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
606 unsigned Opc = MI->getOpcode();
607 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
609 return llvm::getInstrPredicate(MI, PredReg);