1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "Thumb2InstrInfo.h"
29 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
30 : ARMBaseInstrInfo(STI), RI(*this, STI) {
33 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
39 Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
40 MachineBasicBlock::iterator I,
41 unsigned DestReg, unsigned SrcReg,
42 const TargetRegisterClass *DestRC,
43 const TargetRegisterClass *SrcRC,
45 if (DestRC == ARM::GPRRegisterClass) {
46 if (SrcRC == ARM::GPRRegisterClass) {
47 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
49 } else if (SrcRC == ARM::tGPRRegisterClass) {
50 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
53 } else if (DestRC == ARM::tGPRRegisterClass) {
54 if (SrcRC == ARM::GPRRegisterClass) {
55 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
57 } else if (SrcRC == ARM::tGPRRegisterClass) {
58 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
63 // Handle SPR, DPR, and QPR copies.
64 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC,
68 void Thumb2InstrInfo::
69 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
70 unsigned SrcReg, bool isKill, int FI,
71 const TargetRegisterClass *RC,
72 const TargetRegisterInfo *TRI) const {
73 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) {
75 if (I != MBB.end()) DL = I->getDebugLoc();
77 MachineFunction &MF = *MBB.getParent();
78 MachineFrameInfo &MFI = *MF.getFrameInfo();
79 MachineMemOperand *MMO =
80 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
81 MachineMemOperand::MOStore, 0,
82 MFI.getObjectSize(FI),
83 MFI.getObjectAlignment(FI));
84 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
85 .addReg(SrcReg, getKillRegState(isKill))
86 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
90 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
93 void Thumb2InstrInfo::
94 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
95 unsigned DestReg, int FI,
96 const TargetRegisterClass *RC,
97 const TargetRegisterInfo *TRI) const {
98 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) {
100 if (I != MBB.end()) DL = I->getDebugLoc();
102 MachineFunction &MF = *MBB.getParent();
103 MachineFrameInfo &MFI = *MF.getFrameInfo();
104 MachineMemOperand *MMO =
105 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
106 MachineMemOperand::MOLoad, 0,
107 MFI.getObjectSize(FI),
108 MFI.getObjectAlignment(FI));
109 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
110 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
114 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
117 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
118 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
119 unsigned DestReg, unsigned BaseReg, int NumBytes,
120 ARMCC::CondCodes Pred, unsigned PredReg,
121 const ARMBaseInstrInfo &TII) {
122 bool isSub = NumBytes < 0;
123 if (isSub) NumBytes = -NumBytes;
125 // If profitable, use a movw or movt to materialize the offset.
126 // FIXME: Use the scavenger to grab a scratch register.
127 if (DestReg != ARM::SP && DestReg != BaseReg &&
129 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
131 if (NumBytes < 65536) {
132 // Use a movw to materialize the 16-bit constant.
133 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
135 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
137 } else if ((NumBytes & 0xffff) == 0) {
138 // Use a movt to materialize the 32-bit constant.
139 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
141 .addImm(NumBytes >> 16)
142 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
148 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
149 .addReg(BaseReg, RegState::Kill)
150 .addReg(DestReg, RegState::Kill)
151 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
153 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
154 .addReg(DestReg, RegState::Kill)
155 .addReg(BaseReg, RegState::Kill)
156 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
163 unsigned ThisVal = NumBytes;
165 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
166 // mov sp, rn. Note t2MOVr cannot be used.
167 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg).addReg(BaseReg);
172 bool HasCCOut = true;
173 if (BaseReg == ARM::SP) {
175 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
176 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
177 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
178 // FIXME: Fix Thumb1 immediate encoding.
179 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
180 .addReg(BaseReg).addImm(ThisVal/4);
185 // sub rd, sp, so_imm
186 Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
187 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
190 // FIXME: Move this to ARMAddressingModes.h?
191 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
192 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
193 NumBytes &= ~ThisVal;
194 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
195 "Bit extraction didn't work?");
198 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
199 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
200 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
202 } else if (ThisVal < 4096) {
203 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
207 // FIXME: Move this to ARMAddressingModes.h?
208 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
209 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
210 NumBytes &= ~ThisVal;
211 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
212 "Bit extraction didn't work?");
216 // Build the new ADD / SUB.
217 MachineInstrBuilder MIB =
218 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
219 .addReg(BaseReg, RegState::Kill)
229 negativeOffsetOpcode(unsigned opcode)
232 case ARM::t2LDRi12: return ARM::t2LDRi8;
233 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
234 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
235 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
236 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
237 case ARM::t2STRi12: return ARM::t2STRi8;
238 case ARM::t2STRBi12: return ARM::t2STRBi8;
239 case ARM::t2STRHi12: return ARM::t2STRHi8;
259 positiveOffsetOpcode(unsigned opcode)
262 case ARM::t2LDRi8: return ARM::t2LDRi12;
263 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
264 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
265 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
266 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
267 case ARM::t2STRi8: return ARM::t2STRi12;
268 case ARM::t2STRBi8: return ARM::t2STRBi12;
269 case ARM::t2STRHi8: return ARM::t2STRHi12;
274 case ARM::t2LDRSHi12:
275 case ARM::t2LDRSBi12:
289 immediateOffsetOpcode(unsigned opcode)
292 case ARM::t2LDRs: return ARM::t2LDRi12;
293 case ARM::t2LDRHs: return ARM::t2LDRHi12;
294 case ARM::t2LDRBs: return ARM::t2LDRBi12;
295 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
296 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
297 case ARM::t2STRs: return ARM::t2STRi12;
298 case ARM::t2STRBs: return ARM::t2STRBi12;
299 case ARM::t2STRHs: return ARM::t2STRHi12;
304 case ARM::t2LDRSHi12:
305 case ARM::t2LDRSBi12:
326 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
327 unsigned FrameReg, int &Offset,
328 const ARMBaseInstrInfo &TII) {
329 unsigned Opcode = MI.getOpcode();
330 const TargetInstrDesc &Desc = MI.getDesc();
331 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
334 // Memory operands in inline assembly always use AddrModeT2_i12.
335 if (Opcode == ARM::INLINEASM)
336 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
338 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
339 Offset += MI.getOperand(FrameRegIdx+1).getImm();
342 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
343 // Turn it into a move.
344 MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
345 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
346 // Remove offset and remaining explicit predicate operands.
347 do MI.RemoveOperand(FrameRegIdx+1);
348 while (MI.getNumOperands() > FrameRegIdx+1 &&
349 (!MI.getOperand(FrameRegIdx+1).isReg() ||
350 !MI.getOperand(FrameRegIdx+1).isImm()));
354 bool isSP = FrameReg == ARM::SP;
355 bool HasCCOut = Opcode != ARM::t2ADDri12;
360 MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
362 MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
365 // Common case: small offset, fits into instruction.
366 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
367 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
368 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
369 // Add cc_out operand if the original instruction did not have one.
371 MI.addOperand(MachineOperand::CreateReg(0, false));
375 // Another common case: imm12.
377 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
378 unsigned NewOpc = isSP
379 ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
380 : (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12);
381 MI.setDesc(TII.get(NewOpc));
382 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
383 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
384 // Remove the cc_out operand.
386 MI.RemoveOperand(MI.getNumOperands()-1);
391 // Otherwise, extract 8 adjacent bits from the immediate into this
393 unsigned RotAmt = CountLeadingZeros_32(Offset);
394 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
396 // We will handle these bits from offset, clear them.
397 Offset &= ~ThisImmVal;
399 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
400 "Bit extraction didn't work?");
401 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
402 // Add cc_out operand if the original instruction did not have one.
404 MI.addOperand(MachineOperand::CreateReg(0, false));
408 // AddrMode4 and AddrMode6 cannot handle any offset.
409 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
412 // AddrModeT2_so cannot handle any offset. If there is no offset
413 // register then we change to an immediate version.
414 unsigned NewOpc = Opcode;
415 if (AddrMode == ARMII::AddrModeT2_so) {
416 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
417 if (OffsetReg != 0) {
418 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
422 MI.RemoveOperand(FrameRegIdx+1);
423 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
424 NewOpc = immediateOffsetOpcode(Opcode);
425 AddrMode = ARMII::AddrModeT2_i12;
428 unsigned NumBits = 0;
430 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
431 // i8 supports only negative, and i12 supports only positive, so
432 // based on Offset sign convert Opcode to the appropriate
434 Offset += MI.getOperand(FrameRegIdx+1).getImm();
436 NewOpc = negativeOffsetOpcode(Opcode);
441 NewOpc = positiveOffsetOpcode(Opcode);
444 } else if (AddrMode == ARMII::AddrMode5) {
446 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
447 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
448 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
452 Offset += InstrOffs * 4;
453 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
459 llvm_unreachable("Unsupported addressing mode!");
462 if (NewOpc != Opcode)
463 MI.setDesc(TII.get(NewOpc));
465 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
467 // Attempt to fold address computation
468 // Common case: small offset, fits into instruction.
469 int ImmedOffset = Offset / Scale;
470 unsigned Mask = (1 << NumBits) - 1;
471 if ((unsigned)Offset <= Mask * Scale) {
472 // Replace the FrameIndex with fp/sp
473 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
475 if (AddrMode == ARMII::AddrMode5)
476 // FIXME: Not consistent.
477 ImmedOffset |= 1 << NumBits;
479 ImmedOffset = -ImmedOffset;
481 ImmOp.ChangeToImmediate(ImmedOffset);
486 // Otherwise, offset doesn't fit. Pull in what we can to simplify
487 ImmedOffset = ImmedOffset & Mask;
489 if (AddrMode == ARMII::AddrMode5)
490 // FIXME: Not consistent.
491 ImmedOffset |= 1 << NumBits;
493 ImmedOffset = -ImmedOffset;
494 if (ImmedOffset == 0)
495 // Change the opcode back if the encoded offset is zero.
496 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
499 ImmOp.ChangeToImmediate(ImmedOffset);
500 Offset &= ~(Mask*Scale);
503 Offset = (isSub) ? -Offset : Offset;