lib/Target/ARM/Thumb1InstrInfo.h

   1 //===- Thumb1InstrInfo.h - Thumb-1 Instruction Information ------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef THUMB1INSTRUCTIONINFO_H
  15 #define THUMB1INSTRUCTIONINFO_H
  16
  17 #include "llvm/Target/TargetInstrInfo.h"
  18 #include "ARM.h"
  19 #include "ARMInstrInfo.h"
  20 #include "Thumb1RegisterInfo.h"
  21
  22 namespace llvm {
  23   class ARMSubtarget;
  24
  25 class Thumb1InstrInfo : public ARMBaseInstrInfo {
  26   Thumb1RegisterInfo RI;
  27 public:
  28   explicit Thumb1InstrInfo(const ARMSubtarget &STI);
  29
  30   // Return the non-pre/post incrementing version of 'Opc'. Return 0
  31   // if there is not such an opcode.
  32   unsigned getUnindexedOpcode(unsigned Opc) const;
  33
  34   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  35   /// such, whenever a client has an instance of instruction info, it should
  36   /// always be able to get register info as well (through this method).
  37   ///
  38   const Thumb1RegisterInfo &getRegisterInfo() const { return RI; }
  39
  40   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
  41                                  MachineBasicBlock::iterator MI,
  42                                  const std::vector<CalleeSavedInfo> &CSI,
  43                                  const TargetRegisterInfo *TRI) const;
  44   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
  45                                    MachineBasicBlock::iterator MI,
  46                                    const std::vector<CalleeSavedInfo> &CSI,
  47                                    const TargetRegisterInfo *TRI) const;
  48
  49   bool copyRegToReg(MachineBasicBlock &MBB,
  50                             MachineBasicBlock::iterator I,
  51                             unsigned DestReg, unsigned SrcReg,
  52                             const TargetRegisterClass *DestRC,
  53                             const TargetRegisterClass *SrcRC,
  54                             DebugLoc DL) const;
  55   void storeRegToStackSlot(MachineBasicBlock &MBB,
  56                                    MachineBasicBlock::iterator MBBI,
  57                                    unsigned SrcReg, bool isKill, int FrameIndex,
  58                            const TargetRegisterClass *RC,
  59                            const TargetRegisterInfo *TRI) const;
  60
  61   void loadRegFromStackSlot(MachineBasicBlock &MBB,
  62                                     MachineBasicBlock::iterator MBBI,
  63                                     unsigned DestReg, int FrameIndex,
  64                             const TargetRegisterClass *RC,
  65                             const TargetRegisterInfo *TRI) const;
  66
  67   bool canFoldMemoryOperand(const MachineInstr *MI,
  68                                     const SmallVectorImpl<unsigned> &Ops) const;
  69
  70   MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
  71                                       MachineInstr* MI,
  72                                       const SmallVectorImpl<unsigned> &Ops,
  73                                       int FrameIndex) const;
  74
  75   MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
  76                                       MachineInstr* MI,
  77                                       const SmallVectorImpl<unsigned> &Ops,
  78                                       MachineInstr* LoadMI) const {
  79     return 0;
  80   }
  81 };
  82 }
  83
  84 #endif // THUMB1INSTRUCTIONINFO_H