1 //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb1InstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "Thumb1InstrInfo.h"
28 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
29 : ARMBaseInstrInfo(STI), RI(*this, STI) {
32 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
36 bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
37 MachineBasicBlock::iterator I,
38 unsigned DestReg, unsigned SrcReg,
39 const TargetRegisterClass *DestRC,
40 const TargetRegisterClass *SrcRC,
42 if (DestRC == ARM::GPRRegisterClass) {
43 if (SrcRC == ARM::GPRRegisterClass) {
44 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
46 } else if (SrcRC == ARM::tGPRRegisterClass) {
47 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
50 } else if (DestRC == ARM::tGPRRegisterClass) {
51 if (SrcRC == ARM::GPRRegisterClass) {
52 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
54 } else if (SrcRC == ARM::tGPRRegisterClass) {
55 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
63 bool Thumb1InstrInfo::
64 canFoldMemoryOperand(const MachineInstr *MI,
65 const SmallVectorImpl<unsigned> &Ops) const {
66 if (Ops.size() != 1) return false;
68 unsigned OpNum = Ops[0];
69 unsigned Opc = MI->getOpcode();
73 case ARM::tMOVtgpr2gpr:
74 case ARM::tMOVgpr2tgpr:
75 case ARM::tMOVgpr2gpr: {
76 if (OpNum == 0) { // move -> store
77 unsigned SrcReg = MI->getOperand(1).getReg();
78 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
79 !isARMLowRegister(SrcReg))
80 // tSpill cannot take a high register operand.
82 } else { // move -> load
83 unsigned DstReg = MI->getOperand(0).getReg();
84 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
85 !isARMLowRegister(DstReg))
86 // tRestore cannot target a high register operand.
96 void Thumb1InstrInfo::
97 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
98 unsigned SrcReg, bool isKill, int FI,
99 const TargetRegisterClass *RC,
100 const TargetRegisterInfo *TRI) const {
101 assert((RC == ARM::tGPRRegisterClass ||
102 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
103 isARMLowRegister(SrcReg))) && "Unknown regclass!");
105 if (RC == ARM::tGPRRegisterClass ||
106 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
107 isARMLowRegister(SrcReg))) {
109 if (I != MBB.end()) DL = I->getDebugLoc();
111 MachineFunction &MF = *MBB.getParent();
112 MachineFrameInfo &MFI = *MF.getFrameInfo();
113 MachineMemOperand *MMO =
114 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
115 MachineMemOperand::MOStore, 0,
116 MFI.getObjectSize(FI),
117 MFI.getObjectAlignment(FI));
118 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
119 .addReg(SrcReg, getKillRegState(isKill))
120 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
124 void Thumb1InstrInfo::
125 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
126 unsigned DestReg, int FI,
127 const TargetRegisterClass *RC,
128 const TargetRegisterInfo *TRI) const {
129 assert((RC == ARM::tGPRRegisterClass ||
130 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
131 isARMLowRegister(DestReg))) && "Unknown regclass!");
133 if (RC == ARM::tGPRRegisterClass ||
134 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
135 isARMLowRegister(DestReg))) {
137 if (I != MBB.end()) DL = I->getDebugLoc();
139 MachineFunction &MF = *MBB.getParent();
140 MachineFrameInfo &MFI = *MF.getFrameInfo();
141 MachineMemOperand *MMO =
142 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
143 MachineMemOperand::MOLoad, 0,
144 MFI.getObjectSize(FI),
145 MFI.getObjectAlignment(FI));
146 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
147 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
151 bool Thumb1InstrInfo::
152 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
153 MachineBasicBlock::iterator MI,
154 const std::vector<CalleeSavedInfo> &CSI,
155 const TargetRegisterInfo *TRI) const {
160 if (MI != MBB.end()) DL = MI->getDebugLoc();
162 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
164 for (unsigned i = CSI.size(); i != 0; --i) {
165 unsigned Reg = CSI[i-1].getReg();
168 // Add the callee-saved register as live-in unless it's LR and
169 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
170 // then it's already added to the function and entry block live-in sets.
171 if (Reg == ARM::LR) {
172 MachineFunction &MF = *MBB.getParent();
173 if (MF.getFrameInfo()->isReturnAddressTaken() &&
174 MF.getRegInfo().isLiveIn(Reg))
180 MIB.addReg(Reg, RegState::Kill);
186 bool Thumb1InstrInfo::
187 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
188 MachineBasicBlock::iterator MI,
189 const std::vector<CalleeSavedInfo> &CSI,
190 const TargetRegisterInfo *TRI) const {
191 MachineFunction &MF = *MBB.getParent();
192 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
196 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
197 DebugLoc DL = MI->getDebugLoc();
198 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
201 bool NumRegs = false;
202 for (unsigned i = CSI.size(); i != 0; --i) {
203 unsigned Reg = CSI[i-1].getReg();
204 if (Reg == ARM::LR) {
205 // Special epilogue for vararg functions. See emitEpilogue
209 (*MIB).setDesc(get(ARM::tPOP_RET));
212 MIB.addReg(Reg, getDefRegState(true));
216 // It's illegal to emit pop instruction without operands.
218 MBB.insert(MI, &*MIB);
220 MF.DeleteMachineInstr(MIB);
225 MachineInstr *Thumb1InstrInfo::
226 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
227 const SmallVectorImpl<unsigned> &Ops, int FI) const {
228 if (Ops.size() != 1) return NULL;
230 unsigned OpNum = Ops[0];
231 unsigned Opc = MI->getOpcode();
232 MachineInstr *NewMI = NULL;
236 case ARM::tMOVtgpr2gpr:
237 case ARM::tMOVgpr2tgpr:
238 case ARM::tMOVgpr2gpr: {
239 if (OpNum == 0) { // move -> store
240 unsigned SrcReg = MI->getOperand(1).getReg();
241 bool isKill = MI->getOperand(1).isKill();
242 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
243 !isARMLowRegister(SrcReg))
244 // tSpill cannot take a high register operand.
246 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
247 .addReg(SrcReg, getKillRegState(isKill))
248 .addFrameIndex(FI).addImm(0));
249 } else { // move -> load
250 unsigned DstReg = MI->getOperand(0).getReg();
251 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
252 !isARMLowRegister(DstReg))
253 // tRestore cannot target a high register operand.
255 bool isDead = MI->getOperand(0).isDead();
256 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
258 RegState::Define | getDeadRegState(isDead))
259 .addFrameIndex(FI).addImm(0));