1 //===---------------------------------------------------------------------===//
2 // Random ideas for the ARM backend.
3 //===---------------------------------------------------------------------===//
5 Reimplement 'select' in terms of 'SEL'.
7 * We would really like to support UXTAB16, but we need to prove that the
8 add doesn't need to overflow between the two 16-bit chunks.
10 * implement predication support
11 * Implement pre/post increment support. (e.g. PR935)
12 * Coalesce stack slots!
13 * Implement smarter constant generation for binops with large immediates.
15 * Consider materializing FP constants like 0.0f and 1.0f using integer
16 immediate instructions then copy to FPU. Slower than load into FPU?
18 //===---------------------------------------------------------------------===//
20 The constant island pass has been much improved; all the todo items in the
21 previous version of this document have been addressed. However, there are still
22 things that can be done:
24 1. When there isn't an existing water, the current MBB is split right after
25 the use. It would be profitable to look farther forward, especially on Thumb,
26 where negative offsets won't work.
27 Now it will put the island at the end of the block if that is in range. If it
28 is not in range things still work as above, which is poor on Thumb.
30 2. There may be some advantage to trying to be smarter about the initial
31 placement, rather than putting everything at the end.
33 3. The handling of 2-byte padding for Thumb is overly conservative. There
34 would be a small gain to keeping accurate track of the padding (which would
35 require aligning functions containing constant pools to 4-byte boundaries).
37 //===---------------------------------------------------------------------===//
39 We need to start generating predicated instructions. The .td files have a way
40 to express this now (see the PPC conditional return instruction), but the
41 branch folding pass (or a new if-cvt pass) should start producing these, at
42 least in the trivial case.
44 Among the obvious wins, doing so can eliminate the need to custom expand
45 copysign (i.e. we won't need to custom expand it to get the conditional
48 This allows us to eliminate one instruction from:
50 define i32 @_Z6slow4bii(i32 %x, i32 %y) {
51 %tmp = icmp sgt i32 %x, %y
52 %retval = select i1 %tmp, i32 %x, i32 %y
62 //===---------------------------------------------------------------------===//
64 Implement long long "X-3" with instructions that fold the immediate in. These
65 were disabled due to badness with the ARM carry flag on subtracts.
67 //===---------------------------------------------------------------------===//
69 We currently compile abs:
70 int foo(int p) { return p < 0 ? -p : p; }
81 This is very, uh, literal. This could be a 3 operation sequence:
85 Which would be better. This occurs in png decode.
87 //===---------------------------------------------------------------------===//
89 More load / store optimizations:
90 1) Look past instructions without side-effects (not load, store, branch, etc.)
91 when forming the list of loads / stores to optimize.
93 2) Smarter register allocation?
94 We are probably missing some opportunities to use ldm / stm. Consider:
99 This cannot be merged into a ldm. Perhaps we will need to do the transformation
100 before register allocation. Then teach the register allocator to allocate a
101 chunk of consecutive registers.
103 3) Better representation for block transfer? This is from Olden/power:
114 If we can spare the registers, it would be better to use fldm and fstm here.
115 Need major register allocator enhancement though.
117 4) Can we recognize the relative position of constantpool entries? i.e. Treat
128 Then the ldr's can be combined into a single ldm. See Olden/power.
130 Note for ARM v4 gcc uses ldmia to load a pair of 32-bit values to represent a
131 double 64-bit FP constant:
141 5) Can we make use of ldrd and strd? Instead of generating ldm / stm, use
142 ldrd/strd instead if there are only two destination registers that form an
143 odd/even pair. However, we probably would pay a penalty if the address is not
144 aligned on 8-byte boundary. This requires more information on load / store
145 nodes (and MI's?) then we currently carry.
147 //===---------------------------------------------------------------------===//
149 * Consider this silly example:
151 double bar(double x) {
176 Ignore the prologue and epilogue stuff for a second. Note
179 the copys to callee-save registers and the fact they are only being used by the
180 fmdrr instruction. It would have been better had the fmdrr been scheduled
181 before the call and place the result in a callee-save DPR register. The two
182 mov ops would not have been necessary.
184 //===---------------------------------------------------------------------===//
186 Calling convention related stuff:
188 * gcc's parameter passing implementation is terrible and we suffer as a result:
196 void foo(struct s S) {
197 printf("%g, %d\n", S.d1, S.s1);
200 'S' is passed via registers r0, r1, r2. But gcc stores them to the stack, and
201 then reload them to r1, r2, and r3 before issuing the call (r0 contains the
202 address of the format string):
207 stmia sp, {r0, r1, r2}
215 Instead of a stmia, ldmia, and a ldr, wouldn't it be better to do three moves?
217 * Return an aggregate type is even worse:
221 struct s S = {1.1, 2};
230 @ lr needed for prologue
231 ldmia r0, {r0, r1, r2}
232 stmia sp, {r0, r1, r2}
233 stmia ip, {r0, r1, r2}
238 r0 (and later ip) is the hidden parameter from caller to store the value in. The
239 first ldmia loads the constants into r0, r1, r2. The last stmia stores r0, r1,
240 r2 into the address passed in. However, there is one additional stmia that
241 stores r0, r1, and r2 to some stack location. The store is dead.
243 The llvm-gcc generated code looks like this:
245 csretcc void %foo(%struct.s* %agg.result) {
247 %S = alloca %struct.s, align 4 ; <%struct.s*> [#uses=1]
248 %memtmp = alloca %struct.s ; <%struct.s*> [#uses=1]
249 cast %struct.s* %S to sbyte* ; <sbyte*>:0 [#uses=2]
250 call void %llvm.memcpy.i32( sbyte* %0, sbyte* cast ({ double, int }* %C.0.904 to sbyte*), uint 12, uint 4 )
251 cast %struct.s* %agg.result to sbyte* ; <sbyte*>:1 [#uses=2]
252 call void %llvm.memcpy.i32( sbyte* %1, sbyte* %0, uint 12, uint 0 )
253 cast %struct.s* %memtmp to sbyte* ; <sbyte*>:2 [#uses=1]
254 call void %llvm.memcpy.i32( sbyte* %2, sbyte* %1, uint 12, uint 0 )
258 llc ends up issuing two memcpy's (the first memcpy becomes 3 loads from
259 constantpool). Perhaps we should 1) fix llvm-gcc so the memcpy is translated
260 into a number of load and stores, or 2) custom lower memcpy (of small size) to
261 be ldmia / stmia. I think option 2 is better but the current register
262 allocator cannot allocate a chunk of registers at a time.
264 A feasible temporary solution is to use specific physical registers at the
265 lowering time for small (<= 4 words?) transfer size.
267 * ARM CSRet calling convention requires the hidden argument to be returned by
270 //===---------------------------------------------------------------------===//
272 We can definitely do a better job on BB placements to eliminate some branches.
273 It's very common to see llvm generated assembly code that looks like this:
282 If BB4 is the only predecessor of BB3, then we can emit BB3 after BB4. We can
283 then eliminate beq and and turn the unconditional branch to LBB2 to a bne.
285 See McCat/18-imp/ComputeBoundingBoxes for an example.
287 //===---------------------------------------------------------------------===//
289 We need register scavenging. Currently, the 'ip' register is reserved in case
290 frame indexes are too big. This means that we generate extra code for stuff
293 void foo(unsigned x, unsigned y, unsigned z, unsigned *a, unsigned *b, unsigned *c) {
294 short Rconst = (short) (16384.0f * 1.40200 + 0.5 );
303 *** stmfd sp!, {r4, r7}
306 orr r4, r4, #89, 24 @ 22784
316 *** ldmfd sp!, {r4, r7}
335 This is apparently all because we couldn't use ip here.
337 //===---------------------------------------------------------------------===//
339 Pre-/post- indexed load / stores:
341 1) We should not make the pre/post- indexed load/store transform if the base ptr
342 is guaranteed to be live beyond the load/store. This can happen if the base
343 ptr is live out of the block we are performing the optimization. e.g.
355 In most cases, this is just a wasted optimization. However, sometimes it can
356 negatively impact the performance because two-address code is more restrictive
357 when it comes to scheduling.
359 Unfortunately, liveout information is currently unavailable during DAG combine
362 2) Consider spliting a indexed load / store into a pair of add/sub + load/store
363 to solve #1 (in TwoAddressInstructionPass.cpp).
365 3) Enhance LSR to generate more opportunities for indexed ops.
367 4) Once we added support for multiple result patterns, write indexed loads
368 patterns instead of C++ instruction selection code.
370 5) Use FLDM / FSTM to emulate indexed FP load / store.
372 //===---------------------------------------------------------------------===//
374 We should add i64 support to take advantage of the 64-bit load / stores.
375 We can add a pseudo i64 register class containing pseudo registers that are
376 register pairs. All other ops (e.g. add, sub) would be expanded as usual.
378 We need to add pseudo instructions (i.e. gethi / getlo) to extract i32 registers
379 from the i64 register. These are single moves which can be eliminated if the
380 destination register is a sub-register of the source. We should implement proper
381 subreg support in the register allocator to coalesce these away.
383 There are other minor issues such as multiple instructions for a spill / restore
386 //===---------------------------------------------------------------------===//
388 Implement support for some more tricky ways to materialize immediates. For
389 example, to get 0xffff8000, we can use:
394 //===---------------------------------------------------------------------===//
396 We sometimes generate multiple add / sub instructions to update sp in prologue
397 and epilogue if the inc / dec value is too large to fit in a single immediate
398 operand. In some cases, perhaps it might be better to load the value from a
399 constantpool instead.
401 //===---------------------------------------------------------------------===//
403 GCC generates significantly better code for this function.
405 int foo(int StackPtr, unsigned char *Line, unsigned char *Stack, int LineLen) {
409 while (StackPtr != 0 && i < (((LineLen) < (32768))? (LineLen) : (32768)))
410 Line[i++] = Stack[--StackPtr];
413 while (StackPtr != 0 && i < LineLen)
423 //===---------------------------------------------------------------------===//
425 This should compile to the mlas instruction:
426 int mlas(int x, int y, int z) { return ((x * y + z) < 0) ? 7 : 13; }
428 //===---------------------------------------------------------------------===//
430 At some point, we should triage these to see if they still apply to us:
432 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19598
433 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=18560
434 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=27016
436 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11831
437 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11826
438 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11825
439 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11824
440 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11823
441 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11820
442 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=10982
444 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=10242
445 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9831
446 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9760
447 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9759
448 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9703
449 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9702
450 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9663
452 http://www.inf.u-szeged.hu/gcc-arm/
453 http://citeseer.ist.psu.edu/debus04linktime.html
455 //===---------------------------------------------------------------------===//