1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides ARM specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
15 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
17 #include "llvm/Support/DataTypes.h"
21 class formatted_raw_ostream;
29 class MCSubtargetInfo;
31 class MCRelocationInfo;
32 class MCTargetStreamer;
38 extern Target TheARMLETarget, TheThumbLETarget;
39 extern Target TheARMBETarget, TheThumbBETarget;
42 std::string ParseARMTriple(StringRef TT, StringRef CPU);
44 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
45 /// do not need to go through TargetRegistry.
46 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
50 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
51 MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
52 formatted_raw_ostream &OS,
53 MCInstPrinter *InstPrint,
55 MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
56 const MCSubtargetInfo &STI);
58 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
59 const MCRegisterInfo &MRI,
62 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
63 const MCRegisterInfo &MRI,
66 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
67 StringRef TT, StringRef CPU,
70 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
71 StringRef TT, StringRef CPU);
73 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
74 StringRef TT, StringRef CPU);
76 MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
77 StringRef TT, StringRef CPU);
79 MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
80 StringRef TT, StringRef CPU);
82 // Construct a PE/COFF machine code streamer which will generate a PE/COFF
84 MCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB,
85 raw_ostream &OS, MCCodeEmitter *Emitter,
88 /// Construct an ELF Mach-O object writer.
89 MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS,
93 /// Construct an ARM Mach-O object writer.
94 MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
99 /// Construct an ARM PE/COFF object writer.
100 MCObjectWriter *createARMWinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit);
102 /// Construct ARM Mach-O relocation info.
103 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
104 } // End llvm namespace
106 // Defines symbolic names for ARM registers. This defines a mapping from
107 // register name to register number.
109 #define GET_REGINFO_ENUM
110 #include "ARMGenRegisterInfo.inc"
112 // Defines symbolic names for the ARM instructions.
114 #define GET_INSTRINFO_ENUM
115 #include "ARMGenInstrInfo.inc"
117 #define GET_SUBTARGETINFO_ENUM
118 #include "ARMGenSubtargetInfo.inc"