1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides ARM specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInfo.h"
15 #include "ARMMCAsmInfo.h"
16 #include "ARMMCTargetDesc.h"
17 #include "InstPrinter/ARMInstPrinter.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCELFStreamer.h"
21 #include "llvm/MC/MCInstrAnalysis.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
30 #define GET_REGINFO_MC_DESC
31 #include "ARMGenRegisterInfo.inc"
33 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
35 if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
36 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
37 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
38 // Checks for the deprecated CP15ISB encoding:
39 // mcr p15, #0, rX, c7, c5, #4
40 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
41 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
42 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
43 Info = "deprecated since v7, use 'isb'";
47 // Checks for the deprecated CP15DSB encoding:
48 // mcr p15, #0, rX, c7, c10, #4
49 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
50 Info = "deprecated since v7, use 'dsb'";
54 // Checks for the deprecated CP15DMB encoding:
55 // mcr p15, #0, rX, c7, c10, #5
56 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
57 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
58 Info = "deprecated since v7, use 'dmb'";
65 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
67 if (STI.getFeatureBits() & llvm::ARM::HasV8Ops &&
68 MI.getOperand(1).isImm() && MI.getOperand(1).getImm() != 8) {
69 Info = "applying IT instruction to more than one subsequent instruction is deprecated";
76 #define GET_INSTRINFO_MC_DESC
77 #include "ARMGenInstrInfo.inc"
79 #define GET_SUBTARGETINFO_MC_DESC
80 #include "ARMGenSubtargetInfo.inc"
83 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
86 // Set the boolean corresponding to the current target triple, or the default
87 // if one cannot be determined, to true.
88 unsigned Len = TT.size();
91 // FIXME: Enhance Triple helper class to extract ARM version.
92 bool isThumb = triple.getArch() == Triple::thumb ||
93 triple.getArch() == Triple::thumbeb;
94 if (Len >= 5 && TT.substr(0, 4) == "armv")
96 else if (Len >= 7 && TT.substr(0, 6) == "armebv")
98 else if (Len >= 7 && TT.substr(0, 6) == "thumbv")
100 else if (Len >= 9 && TT.substr(0, 8) == "thumbebv")
103 bool NoCPU = CPU == "generic" || CPU.empty();
104 std::string ARMArchFeature;
106 unsigned SubVer = TT[Idx];
109 // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
110 // FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
111 // FeatureT2XtPk, FeatureCrypto, FeatureCRC
112 ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
113 "+trustzone,+t2xtpk,+crypto,+crc";
115 // Use CPU to figure out the exact features
116 ARMArchFeature = "+v8";
117 } else if (SubVer == '7') {
118 if (Len >= Idx+2 && TT[Idx+1] == 'm') {
121 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
122 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
124 // Use CPU to figure out the exact features.
125 ARMArchFeature = "+v7";
126 } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
128 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
129 // FeatureT2XtPk, FeatureMClass
130 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
132 // Use CPU to figure out the exact features.
133 ARMArchFeature = "+v7";
134 } else if (Len >= Idx+2 && TT[Idx+1] == 's') {
136 // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
138 ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
140 // Use CPU to figure out the exact features.
141 ARMArchFeature = "+v7";
143 // v7 CPUs have lots of different feature sets. If no CPU is specified,
144 // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
145 // the "minimum" feature set and use CPU string to figure out the exact
148 // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
149 ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
151 // Use CPU to figure out the exact features.
152 ARMArchFeature = "+v7";
154 } else if (SubVer == '6') {
155 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
156 ARMArchFeature = "+v6t2";
157 else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
160 // v6m: FeatureNoARM, FeatureMClass
161 ARMArchFeature = "+v6m,+noarm,+mclass";
163 ARMArchFeature = "+v6";
165 ARMArchFeature = "+v6";
166 } else if (SubVer == '5') {
167 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
168 ARMArchFeature = "+v5te";
170 ARMArchFeature = "+v5t";
171 } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
172 ARMArchFeature = "+v4t";
176 if (ARMArchFeature.empty())
177 ARMArchFeature = "+thumb-mode";
179 ARMArchFeature += ",+thumb-mode";
182 if (triple.isOSNaCl()) {
183 if (ARMArchFeature.empty())
184 ARMArchFeature = "+nacl-trap";
186 ARMArchFeature += ",+nacl-trap";
189 return ARMArchFeature;
192 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
194 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
197 ArchFS = ArchFS + "," + FS.str();
202 MCSubtargetInfo *X = new MCSubtargetInfo();
203 InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
207 static MCInstrInfo *createARMMCInstrInfo() {
208 MCInstrInfo *X = new MCInstrInfo();
209 InitARMMCInstrInfo(X);
213 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
214 MCRegisterInfo *X = new MCRegisterInfo();
215 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
219 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
220 Triple TheTriple(TT);
223 switch (TheTriple.getOS()) {
224 case llvm::Triple::Darwin:
225 case llvm::Triple::IOS:
226 case llvm::Triple::MacOSX:
227 MAI = new ARMMCAsmInfoDarwin(TT);
229 case llvm::Triple::Win32:
230 switch (TheTriple.getEnvironment()) {
231 case llvm::Triple::Itanium:
232 MAI = new ARMCOFFMCAsmInfoGNU();
234 case llvm::Triple::MSVC:
235 MAI = new ARMCOFFMCAsmInfoMicrosoft();
238 llvm_unreachable("invalid environment");
242 if (TheTriple.isOSBinFormatMachO())
243 MAI = new ARMMCAsmInfoDarwin(TT);
245 MAI = new ARMELFMCAsmInfo(TT);
249 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
250 MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(0, Reg, 0));
255 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
257 CodeGenOpt::Level OL) {
258 MCCodeGenInfo *X = new MCCodeGenInfo();
259 if (RM == Reloc::Default) {
260 Triple TheTriple(TT);
261 // Default relocation model on Darwin is PIC, not DynamicNoPIC.
262 RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
264 X->InitMCCodeGenInfo(RM, CM, OL);
268 // This is duplicated code. Refactor this.
269 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
270 MCContext &Ctx, MCAsmBackend &MAB,
272 MCCodeEmitter *Emitter,
273 const MCSubtargetInfo &STI,
276 Triple TheTriple(TT);
278 if (TheTriple.isOSBinFormatMachO()) {
279 MCStreamer *S = createMachOStreamer(Ctx, MAB, OS, Emitter, false);
280 new ARMTargetStreamer(*S);
284 if (TheTriple.isOSWindows()) {
285 llvm_unreachable("ARM does not support Windows COFF format");
288 return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack,
289 TheTriple.getArch() == Triple::thumb);
292 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
293 unsigned SyntaxVariant,
294 const MCAsmInfo &MAI,
295 const MCInstrInfo &MII,
296 const MCRegisterInfo &MRI,
297 const MCSubtargetInfo &STI) {
298 if (SyntaxVariant == 0)
299 return new ARMInstPrinter(MAI, MII, MRI, STI);
303 static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
305 Triple TheTriple(TT);
306 if (TheTriple.isOSBinFormatMachO())
307 return createARMMachORelocationInfo(Ctx);
308 // Default to the stock relocation info.
309 return llvm::createMCRelocationInfo(TT, Ctx);
314 class ARMMCInstrAnalysis : public MCInstrAnalysis {
316 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
318 bool isUnconditionalBranch(const MCInst &Inst) const override {
319 // BCCs with the "always" predicate are unconditional branches.
320 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
322 return MCInstrAnalysis::isUnconditionalBranch(Inst);
325 bool isConditionalBranch(const MCInst &Inst) const override {
326 // BCCs with the "always" predicate are unconditional branches.
327 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
329 return MCInstrAnalysis::isConditionalBranch(Inst);
332 bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
333 uint64_t Size, uint64_t &Target) const override {
334 // We only handle PCRel branches for now.
335 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
338 int64_t Imm = Inst.getOperand(0).getImm();
339 // FIXME: This is not right for thumb.
340 Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
347 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
348 return new ARMMCInstrAnalysis(Info);
351 // Force static initialization.
352 extern "C" void LLVMInitializeARMTargetMC() {
353 // Register the MC asm info.
354 RegisterMCAsmInfoFn X(TheARMLETarget, createARMMCAsmInfo);
355 RegisterMCAsmInfoFn Y(TheARMBETarget, createARMMCAsmInfo);
356 RegisterMCAsmInfoFn A(TheThumbLETarget, createARMMCAsmInfo);
357 RegisterMCAsmInfoFn B(TheThumbBETarget, createARMMCAsmInfo);
359 // Register the MC codegen info.
360 TargetRegistry::RegisterMCCodeGenInfo(TheARMLETarget, createARMMCCodeGenInfo);
361 TargetRegistry::RegisterMCCodeGenInfo(TheARMBETarget, createARMMCCodeGenInfo);
362 TargetRegistry::RegisterMCCodeGenInfo(TheThumbLETarget, createARMMCCodeGenInfo);
363 TargetRegistry::RegisterMCCodeGenInfo(TheThumbBETarget, createARMMCCodeGenInfo);
365 // Register the MC instruction info.
366 TargetRegistry::RegisterMCInstrInfo(TheARMLETarget, createARMMCInstrInfo);
367 TargetRegistry::RegisterMCInstrInfo(TheARMBETarget, createARMMCInstrInfo);
368 TargetRegistry::RegisterMCInstrInfo(TheThumbLETarget, createARMMCInstrInfo);
369 TargetRegistry::RegisterMCInstrInfo(TheThumbBETarget, createARMMCInstrInfo);
371 // Register the MC register info.
372 TargetRegistry::RegisterMCRegInfo(TheARMLETarget, createARMMCRegisterInfo);
373 TargetRegistry::RegisterMCRegInfo(TheARMBETarget, createARMMCRegisterInfo);
374 TargetRegistry::RegisterMCRegInfo(TheThumbLETarget, createARMMCRegisterInfo);
375 TargetRegistry::RegisterMCRegInfo(TheThumbBETarget, createARMMCRegisterInfo);
377 // Register the MC subtarget info.
378 TargetRegistry::RegisterMCSubtargetInfo(TheARMLETarget,
379 ARM_MC::createARMMCSubtargetInfo);
380 TargetRegistry::RegisterMCSubtargetInfo(TheARMBETarget,
381 ARM_MC::createARMMCSubtargetInfo);
382 TargetRegistry::RegisterMCSubtargetInfo(TheThumbLETarget,
383 ARM_MC::createARMMCSubtargetInfo);
384 TargetRegistry::RegisterMCSubtargetInfo(TheThumbBETarget,
385 ARM_MC::createARMMCSubtargetInfo);
387 // Register the MC instruction analyzer.
388 TargetRegistry::RegisterMCInstrAnalysis(TheARMLETarget,
389 createARMMCInstrAnalysis);
390 TargetRegistry::RegisterMCInstrAnalysis(TheARMBETarget,
391 createARMMCInstrAnalysis);
392 TargetRegistry::RegisterMCInstrAnalysis(TheThumbLETarget,
393 createARMMCInstrAnalysis);
394 TargetRegistry::RegisterMCInstrAnalysis(TheThumbBETarget,
395 createARMMCInstrAnalysis);
397 // Register the MC Code Emitter
398 TargetRegistry::RegisterMCCodeEmitter(TheARMLETarget,
399 createARMLEMCCodeEmitter);
400 TargetRegistry::RegisterMCCodeEmitter(TheARMBETarget,
401 createARMBEMCCodeEmitter);
402 TargetRegistry::RegisterMCCodeEmitter(TheThumbLETarget,
403 createARMLEMCCodeEmitter);
404 TargetRegistry::RegisterMCCodeEmitter(TheThumbBETarget,
405 createARMBEMCCodeEmitter);
407 // Register the asm backend.
408 TargetRegistry::RegisterMCAsmBackend(TheARMLETarget, createARMLEAsmBackend);
409 TargetRegistry::RegisterMCAsmBackend(TheARMBETarget, createARMBEAsmBackend);
410 TargetRegistry::RegisterMCAsmBackend(TheThumbLETarget,
411 createThumbLEAsmBackend);
412 TargetRegistry::RegisterMCAsmBackend(TheThumbBETarget,
413 createThumbBEAsmBackend);
415 // Register the object streamer.
416 TargetRegistry::RegisterMCObjectStreamer(TheARMLETarget, createMCStreamer);
417 TargetRegistry::RegisterMCObjectStreamer(TheARMBETarget, createMCStreamer);
418 TargetRegistry::RegisterMCObjectStreamer(TheThumbLETarget, createMCStreamer);
419 TargetRegistry::RegisterMCObjectStreamer(TheThumbBETarget, createMCStreamer);
421 // Register the asm streamer.
422 TargetRegistry::RegisterAsmStreamer(TheARMLETarget, createMCAsmStreamer);
423 TargetRegistry::RegisterAsmStreamer(TheARMBETarget, createMCAsmStreamer);
424 TargetRegistry::RegisterAsmStreamer(TheThumbLETarget, createMCAsmStreamer);
425 TargetRegistry::RegisterAsmStreamer(TheThumbBETarget, createMCAsmStreamer);
427 // Register the MCInstPrinter.
428 TargetRegistry::RegisterMCInstPrinter(TheARMLETarget, createARMMCInstPrinter);
429 TargetRegistry::RegisterMCInstPrinter(TheARMBETarget, createARMMCInstPrinter);
430 TargetRegistry::RegisterMCInstPrinter(TheThumbLETarget,
431 createARMMCInstPrinter);
432 TargetRegistry::RegisterMCInstPrinter(TheThumbBETarget,
433 createARMMCInstPrinter);
435 // Register the MC relocation info.
436 TargetRegistry::RegisterMCRelocationInfo(TheARMLETarget,
437 createARMMCRelocationInfo);
438 TargetRegistry::RegisterMCRelocationInfo(TheARMBETarget,
439 createARMMCRelocationInfo);
440 TargetRegistry::RegisterMCRelocationInfo(TheThumbLETarget,
441 createARMMCRelocationInfo);
442 TargetRegistry::RegisterMCRelocationInfo(TheThumbBETarget,
443 createARMMCRelocationInfo);