lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

   1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides ARM specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "ARMBaseInfo.h"
  15 #include "ARMMCAsmInfo.h"
  16 #include "ARMMCTargetDesc.h"
  17 #include "InstPrinter/ARMInstPrinter.h"
  18 #include "llvm/ADT/Triple.h"
  19 #include "llvm/MC/MCCodeGenInfo.h"
  20 #include "llvm/MC/MCELFStreamer.h"
  21 #include "llvm/MC/MCInstrAnalysis.h"
  22 #include "llvm/MC/MCInstrInfo.h"
  23 #include "llvm/MC/MCRegisterInfo.h"
  24 #include "llvm/MC/MCStreamer.h"
  25 #include "llvm/MC/MCSubtargetInfo.h"
  26 #include "llvm/Support/ErrorHandling.h"
  27 #include "llvm/Support/TargetRegistry.h"
  28
  29 using namespace llvm;
  30
  31 #define GET_REGINFO_MC_DESC
  32 #include "ARMGenRegisterInfo.inc"
  33
  34 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
  35                                   std::string &Info) {
  36   if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
  37       (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
  38       (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
  39       // Checks for the deprecated CP15ISB encoding:
  40       // mcr p15, #0, rX, c7, c5, #4
  41       (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
  42     if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
  43       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
  44         Info = "deprecated since v7, use 'isb'";
  45         return true;
  46       }
  47
  48       // Checks for the deprecated CP15DSB encoding:
  49       // mcr p15, #0, rX, c7, c10, #4
  50       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
  51         Info = "deprecated since v7, use 'dsb'";
  52         return true;
  53       }
  54     }
  55     // Checks for the deprecated CP15DMB encoding:
  56     // mcr p15, #0, rX, c7, c10, #5
  57     if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
  58         (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
  59       Info = "deprecated since v7, use 'dmb'";
  60       return true;
  61     }
  62   }
  63   return false;
  64 }
  65
  66 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
  67                                   std::string &Info) {
  68   if (STI.getFeatureBits() & llvm::ARM::HasV8Ops &&
  69       MI.getOperand(1).isImm() && MI.getOperand(1).getImm() != 8) {
  70     Info = "applying IT instruction to more than one subsequent instruction is deprecated";
  71     return true;
  72   }
  73
  74   return false;
  75 }
  76
  77 #define GET_INSTRINFO_MC_DESC
  78 #include "ARMGenInstrInfo.inc"
  79
  80 #define GET_SUBTARGETINFO_MC_DESC
  81 #include "ARMGenSubtargetInfo.inc"
  82
  83
  84 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
  85   Triple triple(TT);
  86
  87   bool isThumb = triple.getArch() == Triple::thumb ||
  88                  triple.getArch() == Triple::thumbeb;
  89
  90   bool NoCPU = CPU == "generic" || CPU.empty();
  91   std::string ARMArchFeature;
  92   switch (triple.getSubArch()) {
  93   case Triple::ARMSubArch_v8:
  94     if (NoCPU)
  95       // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
  96       //      FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
  97       //      FeatureT2XtPk, FeatureCrypto, FeatureCRC
  98       ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
  99                        "+trustzone,+t2xtpk,+crypto,+crc";
 100     else
 101       // Use CPU to figure out the exact features
 102       ARMArchFeature = "+v8";
 103     break;
 104   case Triple::ARMSubArch_v7m:
 105     isThumb = true;
 106     if (NoCPU)
 107       // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
 108       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
 109     else
 110       // Use CPU to figure out the exact features.
 111       ARMArchFeature = "+v7";
 112     break;
 113   case Triple::ARMSubArch_v7em:
 114     if (NoCPU)
 115       // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
 116       //       FeatureT2XtPk, FeatureMClass
 117       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
 118     else
 119       // Use CPU to figure out the exact features.
 120       ARMArchFeature = "+v7";
 121     break;
 122   case Triple::ARMSubArch_v7s:
 123     if (NoCPU)
 124       // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
 125       //      Swift
 126       ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
 127     else
 128       // Use CPU to figure out the exact features.
 129       ARMArchFeature = "+v7";
 130     break;
 131   case Triple::ARMSubArch_v7:
 132     // v7 CPUs have lots of different feature sets. If no CPU is specified,
 133     // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
 134     // the "minimum" feature set and use CPU string to figure out the exact
 135     // features.
 136     if (NoCPU)
 137       // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
 138       ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
 139     else
 140       // Use CPU to figure out the exact features.
 141       ARMArchFeature = "+v7";
 142     break;
 143   case Triple::ARMSubArch_v6t2:
 144     ARMArchFeature = "+v6t2";
 145     break;
 146   case Triple::ARMSubArch_v6m:
 147     isThumb = true;
 148     if (NoCPU)
 149       // v6m: FeatureNoARM, FeatureMClass
 150       ARMArchFeature = "+v6m,+noarm,+mclass";
 151     else
 152       ARMArchFeature = "+v6";
 153     break;
 154   case Triple::ARMSubArch_v6:
 155     ARMArchFeature = "+v6";
 156     break;
 157   case Triple::ARMSubArch_v5te:
 158     ARMArchFeature = "+v5te";
 159     break;
 160   case Triple::ARMSubArch_v5:
 161     ARMArchFeature = "+v5t";
 162     break;
 163   case Triple::ARMSubArch_v4t:
 164     ARMArchFeature = "+v4t";
 165     break;
 166   case Triple::NoSubArch:
 167   case Triple::ARMSubArch_v4:
 168     ARMArchFeature = "+v4";
 169     break;
 170   }
 171
 172   if (isThumb) {
 173     if (ARMArchFeature.empty())
 174       ARMArchFeature = "+thumb-mode";
 175     else
 176       ARMArchFeature += ",+thumb-mode";
 177   }
 178
 179   if (triple.isOSNaCl()) {
 180     if (ARMArchFeature.empty())
 181       ARMArchFeature = "+nacl-trap";
 182     else
 183       ARMArchFeature += ",+nacl-trap";
 184   }
 185
 186   return ARMArchFeature;
 187 }
 188
 189 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
 190                                                   StringRef FS) {
 191   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
 192   if (!FS.empty()) {
 193     if (!ArchFS.empty())
 194       ArchFS = ArchFS + "," + FS.str();
 195     else
 196       ArchFS = FS;
 197   }
 198
 199   MCSubtargetInfo *X = new MCSubtargetInfo();
 200   InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
 201   return X;
 202 }
 203
 204 static MCInstrInfo *createARMMCInstrInfo() {
 205   MCInstrInfo *X = new MCInstrInfo();
 206   InitARMMCInstrInfo(X);
 207   return X;
 208 }
 209
 210 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
 211   MCRegisterInfo *X = new MCRegisterInfo();
 212   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
 213   return X;
 214 }
 215
 216 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
 217   Triple TheTriple(TT);
 218
 219   MCAsmInfo *MAI;
 220   switch (TheTriple.getOS()) {
 221   case llvm::Triple::Darwin:
 222   case llvm::Triple::IOS:
 223   case llvm::Triple::MacOSX:
 224     MAI = new ARMMCAsmInfoDarwin(TT);
 225     break;
 226   case llvm::Triple::Win32:
 227     switch (TheTriple.getEnvironment()) {
 228     case llvm::Triple::Itanium:
 229       MAI = new ARMCOFFMCAsmInfoGNU();
 230       break;
 231     case llvm::Triple::MSVC:
 232       MAI = new ARMCOFFMCAsmInfoMicrosoft();
 233       break;
 234     default:
 235       llvm_unreachable("invalid environment");
 236     }
 237     break;
 238   default:
 239     if (TheTriple.isOSBinFormatMachO())
 240       MAI = new ARMMCAsmInfoDarwin(TT);
 241     else
 242       MAI = new ARMELFMCAsmInfo(TT);
 243     break;
 244   }
 245
 246   unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
 247   MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
 248
 249   return MAI;
 250 }
 251
 252 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
 253                                              CodeModel::Model CM,
 254                                              CodeGenOpt::Level OL) {
 255   MCCodeGenInfo *X = new MCCodeGenInfo();
 256   if (RM == Reloc::Default) {
 257     Triple TheTriple(TT);
 258     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
 259     RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
 260   }
 261   X->InitMCCodeGenInfo(RM, CM, OL);
 262   return X;
 263 }
 264
 265 // This is duplicated code. Refactor this.
 266 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
 267                                     MCContext &Ctx, MCAsmBackend &MAB,
 268                                     raw_ostream &OS,
 269                                     MCCodeEmitter *Emitter,
 270                                     const MCSubtargetInfo &STI,
 271                                     bool RelaxAll,
 272                                     bool NoExecStack) {
 273   Triple TheTriple(TT);
 274
 275   switch (TheTriple.getObjectFormat()) {
 276   default: llvm_unreachable("unsupported object format");
 277   case Triple::MachO: {
 278     MCStreamer *S = createMachOStreamer(Ctx, MAB, OS, Emitter, false);
 279     new ARMTargetStreamer(*S);
 280     return S;
 281   }
 282   case Triple::COFF:
 283     assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
 284     return createARMWinCOFFStreamer(Ctx, MAB, *Emitter, OS);
 285   case Triple::ELF:
 286     return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack,
 287                                 TheTriple.getArch() == Triple::thumb);
 288   }
 289 }
 290
 291 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
 292                                              unsigned SyntaxVariant,
 293                                              const MCAsmInfo &MAI,
 294                                              const MCInstrInfo &MII,
 295                                              const MCRegisterInfo &MRI,
 296                                              const MCSubtargetInfo &STI) {
 297   if (SyntaxVariant == 0)
 298     return new ARMInstPrinter(MAI, MII, MRI, STI);
 299   return nullptr;
 300 }
 301
 302 static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
 303                                                    MCContext &Ctx) {
 304   Triple TheTriple(TT);
 305   if (TheTriple.isOSBinFormatMachO())
 306     return createARMMachORelocationInfo(Ctx);
 307   // Default to the stock relocation info.
 308   return llvm::createMCRelocationInfo(TT, Ctx);
 309 }
 310
 311 namespace {
 312
 313 class ARMMCInstrAnalysis : public MCInstrAnalysis {
 314 public:
 315   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
 316
 317   bool isUnconditionalBranch(const MCInst &Inst) const override {
 318     // BCCs with the "always" predicate are unconditional branches.
 319     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
 320       return true;
 321     return MCInstrAnalysis::isUnconditionalBranch(Inst);
 322   }
 323
 324   bool isConditionalBranch(const MCInst &Inst) const override {
 325     // BCCs with the "always" predicate are unconditional branches.
 326     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
 327       return false;
 328     return MCInstrAnalysis::isConditionalBranch(Inst);
 329   }
 330
 331   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
 332                       uint64_t Size, uint64_t &Target) const override {
 333     // We only handle PCRel branches for now.
 334     if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
 335       return false;
 336
 337     int64_t Imm = Inst.getOperand(0).getImm();
 338     // FIXME: This is not right for thumb.
 339     Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
 340     return true;
 341   }
 342 };
 343
 344 }
 345
 346 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
 347   return new ARMMCInstrAnalysis(Info);
 348 }
 349
 350 // Force static initialization.
 351 extern "C" void LLVMInitializeARMTargetMC() {
 352   // Register the MC asm info.
 353   RegisterMCAsmInfoFn X(TheARMLETarget, createARMMCAsmInfo);
 354   RegisterMCAsmInfoFn Y(TheARMBETarget, createARMMCAsmInfo);
 355   RegisterMCAsmInfoFn A(TheThumbLETarget, createARMMCAsmInfo);
 356   RegisterMCAsmInfoFn B(TheThumbBETarget, createARMMCAsmInfo);
 357
 358   // Register the MC codegen info.
 359   TargetRegistry::RegisterMCCodeGenInfo(TheARMLETarget, createARMMCCodeGenInfo);
 360   TargetRegistry::RegisterMCCodeGenInfo(TheARMBETarget, createARMMCCodeGenInfo);
 361   TargetRegistry::RegisterMCCodeGenInfo(TheThumbLETarget, createARMMCCodeGenInfo);
 362   TargetRegistry::RegisterMCCodeGenInfo(TheThumbBETarget, createARMMCCodeGenInfo);
 363
 364   // Register the MC instruction info.
 365   TargetRegistry::RegisterMCInstrInfo(TheARMLETarget, createARMMCInstrInfo);
 366   TargetRegistry::RegisterMCInstrInfo(TheARMBETarget, createARMMCInstrInfo);
 367   TargetRegistry::RegisterMCInstrInfo(TheThumbLETarget, createARMMCInstrInfo);
 368   TargetRegistry::RegisterMCInstrInfo(TheThumbBETarget, createARMMCInstrInfo);
 369
 370   // Register the MC register info.
 371   TargetRegistry::RegisterMCRegInfo(TheARMLETarget, createARMMCRegisterInfo);
 372   TargetRegistry::RegisterMCRegInfo(TheARMBETarget, createARMMCRegisterInfo);
 373   TargetRegistry::RegisterMCRegInfo(TheThumbLETarget, createARMMCRegisterInfo);
 374   TargetRegistry::RegisterMCRegInfo(TheThumbBETarget, createARMMCRegisterInfo);
 375
 376   // Register the MC subtarget info.
 377   TargetRegistry::RegisterMCSubtargetInfo(TheARMLETarget,
 378                                           ARM_MC::createARMMCSubtargetInfo);
 379   TargetRegistry::RegisterMCSubtargetInfo(TheARMBETarget,
 380                                           ARM_MC::createARMMCSubtargetInfo);
 381   TargetRegistry::RegisterMCSubtargetInfo(TheThumbLETarget,
 382                                           ARM_MC::createARMMCSubtargetInfo);
 383   TargetRegistry::RegisterMCSubtargetInfo(TheThumbBETarget,
 384                                           ARM_MC::createARMMCSubtargetInfo);
 385
 386   // Register the MC instruction analyzer.
 387   TargetRegistry::RegisterMCInstrAnalysis(TheARMLETarget,
 388                                           createARMMCInstrAnalysis);
 389   TargetRegistry::RegisterMCInstrAnalysis(TheARMBETarget,
 390                                           createARMMCInstrAnalysis);
 391   TargetRegistry::RegisterMCInstrAnalysis(TheThumbLETarget,
 392                                           createARMMCInstrAnalysis);
 393   TargetRegistry::RegisterMCInstrAnalysis(TheThumbBETarget,
 394                                           createARMMCInstrAnalysis);
 395
 396   // Register the MC Code Emitter
 397   TargetRegistry::RegisterMCCodeEmitter(TheARMLETarget,
 398                                         createARMLEMCCodeEmitter);
 399   TargetRegistry::RegisterMCCodeEmitter(TheARMBETarget,
 400                                         createARMBEMCCodeEmitter);
 401   TargetRegistry::RegisterMCCodeEmitter(TheThumbLETarget,
 402                                         createARMLEMCCodeEmitter);
 403   TargetRegistry::RegisterMCCodeEmitter(TheThumbBETarget,
 404                                         createARMBEMCCodeEmitter);
 405
 406   // Register the asm backend.
 407   TargetRegistry::RegisterMCAsmBackend(TheARMLETarget, createARMLEAsmBackend);
 408   TargetRegistry::RegisterMCAsmBackend(TheARMBETarget, createARMBEAsmBackend);
 409   TargetRegistry::RegisterMCAsmBackend(TheThumbLETarget,
 410                                        createThumbLEAsmBackend);
 411   TargetRegistry::RegisterMCAsmBackend(TheThumbBETarget,
 412                                        createThumbBEAsmBackend);
 413
 414   // Register the object streamer.
 415   TargetRegistry::RegisterMCObjectStreamer(TheARMLETarget, createMCStreamer);
 416   TargetRegistry::RegisterMCObjectStreamer(TheARMBETarget, createMCStreamer);
 417   TargetRegistry::RegisterMCObjectStreamer(TheThumbLETarget, createMCStreamer);
 418   TargetRegistry::RegisterMCObjectStreamer(TheThumbBETarget, createMCStreamer);
 419
 420   // Register the asm streamer.
 421   TargetRegistry::RegisterAsmStreamer(TheARMLETarget, createMCAsmStreamer);
 422   TargetRegistry::RegisterAsmStreamer(TheARMBETarget, createMCAsmStreamer);
 423   TargetRegistry::RegisterAsmStreamer(TheThumbLETarget, createMCAsmStreamer);
 424   TargetRegistry::RegisterAsmStreamer(TheThumbBETarget, createMCAsmStreamer);
 425
 426   // Register the null streamer.
 427   TargetRegistry::RegisterNullStreamer(TheARMLETarget, createARMNullStreamer);
 428   TargetRegistry::RegisterNullStreamer(TheARMBETarget, createARMNullStreamer);
 429   TargetRegistry::RegisterNullStreamer(TheThumbLETarget, createARMNullStreamer);
 430   TargetRegistry::RegisterNullStreamer(TheThumbBETarget, createARMNullStreamer);
 431
 432   // Register the MCInstPrinter.
 433   TargetRegistry::RegisterMCInstPrinter(TheARMLETarget, createARMMCInstPrinter);
 434   TargetRegistry::RegisterMCInstPrinter(TheARMBETarget, createARMMCInstPrinter);
 435   TargetRegistry::RegisterMCInstPrinter(TheThumbLETarget,
 436                                         createARMMCInstPrinter);
 437   TargetRegistry::RegisterMCInstPrinter(TheThumbBETarget,
 438                                         createARMMCInstPrinter);
 439
 440   // Register the MC relocation info.
 441   TargetRegistry::RegisterMCRelocationInfo(TheARMLETarget,
 442                                            createARMMCRelocationInfo);
 443   TargetRegistry::RegisterMCRelocationInfo(TheARMBETarget,
 444                                            createARMMCRelocationInfo);
 445   TargetRegistry::RegisterMCRelocationInfo(TheThumbLETarget,
 446                                            createARMMCRelocationInfo);
 447   TargetRegistry::RegisterMCRelocationInfo(TheThumbBETarget,
 448                                            createARMMCRelocationInfo);
 449 }