1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides ARM specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInfo.h"
15 #include "ARMMCAsmInfo.h"
16 #include "ARMMCTargetDesc.h"
17 #include "InstPrinter/ARMInstPrinter.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCELFStreamer.h"
21 #include "llvm/MC/MCInstrAnalysis.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
30 #define GET_REGINFO_MC_DESC
31 #include "ARMGenRegisterInfo.inc"
33 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
35 if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
36 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
37 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
38 // Checks for the deprecated CP15ISB encoding:
39 // mcr p15, #0, rX, c7, c5, #4
40 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
41 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
42 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
43 Info = "deprecated since v7, use 'isb'";
47 // Checks for the deprecated CP15DSB encoding:
48 // mcr p15, #0, rX, c7, c10, #4
49 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
50 Info = "deprecated since v7, use 'dsb'";
54 // Checks for the deprecated CP15DMB encoding:
55 // mcr p15, #0, rX, c7, c10, #5
56 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
57 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
58 Info = "deprecated since v7, use 'dmb'";
65 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
67 if (STI.getFeatureBits() & llvm::ARM::HasV8Ops &&
68 MI.getOperand(1).isImm() && MI.getOperand(1).getImm() != 8) {
69 Info = "applying IT instruction to more than one subsequent instruction is deprecated";
76 #define GET_INSTRINFO_MC_DESC
77 #include "ARMGenInstrInfo.inc"
79 #define GET_SUBTARGETINFO_MC_DESC
80 #include "ARMGenSubtargetInfo.inc"
83 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
86 // Set the boolean corresponding to the current target triple, or the default
87 // if one cannot be determined, to true.
88 unsigned Len = TT.size();
91 // FIXME: Enhance Triple helper class to extract ARM version.
93 if (Len >= 5 && TT.substr(0, 4) == "armv")
95 else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
97 if (Len >= 7 && TT[5] == 'v')
101 bool NoCPU = CPU == "generic" || CPU.empty();
102 std::string ARMArchFeature;
104 unsigned SubVer = TT[Idx];
107 // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2, FeatureMP,
108 // FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone, FeatureT2XtPk, FeatureCrypto
109 ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,+trustzone,+t2xtpk,+crypto";
111 // Use CPU to figure out the exact features
112 ARMArchFeature = "+v8";
113 } else if (SubVer == '7') {
114 if (Len >= Idx+2 && TT[Idx+1] == 'm') {
117 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
118 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
120 // Use CPU to figure out the exact features.
121 ARMArchFeature = "+v7";
122 } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
124 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
125 // FeatureT2XtPk, FeatureMClass
126 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
128 // Use CPU to figure out the exact features.
129 ARMArchFeature = "+v7";
130 } else if (Len >= Idx+2 && TT[Idx+1] == 's') {
132 // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
134 ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+t2xtpk";
136 // Use CPU to figure out the exact features.
137 ARMArchFeature = "+v7";
139 // v7 CPUs have lots of different feature sets. If no CPU is specified,
140 // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
141 // the "minimum" feature set and use CPU string to figure out the exact
144 // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
145 ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
147 // Use CPU to figure out the exact features.
148 ARMArchFeature = "+v7";
150 } else if (SubVer == '6') {
151 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
152 ARMArchFeature = "+v6t2";
153 else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
156 // v6m: FeatureNoARM, FeatureMClass
157 ARMArchFeature = "+v6m,+noarm,+mclass";
159 ARMArchFeature = "+v6";
161 ARMArchFeature = "+v6";
162 } else if (SubVer == '5') {
163 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
164 ARMArchFeature = "+v5te";
166 ARMArchFeature = "+v5t";
167 } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
168 ARMArchFeature = "+v4t";
172 if (ARMArchFeature.empty())
173 ARMArchFeature = "+thumb-mode";
175 ARMArchFeature += ",+thumb-mode";
178 if (triple.isOSNaCl()) {
179 if (ARMArchFeature.empty())
180 ARMArchFeature = "+nacl-trap";
182 ARMArchFeature += ",+nacl-trap";
185 return ARMArchFeature;
188 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
190 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
193 ArchFS = ArchFS + "," + FS.str();
198 MCSubtargetInfo *X = new MCSubtargetInfo();
199 InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
203 static MCInstrInfo *createARMMCInstrInfo() {
204 MCInstrInfo *X = new MCInstrInfo();
205 InitARMMCInstrInfo(X);
209 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
210 MCRegisterInfo *X = new MCRegisterInfo();
211 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
215 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
216 Triple TheTriple(TT);
218 if (TheTriple.isOSDarwin())
219 return new ARMMCAsmInfoDarwin();
221 return new ARMELFMCAsmInfo();
224 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
226 CodeGenOpt::Level OL) {
227 MCCodeGenInfo *X = new MCCodeGenInfo();
228 if (RM == Reloc::Default) {
229 Triple TheTriple(TT);
230 // Default relocation model on Darwin is PIC, not DynamicNoPIC.
231 RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
233 X->InitMCCodeGenInfo(RM, CM, OL);
237 // This is duplicated code. Refactor this.
238 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
239 MCContext &Ctx, MCAsmBackend &MAB,
241 MCCodeEmitter *Emitter,
244 Triple TheTriple(TT);
246 if (TheTriple.isOSDarwin())
247 return createMachOStreamer(Ctx, MAB, OS, Emitter, false);
249 if (TheTriple.isOSWindows()) {
250 llvm_unreachable("ARM does not support Windows COFF format");
253 return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack,
254 TheTriple.getArch() == Triple::thumb);
257 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
258 unsigned SyntaxVariant,
259 const MCAsmInfo &MAI,
260 const MCInstrInfo &MII,
261 const MCRegisterInfo &MRI,
262 const MCSubtargetInfo &STI) {
263 if (SyntaxVariant == 0)
264 return new ARMInstPrinter(MAI, MII, MRI, STI);
268 static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
270 Triple TheTriple(TT);
271 if (TheTriple.isEnvironmentMachO())
272 return createARMMachORelocationInfo(Ctx);
273 // Default to the stock relocation info.
274 return llvm::createMCRelocationInfo(TT, Ctx);
279 class ARMMCInstrAnalysis : public MCInstrAnalysis {
281 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
283 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
284 // BCCs with the "always" predicate are unconditional branches.
285 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
287 return MCInstrAnalysis::isUnconditionalBranch(Inst);
290 virtual bool isConditionalBranch(const MCInst &Inst) const {
291 // BCCs with the "always" predicate are unconditional branches.
292 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
294 return MCInstrAnalysis::isConditionalBranch(Inst);
297 bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
298 uint64_t Size, uint64_t &Target) const {
299 // We only handle PCRel branches for now.
300 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
303 int64_t Imm = Inst.getOperand(0).getImm();
304 // FIXME: This is not right for thumb.
305 Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
312 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
313 return new ARMMCInstrAnalysis(Info);
316 // Force static initialization.
317 extern "C" void LLVMInitializeARMTargetMC() {
318 // Register the MC asm info.
319 RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
320 RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
322 // Register the MC codegen info.
323 TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
324 TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
326 // Register the MC instruction info.
327 TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
328 TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
330 // Register the MC register info.
331 TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
332 TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
334 // Register the MC subtarget info.
335 TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
336 ARM_MC::createARMMCSubtargetInfo);
337 TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
338 ARM_MC::createARMMCSubtargetInfo);
340 // Register the MC instruction analyzer.
341 TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
342 createARMMCInstrAnalysis);
343 TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
344 createARMMCInstrAnalysis);
346 // Register the MC Code Emitter
347 TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
348 TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
350 // Register the asm backend.
351 TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
352 TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
354 // Register the object streamer.
355 TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
356 TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
358 // Register the asm streamer.
359 TargetRegistry::RegisterAsmStreamer(TheARMTarget, createMCAsmStreamer);
360 TargetRegistry::RegisterAsmStreamer(TheThumbTarget, createMCAsmStreamer);
362 // Register the MCInstPrinter.
363 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
364 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
366 // Register the MC relocation info.
367 TargetRegistry::RegisterMCRelocationInfo(TheARMTarget,
368 createARMMCRelocationInfo);
369 TargetRegistry::RegisterMCRelocationInfo(TheThumbTarget,
370 createARMMCRelocationInfo);