1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides ARM specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInfo.h"
15 #include "ARMELFStreamer.h"
16 #include "ARMMCAsmInfo.h"
17 #include "ARMMCTargetDesc.h"
18 #include "InstPrinter/ARMInstPrinter.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/MC/MCCodeGenInfo.h"
21 #include "llvm/MC/MCInstrAnalysis.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
31 #define GET_REGINFO_MC_DESC
32 #include "ARMGenRegisterInfo.inc"
34 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
36 if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
37 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
38 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
39 // Checks for the deprecated CP15ISB encoding:
40 // mcr p15, #0, rX, c7, c5, #4
41 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
42 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
43 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
44 Info = "deprecated since v7, use 'isb'";
48 // Checks for the deprecated CP15DSB encoding:
49 // mcr p15, #0, rX, c7, c10, #4
50 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
51 Info = "deprecated since v7, use 'dsb'";
55 // Checks for the deprecated CP15DMB encoding:
56 // mcr p15, #0, rX, c7, c10, #5
57 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
58 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
59 Info = "deprecated since v7, use 'dmb'";
66 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
68 if (STI.getFeatureBits() & llvm::ARM::HasV8Ops &&
69 MI.getOperand(1).isImm() && MI.getOperand(1).getImm() != 8) {
70 Info = "applying IT instruction to more than one subsequent instruction is deprecated";
77 #define GET_INSTRINFO_MC_DESC
78 #include "ARMGenInstrInfo.inc"
80 #define GET_SUBTARGETINFO_MC_DESC
81 #include "ARMGenSubtargetInfo.inc"
84 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
87 // Set the boolean corresponding to the current target triple, or the default
88 // if one cannot be determined, to true.
89 unsigned Len = TT.size();
92 // FIXME: Enhance Triple helper class to extract ARM version.
94 if (Len >= 5 && TT.substr(0, 4) == "armv")
96 else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
98 if (Len >= 7 && TT[5] == 'v')
102 bool NoCPU = CPU == "generic" || CPU.empty();
103 std::string ARMArchFeature;
105 unsigned SubVer = TT[Idx];
107 // FIXME: Parse v8 features
108 ARMArchFeature = "+v8,+db";
109 } else if (SubVer == '7') {
110 if (Len >= Idx+2 && TT[Idx+1] == 'm') {
113 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
114 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
116 // Use CPU to figure out the exact features.
117 ARMArchFeature = "+v7";
118 } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
120 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
121 // FeatureT2XtPk, FeatureMClass
122 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
124 // Use CPU to figure out the exact features.
125 ARMArchFeature = "+v7";
126 } else if (Len >= Idx+2 && TT[Idx+1] == 's') {
128 // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
130 ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+t2xtpk";
132 // Use CPU to figure out the exact features.
133 ARMArchFeature = "+v7";
135 // v7 CPUs have lots of different feature sets. If no CPU is specified,
136 // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
137 // the "minimum" feature set and use CPU string to figure out the exact
140 // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
141 ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
143 // Use CPU to figure out the exact features.
144 ARMArchFeature = "+v7";
146 } else if (SubVer == '6') {
147 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
148 ARMArchFeature = "+v6t2";
149 else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
152 // v6m: FeatureNoARM, FeatureMClass
153 ARMArchFeature = "+v6,+noarm,+mclass";
155 ARMArchFeature = "+v6";
157 ARMArchFeature = "+v6";
158 } else if (SubVer == '5') {
159 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
160 ARMArchFeature = "+v5te";
162 ARMArchFeature = "+v5t";
163 } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
164 ARMArchFeature = "+v4t";
168 if (ARMArchFeature.empty())
169 ARMArchFeature = "+thumb-mode";
171 ARMArchFeature += ",+thumb-mode";
174 if (triple.isOSNaCl()) {
175 if (ARMArchFeature.empty())
176 ARMArchFeature = "+nacl-trap";
178 ARMArchFeature += ",+nacl-trap";
181 return ARMArchFeature;
184 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
186 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
189 ArchFS = ArchFS + "," + FS.str();
194 MCSubtargetInfo *X = new MCSubtargetInfo();
195 InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
199 static MCInstrInfo *createARMMCInstrInfo() {
200 MCInstrInfo *X = new MCInstrInfo();
201 InitARMMCInstrInfo(X);
205 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
206 MCRegisterInfo *X = new MCRegisterInfo();
207 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
211 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
212 Triple TheTriple(TT);
214 if (TheTriple.isOSDarwin())
215 return new ARMMCAsmInfoDarwin();
217 return new ARMELFMCAsmInfo();
220 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
222 CodeGenOpt::Level OL) {
223 MCCodeGenInfo *X = new MCCodeGenInfo();
224 if (RM == Reloc::Default) {
225 Triple TheTriple(TT);
226 // Default relocation model on Darwin is PIC, not DynamicNoPIC.
227 RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
229 X->InitMCCodeGenInfo(RM, CM, OL);
233 // This is duplicated code. Refactor this.
234 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
235 MCContext &Ctx, MCAsmBackend &MAB,
237 MCCodeEmitter *Emitter,
240 Triple TheTriple(TT);
242 if (TheTriple.isOSDarwin())
243 return createMachOStreamer(Ctx, MAB, OS, Emitter, false);
245 if (TheTriple.isOSWindows()) {
246 llvm_unreachable("ARM does not support Windows COFF format");
249 return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack,
250 TheTriple.getArch() == Triple::thumb);
253 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
254 unsigned SyntaxVariant,
255 const MCAsmInfo &MAI,
256 const MCInstrInfo &MII,
257 const MCRegisterInfo &MRI,
258 const MCSubtargetInfo &STI) {
259 if (SyntaxVariant == 0)
260 return new ARMInstPrinter(MAI, MII, MRI, STI);
264 static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
266 Triple TheTriple(TT);
267 if (TheTriple.isEnvironmentMachO())
268 return createARMMachORelocationInfo(Ctx);
269 // Default to the stock relocation info.
270 return llvm::createMCRelocationInfo(TT, Ctx);
275 class ARMMCInstrAnalysis : public MCInstrAnalysis {
277 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
279 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
280 // BCCs with the "always" predicate are unconditional branches.
281 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
283 return MCInstrAnalysis::isUnconditionalBranch(Inst);
286 virtual bool isConditionalBranch(const MCInst &Inst) const {
287 // BCCs with the "always" predicate are unconditional branches.
288 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
290 return MCInstrAnalysis::isConditionalBranch(Inst);
293 bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
294 uint64_t Size, uint64_t &Target) const {
295 // We only handle PCRel branches for now.
296 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
299 int64_t Imm = Inst.getOperand(0).getImm();
300 // FIXME: This is not right for thumb.
301 Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
308 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
309 return new ARMMCInstrAnalysis(Info);
312 // Force static initialization.
313 extern "C" void LLVMInitializeARMTargetMC() {
314 // Register the MC asm info.
315 RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
316 RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
318 // Register the MC codegen info.
319 TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
320 TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
322 // Register the MC instruction info.
323 TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
324 TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
326 // Register the MC register info.
327 TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
328 TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
330 // Register the MC subtarget info.
331 TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
332 ARM_MC::createARMMCSubtargetInfo);
333 TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
334 ARM_MC::createARMMCSubtargetInfo);
336 // Register the MC instruction analyzer.
337 TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
338 createARMMCInstrAnalysis);
339 TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
340 createARMMCInstrAnalysis);
342 // Register the MC Code Emitter
343 TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
344 TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
346 // Register the asm backend.
347 TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
348 TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
350 // Register the object streamer.
351 TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
352 TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
354 // Register the MCInstPrinter.
355 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
356 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
358 // Register the MC relocation info.
359 TargetRegistry::RegisterMCRelocationInfo(TheARMTarget,
360 createARMMCRelocationInfo);
361 TargetRegistry::RegisterMCRelocationInfo(TheThumbTarget,
362 createARMMCRelocationInfo);