lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

   1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides ARM specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "ARMBaseInfo.h"
  15 #include "ARMMCAsmInfo.h"
  16 #include "ARMMCTargetDesc.h"
  17 #include "InstPrinter/ARMInstPrinter.h"
  18 #include "llvm/ADT/Triple.h"
  19 #include "llvm/MC/MCCodeGenInfo.h"
  20 #include "llvm/MC/MCELFStreamer.h"
  21 #include "llvm/MC/MCInstrAnalysis.h"
  22 #include "llvm/MC/MCInstrInfo.h"
  23 #include "llvm/MC/MCRegisterInfo.h"
  24 #include "llvm/MC/MCStreamer.h"
  25 #include "llvm/MC/MCSubtargetInfo.h"
  26 #include "llvm/Support/ErrorHandling.h"
  27 #include "llvm/Support/TargetRegistry.h"
  28
  29 using namespace llvm;
  30
  31 #define GET_REGINFO_MC_DESC
  32 #include "ARMGenRegisterInfo.inc"
  33
  34 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
  35                                   std::string &Info) {
  36   if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
  37       (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
  38       (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
  39       // Checks for the deprecated CP15ISB encoding:
  40       // mcr p15, #0, rX, c7, c5, #4
  41       (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
  42     if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
  43       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
  44         Info = "deprecated since v7, use 'isb'";
  45         return true;
  46       }
  47
  48       // Checks for the deprecated CP15DSB encoding:
  49       // mcr p15, #0, rX, c7, c10, #4
  50       if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
  51         Info = "deprecated since v7, use 'dsb'";
  52         return true;
  53       }
  54     }
  55     // Checks for the deprecated CP15DMB encoding:
  56     // mcr p15, #0, rX, c7, c10, #5
  57     if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
  58         (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
  59       Info = "deprecated since v7, use 'dmb'";
  60       return true;
  61     }
  62   }
  63   return false;
  64 }
  65
  66 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
  67                                  std::string &Info) {
  68   if (STI.getFeatureBits() & llvm::ARM::HasV8Ops && MI.getOperand(1).isImm() &&
  69       MI.getOperand(1).getImm() != 8) {
  70     Info = "applying IT instruction to more than one subsequent instruction is "
  71            "deprecated";
  72     return true;
  73   }
  74
  75   return false;
  76 }
  77
  78 static bool getARMStoreDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
  79                                        std::string &Info) {
  80   assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) &&
  81          "cannot predicate thumb instructions");
  82
  83   assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
  84   for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
  85     assert(MI.getOperand(OI).isReg() && "expected register");
  86     if (MI.getOperand(OI).getReg() == ARM::SP ||
  87         MI.getOperand(OI).getReg() == ARM::PC) {
  88       Info = "use of SP or PC in the list is deprecated";
  89       return true;
  90     }
  91   }
  92   return false;
  93 }
  94
  95 static bool getARMLoadDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
  96                                       std::string &Info) {
  97   assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) &&
  98          "cannot predicate thumb instructions");
  99
 100   assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
 101   bool ListContainsPC = false, ListContainsLR = false;
 102   for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
 103     assert(MI.getOperand(OI).isReg() && "expected register");
 104     switch (MI.getOperand(OI).getReg()) {
 105     default:
 106       break;
 107     case ARM::LR:
 108       ListContainsLR = true;
 109       break;
 110     case ARM::PC:
 111       ListContainsPC = true;
 112       break;
 113     case ARM::SP:
 114       Info = "use of SP in the list is deprecated";
 115       return true;
 116     }
 117   }
 118
 119   if (ListContainsPC && ListContainsLR) {
 120     Info = "use of LR and PC simultaneously in the list is deprecated";
 121     return true;
 122   }
 123
 124   return false;
 125 }
 126
 127 #define GET_INSTRINFO_MC_DESC
 128 #include "ARMGenInstrInfo.inc"
 129
 130 #define GET_SUBTARGETINFO_MC_DESC
 131 #include "ARMGenSubtargetInfo.inc"
 132
 133
 134 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
 135   Triple triple(TT);
 136
 137   bool isThumb = triple.getArch() == Triple::thumb ||
 138                  triple.getArch() == Triple::thumbeb;
 139
 140   bool NoCPU = CPU == "generic" || CPU.empty();
 141   std::string ARMArchFeature;
 142   switch (triple.getSubArch()) {
 143   default:
 144     llvm_unreachable("invalid sub-architecture for ARM");
 145   case Triple::ARMSubArch_v8:
 146     if (NoCPU)
 147       // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
 148       //      FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
 149       //      FeatureT2XtPk, FeatureCrypto, FeatureCRC
 150       ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
 151                        "+trustzone,+t2xtpk,+crypto,+crc";
 152     else
 153       // Use CPU to figure out the exact features
 154       ARMArchFeature = "+v8";
 155     break;
 156   case Triple::ARMSubArch_v7m:
 157     isThumb = true;
 158     if (NoCPU)
 159       // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
 160       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
 161     else
 162       // Use CPU to figure out the exact features.
 163       ARMArchFeature = "+v7";
 164     break;
 165   case Triple::ARMSubArch_v7em:
 166     if (NoCPU)
 167       // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
 168       //       FeatureT2XtPk, FeatureMClass
 169       ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
 170     else
 171       // Use CPU to figure out the exact features.
 172       ARMArchFeature = "+v7";
 173     break;
 174   case Triple::ARMSubArch_v7s:
 175     if (NoCPU)
 176       // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
 177       //      Swift
 178       ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
 179     else
 180       // Use CPU to figure out the exact features.
 181       ARMArchFeature = "+v7";
 182     break;
 183   case Triple::ARMSubArch_v7:
 184     // v7 CPUs have lots of different feature sets. If no CPU is specified,
 185     // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
 186     // the "minimum" feature set and use CPU string to figure out the exact
 187     // features.
 188     if (NoCPU)
 189       // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
 190       ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
 191     else
 192       // Use CPU to figure out the exact features.
 193       ARMArchFeature = "+v7";
 194     break;
 195   case Triple::ARMSubArch_v6t2:
 196     ARMArchFeature = "+v6t2";
 197     break;
 198   case Triple::ARMSubArch_v6k:
 199     ARMArchFeature = "+v6k";
 200     break;
 201   case Triple::ARMSubArch_v6m:
 202     isThumb = true;
 203     if (NoCPU)
 204       // v6m: FeatureNoARM, FeatureMClass
 205       ARMArchFeature = "+v6m,+noarm,+mclass";
 206     else
 207       ARMArchFeature = "+v6";
 208     break;
 209   case Triple::ARMSubArch_v6:
 210     ARMArchFeature = "+v6";
 211     break;
 212   case Triple::ARMSubArch_v5te:
 213     ARMArchFeature = "+v5te";
 214     break;
 215   case Triple::ARMSubArch_v5:
 216     ARMArchFeature = "+v5t";
 217     break;
 218   case Triple::ARMSubArch_v4t:
 219     ARMArchFeature = "+v4t";
 220     break;
 221   case Triple::NoSubArch:
 222     break;
 223   }
 224
 225   if (isThumb) {
 226     if (ARMArchFeature.empty())
 227       ARMArchFeature = "+thumb-mode";
 228     else
 229       ARMArchFeature += ",+thumb-mode";
 230   }
 231
 232   if (triple.isOSNaCl()) {
 233     if (ARMArchFeature.empty())
 234       ARMArchFeature = "+nacl-trap";
 235     else
 236       ARMArchFeature += ",+nacl-trap";
 237   }
 238
 239   return ARMArchFeature;
 240 }
 241
 242 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
 243                                                   StringRef FS) {
 244   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
 245   if (!FS.empty()) {
 246     if (!ArchFS.empty())
 247       ArchFS = ArchFS + "," + FS.str();
 248     else
 249       ArchFS = FS;
 250   }
 251
 252   MCSubtargetInfo *X = new MCSubtargetInfo();
 253   InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
 254   return X;
 255 }
 256
 257 static MCInstrInfo *createARMMCInstrInfo() {
 258   MCInstrInfo *X = new MCInstrInfo();
 259   InitARMMCInstrInfo(X);
 260   return X;
 261 }
 262
 263 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
 264   MCRegisterInfo *X = new MCRegisterInfo();
 265   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
 266   return X;
 267 }
 268
 269 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
 270   Triple TheTriple(TT);
 271
 272   MCAsmInfo *MAI;
 273   if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
 274     MAI = new ARMMCAsmInfoDarwin(TT);
 275   else if (TheTriple.isWindowsItaniumEnvironment())
 276     MAI = new ARMCOFFMCAsmInfoGNU();
 277   else if (TheTriple.isWindowsMSVCEnvironment())
 278     MAI = new ARMCOFFMCAsmInfoMicrosoft();
 279   else
 280     MAI = new ARMELFMCAsmInfo(TT);
 281
 282   unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
 283   MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
 284
 285   return MAI;
 286 }
 287
 288 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
 289                                              CodeModel::Model CM,
 290                                              CodeGenOpt::Level OL) {
 291   MCCodeGenInfo *X = new MCCodeGenInfo();
 292   if (RM == Reloc::Default) {
 293     Triple TheTriple(TT);
 294     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
 295     RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
 296   }
 297   X->InitMCCodeGenInfo(RM, CM, OL);
 298   return X;
 299 }
 300
 301 // This is duplicated code. Refactor this.
 302 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Ctx,
 303                                     MCAsmBackend &MAB, raw_ostream &OS,
 304                                     MCCodeEmitter *Emitter,
 305                                     const MCSubtargetInfo &STI, bool RelaxAll) {
 306   switch (T.getObjectFormat()) {
 307   default: llvm_unreachable("unsupported object format");
 308   case Triple::MachO: {
 309     MCStreamer *S = createMachOStreamer(Ctx, MAB, OS, Emitter, false);
 310     new ARMTargetStreamer(*S);
 311     return S;
 312   }
 313   case Triple::COFF:
 314     assert(T.isOSWindows() && "non-Windows ARM COFF is not supported");
 315     return createARMWinCOFFStreamer(Ctx, MAB, *Emitter, OS);
 316   case Triple::ELF:
 317     return createARMELFStreamer(Ctx, MAB, OS, Emitter, false,
 318                                 T.getArch() == Triple::thumb);
 319   }
 320 }
 321
 322 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
 323                                              unsigned SyntaxVariant,
 324                                              const MCAsmInfo &MAI,
 325                                              const MCInstrInfo &MII,
 326                                              const MCRegisterInfo &MRI,
 327                                              const MCSubtargetInfo &STI) {
 328   if (SyntaxVariant == 0)
 329     return new ARMInstPrinter(MAI, MII, MRI, STI);
 330   return nullptr;
 331 }
 332
 333 static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
 334                                                    MCContext &Ctx) {
 335   Triple TheTriple(TT);
 336   if (TheTriple.isOSBinFormatMachO())
 337     return createARMMachORelocationInfo(Ctx);
 338   // Default to the stock relocation info.
 339   return llvm::createMCRelocationInfo(TT, Ctx);
 340 }
 341
 342 namespace {
 343
 344 class ARMMCInstrAnalysis : public MCInstrAnalysis {
 345 public:
 346   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
 347
 348   bool isUnconditionalBranch(const MCInst &Inst) const override {
 349     // BCCs with the "always" predicate are unconditional branches.
 350     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
 351       return true;
 352     return MCInstrAnalysis::isUnconditionalBranch(Inst);
 353   }
 354
 355   bool isConditionalBranch(const MCInst &Inst) const override {
 356     // BCCs with the "always" predicate are unconditional branches.
 357     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
 358       return false;
 359     return MCInstrAnalysis::isConditionalBranch(Inst);
 360   }
 361
 362   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
 363                       uint64_t Size, uint64_t &Target) const override {
 364     // We only handle PCRel branches for now.
 365     if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
 366       return false;
 367
 368     int64_t Imm = Inst.getOperand(0).getImm();
 369     // FIXME: This is not right for thumb.
 370     Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
 371     return true;
 372   }
 373 };
 374
 375 }
 376
 377 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
 378   return new ARMMCInstrAnalysis(Info);
 379 }
 380
 381 // Force static initialization.
 382 extern "C" void LLVMInitializeARMTargetMC() {
 383   // Register the MC asm info.
 384   RegisterMCAsmInfoFn X(TheARMLETarget, createARMMCAsmInfo);
 385   RegisterMCAsmInfoFn Y(TheARMBETarget, createARMMCAsmInfo);
 386   RegisterMCAsmInfoFn A(TheThumbLETarget, createARMMCAsmInfo);
 387   RegisterMCAsmInfoFn B(TheThumbBETarget, createARMMCAsmInfo);
 388
 389   // Register the MC codegen info.
 390   TargetRegistry::RegisterMCCodeGenInfo(TheARMLETarget, createARMMCCodeGenInfo);
 391   TargetRegistry::RegisterMCCodeGenInfo(TheARMBETarget, createARMMCCodeGenInfo);
 392   TargetRegistry::RegisterMCCodeGenInfo(TheThumbLETarget,
 393                                         createARMMCCodeGenInfo);
 394   TargetRegistry::RegisterMCCodeGenInfo(TheThumbBETarget,
 395                                         createARMMCCodeGenInfo);
 396
 397   // Register the MC instruction info.
 398   TargetRegistry::RegisterMCInstrInfo(TheARMLETarget, createARMMCInstrInfo);
 399   TargetRegistry::RegisterMCInstrInfo(TheARMBETarget, createARMMCInstrInfo);
 400   TargetRegistry::RegisterMCInstrInfo(TheThumbLETarget, createARMMCInstrInfo);
 401   TargetRegistry::RegisterMCInstrInfo(TheThumbBETarget, createARMMCInstrInfo);
 402
 403   // Register the MC register info.
 404   TargetRegistry::RegisterMCRegInfo(TheARMLETarget, createARMMCRegisterInfo);
 405   TargetRegistry::RegisterMCRegInfo(TheARMBETarget, createARMMCRegisterInfo);
 406   TargetRegistry::RegisterMCRegInfo(TheThumbLETarget, createARMMCRegisterInfo);
 407   TargetRegistry::RegisterMCRegInfo(TheThumbBETarget, createARMMCRegisterInfo);
 408
 409   // Register the MC subtarget info.
 410   TargetRegistry::RegisterMCSubtargetInfo(TheARMLETarget,
 411                                           ARM_MC::createARMMCSubtargetInfo);
 412   TargetRegistry::RegisterMCSubtargetInfo(TheARMBETarget,
 413                                           ARM_MC::createARMMCSubtargetInfo);
 414   TargetRegistry::RegisterMCSubtargetInfo(TheThumbLETarget,
 415                                           ARM_MC::createARMMCSubtargetInfo);
 416   TargetRegistry::RegisterMCSubtargetInfo(TheThumbBETarget,
 417                                           ARM_MC::createARMMCSubtargetInfo);
 418
 419   // Register the MC instruction analyzer.
 420   TargetRegistry::RegisterMCInstrAnalysis(TheARMLETarget,
 421                                           createARMMCInstrAnalysis);
 422   TargetRegistry::RegisterMCInstrAnalysis(TheARMBETarget,
 423                                           createARMMCInstrAnalysis);
 424   TargetRegistry::RegisterMCInstrAnalysis(TheThumbLETarget,
 425                                           createARMMCInstrAnalysis);
 426   TargetRegistry::RegisterMCInstrAnalysis(TheThumbBETarget,
 427                                           createARMMCInstrAnalysis);
 428
 429   // Register the MC Code Emitter
 430   TargetRegistry::RegisterMCCodeEmitter(TheARMLETarget,
 431                                         createARMLEMCCodeEmitter);
 432   TargetRegistry::RegisterMCCodeEmitter(TheARMBETarget,
 433                                         createARMBEMCCodeEmitter);
 434   TargetRegistry::RegisterMCCodeEmitter(TheThumbLETarget,
 435                                         createARMLEMCCodeEmitter);
 436   TargetRegistry::RegisterMCCodeEmitter(TheThumbBETarget,
 437                                         createARMBEMCCodeEmitter);
 438
 439   // Register the asm backend.
 440   TargetRegistry::RegisterMCAsmBackend(TheARMLETarget, createARMLEAsmBackend);
 441   TargetRegistry::RegisterMCAsmBackend(TheARMBETarget, createARMBEAsmBackend);
 442   TargetRegistry::RegisterMCAsmBackend(TheThumbLETarget,
 443                                        createThumbLEAsmBackend);
 444   TargetRegistry::RegisterMCAsmBackend(TheThumbBETarget,
 445                                        createThumbBEAsmBackend);
 446
 447   // Register the object streamer.
 448   TargetRegistry::RegisterMCObjectStreamer(TheARMLETarget, createMCStreamer);
 449   TargetRegistry::RegisterMCObjectStreamer(TheARMBETarget, createMCStreamer);
 450   TargetRegistry::RegisterMCObjectStreamer(TheThumbLETarget, createMCStreamer);
 451   TargetRegistry::RegisterMCObjectStreamer(TheThumbBETarget, createMCStreamer);
 452
 453   // Register the asm streamer.
 454   TargetRegistry::RegisterAsmTargetStreamer(TheARMLETarget,
 455                                             createARMTargetAsmStreamer);
 456   TargetRegistry::RegisterAsmTargetStreamer(TheARMBETarget,
 457                                             createARMTargetAsmStreamer);
 458   TargetRegistry::RegisterAsmTargetStreamer(TheThumbLETarget,
 459                                             createARMTargetAsmStreamer);
 460   TargetRegistry::RegisterAsmTargetStreamer(TheThumbBETarget,
 461                                             createARMTargetAsmStreamer);
 462
 463   // Register the null TargetStreamer.
 464   TargetRegistry::RegisterNullTargetStreamer(TheARMLETarget,
 465                                              createARMNullTargetStreamer);
 466   TargetRegistry::RegisterNullTargetStreamer(TheARMBETarget,
 467                                              createARMNullTargetStreamer);
 468   TargetRegistry::RegisterNullTargetStreamer(TheThumbLETarget,
 469                                              createARMNullTargetStreamer);
 470   TargetRegistry::RegisterNullTargetStreamer(TheThumbBETarget,
 471                                              createARMNullTargetStreamer);
 472
 473   // Register the MCInstPrinter.
 474   TargetRegistry::RegisterMCInstPrinter(TheARMLETarget, createARMMCInstPrinter);
 475   TargetRegistry::RegisterMCInstPrinter(TheARMBETarget, createARMMCInstPrinter);
 476   TargetRegistry::RegisterMCInstPrinter(TheThumbLETarget,
 477                                         createARMMCInstPrinter);
 478   TargetRegistry::RegisterMCInstPrinter(TheThumbBETarget,
 479                                         createARMMCInstPrinter);
 480
 481   // Register the MC relocation info.
 482   TargetRegistry::RegisterMCRelocationInfo(TheARMLETarget,
 483                                            createARMMCRelocationInfo);
 484   TargetRegistry::RegisterMCRelocationInfo(TheARMBETarget,
 485                                            createARMMCRelocationInfo);
 486   TargetRegistry::RegisterMCRelocationInfo(TheThumbLETarget,
 487                                            createARMMCRelocationInfo);
 488   TargetRegistry::RegisterMCRelocationInfo(TheThumbBETarget,
 489                                            createARMMCRelocationInfo);
 490 }