1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides ARM specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "ARMMCTargetDesc.h"
15 #include "ARMMCAsmInfo.h"
16 #include "ARMBaseInfo.h"
17 #include "InstPrinter/ARMInstPrinter.h"
18 #include "llvm/MC/MCCodeGenInfo.h"
19 #include "llvm/MC/MCInstrAnalysis.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
27 #define GET_REGINFO_MC_DESC
28 #include "ARMGenRegisterInfo.inc"
30 #define GET_INSTRINFO_MC_DESC
31 #include "ARMGenInstrInfo.inc"
33 #define GET_SUBTARGETINFO_MC_DESC
34 #include "ARMGenSubtargetInfo.inc"
38 std::string ARM_MC::ParseARMTriple(StringRef TT) {
39 // Set the boolean corresponding to the current target triple, or the default
40 // if one cannot be determined, to true.
41 unsigned Len = TT.size();
44 // FIXME: Enhance Triple helper class to extract ARM version.
46 if (Len >= 5 && TT.substr(0, 4) == "armv")
48 else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
50 if (Len >= 7 && TT[5] == 'v')
54 std::string ARMArchFeature;
56 unsigned SubVer = TT[Idx];
57 if (SubVer >= '7' && SubVer <= '9') {
58 if (Len >= Idx+2 && TT[Idx+1] == 'm') {
59 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
60 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
61 } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
62 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
63 // FeatureT2XtPk, FeatureMClass
64 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
66 // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
67 ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
68 } else if (SubVer == '6') {
69 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
70 ARMArchFeature = "+v6t2";
71 else if (Len >= Idx+2 && TT[Idx+1] == 'm')
72 // v6m: FeatureNoARM, FeatureMClass
73 ARMArchFeature = "+v6t2,+noarm,+mclass";
75 ARMArchFeature = "+v6";
76 } else if (SubVer == '5') {
77 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
78 ARMArchFeature = "+v5te";
80 ARMArchFeature = "+v5t";
81 } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
82 ARMArchFeature = "+v4t";
86 if (ARMArchFeature.empty())
87 ARMArchFeature = "+thumb-mode";
89 ARMArchFeature += ",+thumb-mode";
93 if (TheTriple.getOS() == Triple::NativeClient) {
94 if (ARMArchFeature.empty())
95 ARMArchFeature = "+nacl-mode";
97 ARMArchFeature += ",+nacl-mode";
100 return ARMArchFeature;
103 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
105 std::string ArchFS = ARM_MC::ParseARMTriple(TT);
108 ArchFS = ArchFS + "," + FS.str();
113 MCSubtargetInfo *X = new MCSubtargetInfo();
114 InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
118 static MCInstrInfo *createARMMCInstrInfo() {
119 MCInstrInfo *X = new MCInstrInfo();
120 InitARMMCInstrInfo(X);
124 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
125 MCRegisterInfo *X = new MCRegisterInfo();
126 InitARMMCRegisterInfo(X, ARM::LR);
130 static MCAsmInfo *createARMMCAsmInfo(const Target &T, StringRef TT) {
131 Triple TheTriple(TT);
133 if (TheTriple.isOSDarwin())
134 return new ARMMCAsmInfoDarwin();
136 return new ARMELFMCAsmInfo();
139 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
140 CodeModel::Model CM) {
141 MCCodeGenInfo *X = new MCCodeGenInfo();
142 if (RM == Reloc::Default)
143 RM = Reloc::DynamicNoPIC;
144 X->InitMCCodeGenInfo(RM, CM);
148 // This is duplicated code. Refactor this.
149 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
150 MCContext &Ctx, MCAsmBackend &MAB,
152 MCCodeEmitter *Emitter,
155 Triple TheTriple(TT);
157 if (TheTriple.isOSDarwin())
158 return createMachOStreamer(Ctx, MAB, OS, Emitter, RelaxAll);
160 if (TheTriple.isOSWindows()) {
161 llvm_unreachable("ARM does not support Windows COFF format");
165 return createELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll, NoExecStack);
168 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
169 unsigned SyntaxVariant,
170 const MCAsmInfo &MAI,
171 const MCSubtargetInfo &STI) {
172 if (SyntaxVariant == 0)
173 return new ARMInstPrinter(MAI, STI);
179 class ARMMCInstrAnalysis : public MCInstrAnalysis {
181 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
183 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
184 // BCCs with the "always" predicate are unconditional branches.
185 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
187 return MCInstrAnalysis::isUnconditionalBranch(Inst);
190 virtual bool isConditionalBranch(const MCInst &Inst) const {
191 // BCCs with the "always" predicate are unconditional branches.
192 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
194 return MCInstrAnalysis::isConditionalBranch(Inst);
197 uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr,
198 uint64_t Size) const {
199 // We only handle PCRel branches for now.
200 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
203 int64_t Imm = Inst.getOperand(0).getImm();
204 // FIXME: This is not right for thumb.
205 return Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
211 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
212 return new ARMMCInstrAnalysis(Info);
215 // Force static initialization.
216 extern "C" void LLVMInitializeARMTargetMC() {
217 // Register the MC asm info.
218 RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
219 RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
221 // Register the MC codegen info.
222 TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
223 TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
225 // Register the MC instruction info.
226 TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
227 TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
229 // Register the MC register info.
230 TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
231 TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
233 // Register the MC subtarget info.
234 TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
235 ARM_MC::createARMMCSubtargetInfo);
236 TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
237 ARM_MC::createARMMCSubtargetInfo);
239 // Register the MC instruction analyzer.
240 TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
241 createARMMCInstrAnalysis);
242 TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
243 createARMMCInstrAnalysis);
245 // Register the MC Code Emitter
246 TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
247 TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
249 // Register the asm backend.
250 TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
251 TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
253 // Register the object streamer.
254 TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
255 TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
257 // Register the MCInstPrinter.
258 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
259 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);