1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides ARM specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInfo.h"
15 #include "ARMMCAsmInfo.h"
16 #include "ARMMCTargetDesc.h"
17 #include "InstPrinter/ARMInstPrinter.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCELFStreamer.h"
21 #include "llvm/MC/MCInstrAnalysis.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
31 #define GET_REGINFO_MC_DESC
32 #include "ARMGenRegisterInfo.inc"
34 static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
36 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
37 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
38 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
39 // Checks for the deprecated CP15ISB encoding:
40 // mcr p15, #0, rX, c7, c5, #4
41 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
42 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
43 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
44 Info = "deprecated since v7, use 'isb'";
48 // Checks for the deprecated CP15DSB encoding:
49 // mcr p15, #0, rX, c7, c10, #4
50 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
51 Info = "deprecated since v7, use 'dsb'";
55 // Checks for the deprecated CP15DMB encoding:
56 // mcr p15, #0, rX, c7, c10, #5
57 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
58 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
59 Info = "deprecated since v7, use 'dmb'";
66 static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
68 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
69 MI.getOperand(1).getImm() != 8) {
70 Info = "applying IT instruction to more than one subsequent instruction is "
78 static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
80 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
81 "cannot predicate thumb instructions");
83 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
84 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
85 assert(MI.getOperand(OI).isReg() && "expected register");
86 if (MI.getOperand(OI).getReg() == ARM::SP ||
87 MI.getOperand(OI).getReg() == ARM::PC) {
88 Info = "use of SP or PC in the list is deprecated";
95 static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
97 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
98 "cannot predicate thumb instructions");
100 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
101 bool ListContainsPC = false, ListContainsLR = false;
102 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
103 assert(MI.getOperand(OI).isReg() && "expected register");
104 switch (MI.getOperand(OI).getReg()) {
108 ListContainsLR = true;
111 ListContainsPC = true;
114 Info = "use of SP in the list is deprecated";
119 if (ListContainsPC && ListContainsLR) {
120 Info = "use of LR and PC simultaneously in the list is deprecated";
127 #define GET_INSTRINFO_MC_DESC
128 #include "ARMGenInstrInfo.inc"
130 #define GET_SUBTARGETINFO_MC_DESC
131 #include "ARMGenSubtargetInfo.inc"
133 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
135 TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb;
137 bool NoCPU = CPU == "generic" || CPU.empty();
138 std::string ARMArchFeature;
139 switch (TT.getSubArch()) {
141 llvm_unreachable("invalid sub-architecture for ARM");
142 case Triple::ARMSubArch_v8:
144 // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP,
145 // FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
146 // FeatureT2XtPk, FeatureCrypto, FeatureCRC
147 ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
148 "+trustzone,+t2xtpk,+crypto,+crc";
150 // Use CPU to figure out the exact features
151 ARMArchFeature = "+v8";
153 case Triple::ARMSubArch_v8_1a:
155 // v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP,
156 // FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
157 // FeatureT2XtPk, FeatureCrypto, FeatureCRC, FeatureV8_1a
158 ARMArchFeature = "+v8.1a,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
159 "+trustzone,+t2xtpk,+crypto,+crc";
161 // Use CPU to figure out the exact features
162 ARMArchFeature = "+v8.1a";
164 case Triple::ARMSubArch_v7m:
167 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
168 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
170 // Use CPU to figure out the exact features.
171 ARMArchFeature = "+v7";
173 case Triple::ARMSubArch_v7em:
175 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSP,
176 // FeatureT2XtPk, FeatureMClass
177 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,+t2xtpk,+mclass";
179 // Use CPU to figure out the exact features.
180 ARMArchFeature = "+v7";
182 case Triple::ARMSubArch_v7s:
184 // v7s: FeatureNEON, FeatureDB, FeatureDSP, FeatureHasRAS
186 ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
188 // Use CPU to figure out the exact features.
189 ARMArchFeature = "+v7";
191 case Triple::ARMSubArch_v7:
192 // v7 CPUs have lots of different feature sets. If no CPU is specified,
193 // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
194 // the "minimum" feature set and use CPU string to figure out the exact
197 // v7a: FeatureNEON, FeatureDB, FeatureDSP, FeatureT2XtPk
198 ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
200 // Use CPU to figure out the exact features.
201 ARMArchFeature = "+v7";
203 case Triple::ARMSubArch_v6t2:
204 ARMArchFeature = "+v6t2";
206 case Triple::ARMSubArch_v6k:
207 ARMArchFeature = "+v6k";
209 case Triple::ARMSubArch_v6m:
212 // v6m: FeatureNoARM, FeatureMClass
213 ARMArchFeature = "+v6m,+noarm,+mclass";
215 ARMArchFeature = "+v6";
217 case Triple::ARMSubArch_v6:
218 ARMArchFeature = "+v6";
220 case Triple::ARMSubArch_v5te:
221 ARMArchFeature = "+v5te";
223 case Triple::ARMSubArch_v5:
224 ARMArchFeature = "+v5t";
226 case Triple::ARMSubArch_v4t:
227 ARMArchFeature = "+v4t";
229 case Triple::NoSubArch:
234 if (ARMArchFeature.empty())
235 ARMArchFeature = "+thumb-mode";
237 ARMArchFeature += ",+thumb-mode";
241 if (ARMArchFeature.empty())
242 ARMArchFeature = "+nacl-trap";
244 ARMArchFeature += ",+nacl-trap";
247 return ARMArchFeature;
250 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
251 StringRef CPU, StringRef FS) {
252 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
255 ArchFS = (Twine(ArchFS) + "," + FS).str();
260 return createARMMCSubtargetInfoImpl(TT, CPU, ArchFS);
263 static MCInstrInfo *createARMMCInstrInfo() {
264 MCInstrInfo *X = new MCInstrInfo();
265 InitARMMCInstrInfo(X);
269 static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
270 MCRegisterInfo *X = new MCRegisterInfo();
271 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
275 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
276 const Triple &TheTriple) {
278 if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
279 MAI = new ARMMCAsmInfoDarwin(TheTriple);
280 else if (TheTriple.isWindowsMSVCEnvironment())
281 MAI = new ARMCOFFMCAsmInfoMicrosoft();
282 else if (TheTriple.isOSWindows())
283 MAI = new ARMCOFFMCAsmInfoGNU();
285 MAI = new ARMELFMCAsmInfo(TheTriple);
287 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
288 MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
293 static MCCodeGenInfo *createARMMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
295 CodeGenOpt::Level OL) {
296 MCCodeGenInfo *X = new MCCodeGenInfo();
297 if (RM == Reloc::Default) {
298 // Default relocation model on Darwin is PIC, not DynamicNoPIC.
299 RM = TT.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
301 X->initMCCodeGenInfo(RM, CM, OL);
305 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
306 MCAsmBackend &MAB, raw_pwrite_stream &OS,
307 MCCodeEmitter *Emitter, bool RelaxAll) {
308 return createARMELFStreamer(Ctx, MAB, OS, Emitter, false,
309 T.getArch() == Triple::thumb);
312 static MCStreamer *createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB,
313 raw_pwrite_stream &OS,
314 MCCodeEmitter *Emitter, bool RelaxAll,
315 bool DWARFMustBeAtTheEnd) {
316 return createMachOStreamer(Ctx, MAB, OS, Emitter, false, DWARFMustBeAtTheEnd);
319 static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
320 unsigned SyntaxVariant,
321 const MCAsmInfo &MAI,
322 const MCInstrInfo &MII,
323 const MCRegisterInfo &MRI) {
324 if (SyntaxVariant == 0)
325 return new ARMInstPrinter(MAI, MII, MRI);
329 static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT,
331 if (TT.isOSBinFormatMachO())
332 return createARMMachORelocationInfo(Ctx);
333 // Default to the stock relocation info.
334 return llvm::createMCRelocationInfo(TT, Ctx);
339 class ARMMCInstrAnalysis : public MCInstrAnalysis {
341 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
343 bool isUnconditionalBranch(const MCInst &Inst) const override {
344 // BCCs with the "always" predicate are unconditional branches.
345 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
347 return MCInstrAnalysis::isUnconditionalBranch(Inst);
350 bool isConditionalBranch(const MCInst &Inst) const override {
351 // BCCs with the "always" predicate are unconditional branches.
352 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
354 return MCInstrAnalysis::isConditionalBranch(Inst);
357 bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
358 uint64_t Size, uint64_t &Target) const override {
359 // We only handle PCRel branches for now.
360 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
363 int64_t Imm = Inst.getOperand(0).getImm();
364 // FIXME: This is not right for thumb.
365 Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
372 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
373 return new ARMMCInstrAnalysis(Info);
376 // Force static initialization.
377 extern "C" void LLVMInitializeARMTargetMC() {
378 for (Target *T : {&TheARMLETarget, &TheARMBETarget, &TheThumbLETarget,
379 &TheThumbBETarget}) {
380 // Register the MC asm info.
381 RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);
383 // Register the MC codegen info.
384 TargetRegistry::RegisterMCCodeGenInfo(*T, createARMMCCodeGenInfo);
386 // Register the MC instruction info.
387 TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo);
389 // Register the MC register info.
390 TargetRegistry::RegisterMCRegInfo(*T, createARMMCRegisterInfo);
392 // Register the MC subtarget info.
393 TargetRegistry::RegisterMCSubtargetInfo(*T,
394 ARM_MC::createARMMCSubtargetInfo);
396 // Register the MC instruction analyzer.
397 TargetRegistry::RegisterMCInstrAnalysis(*T, createARMMCInstrAnalysis);
399 TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
400 TargetRegistry::RegisterCOFFStreamer(*T, createARMWinCOFFStreamer);
401 TargetRegistry::RegisterMachOStreamer(*T, createARMMachOStreamer);
403 // Register the obj target streamer.
404 TargetRegistry::RegisterObjectTargetStreamer(*T,
405 createARMObjectTargetStreamer);
407 // Register the asm streamer.
408 TargetRegistry::RegisterAsmTargetStreamer(*T, createARMTargetAsmStreamer);
410 // Register the null TargetStreamer.
411 TargetRegistry::RegisterNullTargetStreamer(*T, createARMNullTargetStreamer);
413 // Register the MCInstPrinter.
414 TargetRegistry::RegisterMCInstPrinter(*T, createARMMCInstPrinter);
416 // Register the MC relocation info.
417 TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo);
420 // Register the MC Code Emitter
421 for (Target *T : {&TheARMLETarget, &TheThumbLETarget})
422 TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter);
423 for (Target *T : {&TheARMBETarget, &TheThumbBETarget})
424 TargetRegistry::RegisterMCCodeEmitter(*T, createARMBEMCCodeEmitter);
426 // Register the asm backend.
427 TargetRegistry::RegisterMCAsmBackend(TheARMLETarget, createARMLEAsmBackend);
428 TargetRegistry::RegisterMCAsmBackend(TheARMBETarget, createARMBEAsmBackend);
429 TargetRegistry::RegisterMCAsmBackend(TheThumbLETarget,
430 createThumbLEAsmBackend);
431 TargetRegistry::RegisterMCAsmBackend(TheThumbBETarget,
432 createThumbBEAsmBackend);