1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #include "MCTargetDesc/ARMMCTargetDesc.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMFixupKinds.h"
18 #include "MCTargetDesc/ARMMCExpr.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCExpr.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
33 #define DEBUG_TYPE "mccodeemitter"
35 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
36 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
39 class ARMMCCodeEmitter : public MCCodeEmitter {
40 ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
41 void operator=(const ARMMCCodeEmitter &) = delete;
42 const MCInstrInfo &MCII;
47 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
48 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
51 ~ARMMCCodeEmitter() override {}
53 bool isThumb(const MCSubtargetInfo &STI) const {
54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
56 bool isThumb2(const MCSubtargetInfo &STI) const {
57 return isThumb(STI) && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
59 bool isTargetMachO(const MCSubtargetInfo &STI) const {
60 Triple TT(STI.getTargetTriple());
61 return TT.isOSBinFormatMachO();
64 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
66 // getBinaryCodeForInstr - TableGen'erated function for getting the
67 // binary encoding for an instruction.
68 uint64_t getBinaryCodeForInstr(const MCInst &MI,
69 SmallVectorImpl<MCFixup> &Fixups,
70 const MCSubtargetInfo &STI) const;
72 /// getMachineOpValue - Return binary encoding of operand. If the machine
73 /// operand requires relocation, record the relocation and return zero.
74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
75 SmallVectorImpl<MCFixup> &Fixups,
76 const MCSubtargetInfo &STI) const;
78 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
79 /// the specified operand. This is used for operands with :lower16: and
80 /// :upper16: prefixes.
81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
82 SmallVectorImpl<MCFixup> &Fixups,
83 const MCSubtargetInfo &STI) const;
85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
86 unsigned &Reg, unsigned &Imm,
87 SmallVectorImpl<MCFixup> &Fixups,
88 const MCSubtargetInfo &STI) const;
90 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
93 SmallVectorImpl<MCFixup> &Fixups,
94 const MCSubtargetInfo &STI) const;
96 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
97 /// BLX branch target.
98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
99 SmallVectorImpl<MCFixup> &Fixups,
100 const MCSubtargetInfo &STI) const;
102 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
104 SmallVectorImpl<MCFixup> &Fixups,
105 const MCSubtargetInfo &STI) const;
107 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
109 SmallVectorImpl<MCFixup> &Fixups,
110 const MCSubtargetInfo &STI) const;
112 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
114 SmallVectorImpl<MCFixup> &Fixups,
115 const MCSubtargetInfo &STI) const;
117 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120 SmallVectorImpl<MCFixup> &Fixups,
121 const MCSubtargetInfo &STI) const;
123 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
124 /// immediate Thumb2 direct branch target.
125 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
126 SmallVectorImpl<MCFixup> &Fixups,
127 const MCSubtargetInfo &STI) const;
129 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
131 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
132 SmallVectorImpl<MCFixup> &Fixups,
133 const MCSubtargetInfo &STI) const;
134 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
135 SmallVectorImpl<MCFixup> &Fixups,
136 const MCSubtargetInfo &STI) const;
137 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
138 SmallVectorImpl<MCFixup> &Fixups,
139 const MCSubtargetInfo &STI) const;
141 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
142 /// ADR label target.
143 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
144 SmallVectorImpl<MCFixup> &Fixups,
145 const MCSubtargetInfo &STI) const;
146 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
147 SmallVectorImpl<MCFixup> &Fixups,
148 const MCSubtargetInfo &STI) const;
149 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
150 SmallVectorImpl<MCFixup> &Fixups,
151 const MCSubtargetInfo &STI) const;
154 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
156 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
157 SmallVectorImpl<MCFixup> &Fixups,
158 const MCSubtargetInfo &STI) const;
160 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
161 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
162 SmallVectorImpl<MCFixup> &Fixups,
163 const MCSubtargetInfo &STI) const;
165 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
167 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
168 SmallVectorImpl<MCFixup> &Fixups,
169 const MCSubtargetInfo &STI) const;
171 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
173 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
174 SmallVectorImpl<MCFixup> &Fixups,
175 const MCSubtargetInfo &STI) const;
177 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
179 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
180 SmallVectorImpl<MCFixup> &Fixups,
181 const MCSubtargetInfo &STI) const;
184 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
185 /// operand as needed by load/store instructions.
186 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
187 SmallVectorImpl<MCFixup> &Fixups,
188 const MCSubtargetInfo &STI) const;
190 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
191 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
192 SmallVectorImpl<MCFixup> &Fixups,
193 const MCSubtargetInfo &STI) const {
194 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
196 default: llvm_unreachable("Unknown addressing sub-mode!");
197 case ARM_AM::da: return 0;
198 case ARM_AM::ia: return 1;
199 case ARM_AM::db: return 2;
200 case ARM_AM::ib: return 3;
203 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
205 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
207 case ARM_AM::no_shift:
208 case ARM_AM::lsl: return 0;
209 case ARM_AM::lsr: return 1;
210 case ARM_AM::asr: return 2;
212 case ARM_AM::rrx: return 3;
214 llvm_unreachable("Invalid ShiftOpc!");
217 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
218 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
219 SmallVectorImpl<MCFixup> &Fixups,
220 const MCSubtargetInfo &STI) const;
222 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
223 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
224 SmallVectorImpl<MCFixup> &Fixups,
225 const MCSubtargetInfo &STI) const;
227 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
228 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
229 SmallVectorImpl<MCFixup> &Fixups,
230 const MCSubtargetInfo &STI) const;
232 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
233 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
234 SmallVectorImpl<MCFixup> &Fixups,
235 const MCSubtargetInfo &STI) const;
237 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
238 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
239 SmallVectorImpl<MCFixup> &Fixups,
240 const MCSubtargetInfo &STI) const;
242 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
244 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
245 SmallVectorImpl<MCFixup> &Fixups,
246 const MCSubtargetInfo &STI) const;
248 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
249 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
250 SmallVectorImpl<MCFixup> &Fixups,
251 const MCSubtargetInfo &STI) const;
253 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
254 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
255 SmallVectorImpl<MCFixup> &Fixups,
256 const MCSubtargetInfo &STI) const;
258 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
259 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
260 SmallVectorImpl<MCFixup> &Fixups,
261 const MCSubtargetInfo &STI) const;
263 /// getCCOutOpValue - Return encoding of the 's' bit.
264 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
265 SmallVectorImpl<MCFixup> &Fixups,
266 const MCSubtargetInfo &STI) const {
267 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
269 return MI.getOperand(Op).getReg() == ARM::CPSR;
272 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
273 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
274 SmallVectorImpl<MCFixup> &Fixups,
275 const MCSubtargetInfo &STI) const {
277 const MCOperand &MO = MI.getOperand(Op);
279 // We expect MO to be an immediate or an expression,
280 // if it is an immediate - that's fine, just encode the value.
281 // Otherwise - create a Fixup.
283 const MCExpr *Expr = MO.getExpr();
284 // In instruction code this value always encoded as lowest 12 bits,
285 // so we don't have to perform any specific adjustments.
286 // Due to requirements of relocatable records we have to use FK_Data_4.
287 // See ARMELFObjectWriter::ExplicitRelSym and
288 // ARMELFObjectWriter::GetRelocTypeInner for more details.
289 MCFixupKind Kind = MCFixupKind(FK_Data_4);
290 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
294 unsigned SoImm = MO.getImm();
295 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
296 assert(SoImmVal != -1 && "Not a valid so_imm value!");
298 // Encode rotate_imm.
299 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
300 << ARMII::SoRotImmShift;
303 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
307 unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
308 SmallVectorImpl<MCFixup> &Fixups,
309 const MCSubtargetInfo &ST) const {
310 const MCOperand &MO = MI.getOperand(Op);
312 // Support for fixups (MCFixup)
314 const MCExpr *Expr = MO.getExpr();
315 // In instruction code this value always encoded as lowest 12 bits,
316 // so we don't have to perform any specific adjustments.
317 // Due to requirements of relocatable records we have to use FK_Data_4.
318 // See ARMELFObjectWriter::ExplicitRelSym and
319 // ARMELFObjectWriter::GetRelocTypeInner for more details.
320 MCFixupKind Kind = MCFixupKind(FK_Data_4);
321 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
325 // Immediate is already in its encoded format
329 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
330 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
331 SmallVectorImpl<MCFixup> &Fixups,
332 const MCSubtargetInfo &STI) const {
333 unsigned SoImm = MI.getOperand(Op).getImm();
334 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
335 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
339 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
340 SmallVectorImpl<MCFixup> &Fixups,
341 const MCSubtargetInfo &STI) const;
342 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
343 SmallVectorImpl<MCFixup> &Fixups,
344 const MCSubtargetInfo &STI) const;
345 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
346 SmallVectorImpl<MCFixup> &Fixups,
347 const MCSubtargetInfo &STI) const;
348 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
349 SmallVectorImpl<MCFixup> &Fixups,
350 const MCSubtargetInfo &STI) const;
352 /// getSORegOpValue - Return an encoded so_reg shifted register value.
353 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
354 SmallVectorImpl<MCFixup> &Fixups,
355 const MCSubtargetInfo &STI) const;
356 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
357 SmallVectorImpl<MCFixup> &Fixups,
358 const MCSubtargetInfo &STI) const;
359 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
360 SmallVectorImpl<MCFixup> &Fixups,
361 const MCSubtargetInfo &STI) const;
363 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
364 SmallVectorImpl<MCFixup> &Fixups,
365 const MCSubtargetInfo &STI) const {
366 return 64 - MI.getOperand(Op).getImm();
369 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
370 SmallVectorImpl<MCFixup> &Fixups,
371 const MCSubtargetInfo &STI) const;
373 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
374 SmallVectorImpl<MCFixup> &Fixups,
375 const MCSubtargetInfo &STI) const;
376 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
377 SmallVectorImpl<MCFixup> &Fixups,
378 const MCSubtargetInfo &STI) const;
379 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
380 SmallVectorImpl<MCFixup> &Fixups,
381 const MCSubtargetInfo &STI) const;
382 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
383 SmallVectorImpl<MCFixup> &Fixups,
384 const MCSubtargetInfo &STI) const;
385 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
386 SmallVectorImpl<MCFixup> &Fixups,
387 const MCSubtargetInfo &STI) const;
389 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
390 SmallVectorImpl<MCFixup> &Fixups,
391 const MCSubtargetInfo &STI) const;
392 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
393 SmallVectorImpl<MCFixup> &Fixups,
394 const MCSubtargetInfo &STI) const;
395 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
396 SmallVectorImpl<MCFixup> &Fixups,
397 const MCSubtargetInfo &STI) const;
398 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
399 SmallVectorImpl<MCFixup> &Fixups,
400 const MCSubtargetInfo &STI) const;
402 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
403 SmallVectorImpl<MCFixup> &Fixups,
404 const MCSubtargetInfo &STI) const;
406 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
407 unsigned EncodedValue,
408 const MCSubtargetInfo &STI) const;
409 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
410 unsigned EncodedValue,
411 const MCSubtargetInfo &STI) const;
412 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
413 unsigned EncodedValue,
414 const MCSubtargetInfo &STI) const;
415 unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
416 unsigned EncodedValue,
417 const MCSubtargetInfo &STI) const;
419 unsigned VFPThumb2PostEncoder(const MCInst &MI,
420 unsigned EncodedValue,
421 const MCSubtargetInfo &STI) const;
423 void EmitByte(unsigned char C, raw_ostream &OS) const {
427 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
428 // Output the constant in little endian byte order.
429 for (unsigned i = 0; i != Size; ++i) {
430 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
431 EmitByte((Val >> Shift) & 0xff, OS);
435 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
436 SmallVectorImpl<MCFixup> &Fixups,
437 const MCSubtargetInfo &STI) const override;
440 } // end anonymous namespace
442 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
443 const MCRegisterInfo &MRI,
445 return new ARMMCCodeEmitter(MCII, Ctx, true);
448 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
449 const MCRegisterInfo &MRI,
451 return new ARMMCCodeEmitter(MCII, Ctx, false);
454 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
455 /// instructions, and rewrite them to their Thumb2 form if we are currently in
457 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
458 unsigned EncodedValue,
459 const MCSubtargetInfo &STI) const {
461 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
462 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
464 unsigned Bit24 = EncodedValue & 0x01000000;
465 unsigned Bit28 = Bit24 << 4;
466 EncodedValue &= 0xEFFFFFFF;
467 EncodedValue |= Bit28;
468 EncodedValue |= 0x0F000000;
474 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
475 /// instructions, and rewrite them to their Thumb2 form if we are currently in
477 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
478 unsigned EncodedValue,
479 const MCSubtargetInfo &STI) const {
481 EncodedValue &= 0xF0FFFFFF;
482 EncodedValue |= 0x09000000;
488 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
489 /// instructions, and rewrite them to their Thumb2 form if we are currently in
491 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
492 unsigned EncodedValue,
493 const MCSubtargetInfo &STI) const {
495 EncodedValue &= 0x00FFFFFF;
496 EncodedValue |= 0xEE000000;
502 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
503 /// if we are in Thumb2.
504 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
505 unsigned EncodedValue,
506 const MCSubtargetInfo &STI) const {
508 EncodedValue |= 0xC000000; // Set bits 27-26
514 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
515 /// them to their Thumb2 form if we are currently in Thumb2 mode.
516 unsigned ARMMCCodeEmitter::
517 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
518 const MCSubtargetInfo &STI) const {
520 EncodedValue &= 0x0FFFFFFF;
521 EncodedValue |= 0xE0000000;
526 /// getMachineOpValue - Return binary encoding of operand. If the machine
527 /// operand requires relocation, record the relocation and return zero.
528 unsigned ARMMCCodeEmitter::
529 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
530 SmallVectorImpl<MCFixup> &Fixups,
531 const MCSubtargetInfo &STI) const {
533 unsigned Reg = MO.getReg();
534 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
536 // Q registers are encoded as 2x their register number.
540 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
541 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
542 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
543 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
546 } else if (MO.isImm()) {
547 return static_cast<unsigned>(MO.getImm());
548 } else if (MO.isFPImm()) {
549 return static_cast<unsigned>(APFloat(MO.getFPImm())
550 .bitcastToAPInt().getHiBits(32).getLimitedValue());
553 llvm_unreachable("Unable to encode MCOperand!");
556 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
557 bool ARMMCCodeEmitter::
558 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
559 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
560 const MCSubtargetInfo &STI) const {
561 const MCOperand &MO = MI.getOperand(OpIdx);
562 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
564 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
566 int32_t SImm = MO1.getImm();
569 // Special value for #-0
570 if (SImm == INT32_MIN) {
575 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
585 /// getBranchTargetOpValue - Helper function to get the branch target operand,
586 /// which is either an immediate or requires a fixup.
587 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
589 SmallVectorImpl<MCFixup> &Fixups,
590 const MCSubtargetInfo &STI) {
591 const MCOperand &MO = MI.getOperand(OpIdx);
593 // If the destination is an immediate, we have nothing to do.
594 if (MO.isImm()) return MO.getImm();
595 assert(MO.isExpr() && "Unexpected branch target type!");
596 const MCExpr *Expr = MO.getExpr();
597 MCFixupKind Kind = MCFixupKind(FixupKind);
598 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
600 // All of the information is in the fixup.
604 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
605 // determined by negating them and XOR'ing them with bit 23.
606 static int32_t encodeThumbBLOffset(int32_t offset) {
608 uint32_t S = (offset & 0x800000) >> 23;
609 uint32_t J1 = (offset & 0x400000) >> 22;
610 uint32_t J2 = (offset & 0x200000) >> 21;
623 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
624 uint32_t ARMMCCodeEmitter::
625 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
626 SmallVectorImpl<MCFixup> &Fixups,
627 const MCSubtargetInfo &STI) const {
628 const MCOperand MO = MI.getOperand(OpIdx);
630 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
632 return encodeThumbBLOffset(MO.getImm());
635 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
636 /// BLX branch target.
637 uint32_t ARMMCCodeEmitter::
638 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
639 SmallVectorImpl<MCFixup> &Fixups,
640 const MCSubtargetInfo &STI) const {
641 const MCOperand MO = MI.getOperand(OpIdx);
643 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
645 return encodeThumbBLOffset(MO.getImm());
648 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
649 uint32_t ARMMCCodeEmitter::
650 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
651 SmallVectorImpl<MCFixup> &Fixups,
652 const MCSubtargetInfo &STI) const {
653 const MCOperand MO = MI.getOperand(OpIdx);
655 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
657 return (MO.getImm() >> 1);
660 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
661 uint32_t ARMMCCodeEmitter::
662 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
663 SmallVectorImpl<MCFixup> &Fixups,
664 const MCSubtargetInfo &STI) const {
665 const MCOperand MO = MI.getOperand(OpIdx);
667 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
669 return (MO.getImm() >> 1);
672 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
673 uint32_t ARMMCCodeEmitter::
674 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
675 SmallVectorImpl<MCFixup> &Fixups,
676 const MCSubtargetInfo &STI) const {
677 const MCOperand MO = MI.getOperand(OpIdx);
679 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
680 return (MO.getImm() >> 1);
683 /// Return true if this branch has a non-always predication
684 static bool HasConditionalBranch(const MCInst &MI) {
685 int NumOp = MI.getNumOperands();
687 for (int i = 0; i < NumOp-1; ++i) {
688 const MCOperand &MCOp1 = MI.getOperand(i);
689 const MCOperand &MCOp2 = MI.getOperand(i + 1);
690 if (MCOp1.isImm() && MCOp2.isReg() &&
691 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
692 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
700 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
702 uint32_t ARMMCCodeEmitter::
703 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
704 SmallVectorImpl<MCFixup> &Fixups,
705 const MCSubtargetInfo &STI) const {
706 // FIXME: This really, really shouldn't use TargetMachine. We don't want
707 // coupling between MC and TM anywhere we can help it.
710 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
711 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
714 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
716 uint32_t ARMMCCodeEmitter::
717 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
718 SmallVectorImpl<MCFixup> &Fixups,
719 const MCSubtargetInfo &STI) const {
720 const MCOperand MO = MI.getOperand(OpIdx);
722 if (HasConditionalBranch(MI))
723 return ::getBranchTargetOpValue(MI, OpIdx,
724 ARM::fixup_arm_condbranch, Fixups, STI);
725 return ::getBranchTargetOpValue(MI, OpIdx,
726 ARM::fixup_arm_uncondbranch, Fixups, STI);
729 return MO.getImm() >> 2;
732 uint32_t ARMMCCodeEmitter::
733 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
734 SmallVectorImpl<MCFixup> &Fixups,
735 const MCSubtargetInfo &STI) const {
736 const MCOperand MO = MI.getOperand(OpIdx);
738 if (HasConditionalBranch(MI))
739 return ::getBranchTargetOpValue(MI, OpIdx,
740 ARM::fixup_arm_condbl, Fixups, STI);
741 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
744 return MO.getImm() >> 2;
747 uint32_t ARMMCCodeEmitter::
748 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
749 SmallVectorImpl<MCFixup> &Fixups,
750 const MCSubtargetInfo &STI) const {
751 const MCOperand MO = MI.getOperand(OpIdx);
753 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
755 return MO.getImm() >> 1;
758 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
759 /// immediate branch target.
760 uint32_t ARMMCCodeEmitter::
761 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
762 SmallVectorImpl<MCFixup> &Fixups,
763 const MCSubtargetInfo &STI) const {
765 const MCOperand MO = MI.getOperand(OpIdx);
768 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
770 Val = MO.getImm() >> 1;
772 bool I = (Val & 0x800000);
773 bool J1 = (Val & 0x400000);
774 bool J2 = (Val & 0x200000);
788 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
789 /// ADR label target.
790 uint32_t ARMMCCodeEmitter::
791 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
792 SmallVectorImpl<MCFixup> &Fixups,
793 const MCSubtargetInfo &STI) const {
794 const MCOperand MO = MI.getOperand(OpIdx);
796 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
798 int64_t offset = MO.getImm();
799 uint32_t Val = 0x2000;
802 if (offset == INT32_MIN) {
805 } else if (offset < 0) {
808 SoImmVal = ARM_AM::getSOImmVal(offset);
812 SoImmVal = ARM_AM::getSOImmVal(offset);
815 SoImmVal = ARM_AM::getSOImmVal(offset);
819 SoImmVal = ARM_AM::getSOImmVal(offset);
823 assert(SoImmVal != -1 && "Not a valid so_imm value!");
829 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
831 uint32_t ARMMCCodeEmitter::
832 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
833 SmallVectorImpl<MCFixup> &Fixups,
834 const MCSubtargetInfo &STI) const {
835 const MCOperand MO = MI.getOperand(OpIdx);
837 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
839 int32_t Val = MO.getImm();
840 if (Val == INT32_MIN)
849 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
851 uint32_t ARMMCCodeEmitter::
852 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
853 SmallVectorImpl<MCFixup> &Fixups,
854 const MCSubtargetInfo &STI) const {
855 const MCOperand MO = MI.getOperand(OpIdx);
857 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
862 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
864 uint32_t ARMMCCodeEmitter::
865 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
866 SmallVectorImpl<MCFixup> &,
867 const MCSubtargetInfo &STI) const {
871 const MCOperand &MO1 = MI.getOperand(OpIdx);
872 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
873 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
874 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
875 return (Rm << 3) | Rn;
878 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
879 uint32_t ARMMCCodeEmitter::
880 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
881 SmallVectorImpl<MCFixup> &Fixups,
882 const MCSubtargetInfo &STI) const {
884 // {12} = (U)nsigned (add == '1', sub == '0')
888 // If The first operand isn't a register, we have a label reference.
889 const MCOperand &MO = MI.getOperand(OpIdx);
891 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
895 const MCExpr *Expr = MO.getExpr();
896 isAdd = false ; // 'U' bit is set as part of the fixup.
900 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
902 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
903 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
905 ++MCNumCPRelocations;
908 int32_t Offset = MO.getImm();
909 if (Offset == INT32_MIN) {
912 } else if (Offset < 0) {
919 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
921 uint32_t Binary = Imm12 & 0xfff;
922 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
925 Binary |= (Reg << 13);
929 /// getT2Imm8s4OpValue - Return encoding info for
930 /// '+/- imm8<<2' operand.
931 uint32_t ARMMCCodeEmitter::
932 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
933 SmallVectorImpl<MCFixup> &Fixups,
934 const MCSubtargetInfo &STI) const {
935 // FIXME: The immediate operand should have already been encoded like this
936 // before ever getting here. The encoder method should just need to combine
937 // the MI operands for the register and the offset into a single
938 // representation for the complex operand in the .td file. This isn't just
939 // style, unfortunately. As-is, we can't represent the distinct encoding
942 // {8} = (U)nsigned (add == '1', sub == '0')
944 int32_t Imm8 = MI.getOperand(OpIdx).getImm();
945 bool isAdd = Imm8 >= 0;
947 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
949 Imm8 = -(uint32_t)Imm8;
954 uint32_t Binary = Imm8 & 0xff;
955 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
961 /// getT2AddrModeImm8s4OpValue - Return encoding info for
962 /// 'reg +/- imm8<<2' operand.
963 uint32_t ARMMCCodeEmitter::
964 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
965 SmallVectorImpl<MCFixup> &Fixups,
966 const MCSubtargetInfo &STI) const {
968 // {8} = (U)nsigned (add == '1', sub == '0')
972 // If The first operand isn't a register, we have a label reference.
973 const MCOperand &MO = MI.getOperand(OpIdx);
975 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
977 isAdd = false ; // 'U' bit is set as part of the fixup.
979 assert(MO.isExpr() && "Unexpected machine operand type!");
980 const MCExpr *Expr = MO.getExpr();
981 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
982 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
984 ++MCNumCPRelocations;
986 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
988 // FIXME: The immediate operand should have already been encoded like this
989 // before ever getting here. The encoder method should just need to combine
990 // the MI operands for the register and the offset into a single
991 // representation for the complex operand in the .td file. This isn't just
992 // style, unfortunately. As-is, we can't represent the distinct encoding
994 uint32_t Binary = (Imm8 >> 2) & 0xff;
995 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
998 Binary |= (Reg << 9);
1002 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
1003 /// 'reg + imm8<<2' operand.
1004 uint32_t ARMMCCodeEmitter::
1005 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1006 SmallVectorImpl<MCFixup> &Fixups,
1007 const MCSubtargetInfo &STI) const {
1010 const MCOperand &MO = MI.getOperand(OpIdx);
1011 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1012 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1013 unsigned Imm8 = MO1.getImm();
1014 return (Reg << 8) | Imm8;
1018 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
1019 SmallVectorImpl<MCFixup> &Fixups,
1020 const MCSubtargetInfo &STI) const {
1021 // {20-16} = imm{15-12}
1022 // {11-0} = imm{11-0}
1023 const MCOperand &MO = MI.getOperand(OpIdx);
1025 // Hi / lo 16 bits already extracted during earlier passes.
1026 return static_cast<unsigned>(MO.getImm());
1028 // Handle :upper16: and :lower16: assembly prefixes.
1029 const MCExpr *E = MO.getExpr();
1031 if (E->getKind() == MCExpr::Target) {
1032 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
1033 E = ARM16Expr->getSubExpr();
1035 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1036 const int64_t Value = MCE->getValue();
1037 if (Value > UINT32_MAX)
1038 report_fatal_error("constant value truncated (limited to 32-bit)");
1040 switch (ARM16Expr->getKind()) {
1041 case ARMMCExpr::VK_ARM_HI16:
1042 return (int32_t(Value) & 0xffff0000) >> 16;
1043 case ARMMCExpr::VK_ARM_LO16:
1044 return (int32_t(Value) & 0x0000ffff);
1045 default: llvm_unreachable("Unsupported ARMFixup");
1049 switch (ARM16Expr->getKind()) {
1050 default: llvm_unreachable("Unsupported ARMFixup");
1051 case ARMMCExpr::VK_ARM_HI16:
1052 Kind = MCFixupKind(isThumb2(STI) ? ARM::fixup_t2_movt_hi16
1053 : ARM::fixup_arm_movt_hi16);
1055 case ARMMCExpr::VK_ARM_LO16:
1056 Kind = MCFixupKind(isThumb2(STI) ? ARM::fixup_t2_movw_lo16
1057 : ARM::fixup_arm_movw_lo16);
1061 Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
1064 // If the expression doesn't have :upper16: or :lower16: on it,
1065 // it's just a plain immediate expression, previously those evaluated to
1066 // the lower 16 bits of the expression regardless of whether
1067 // we have a movt or a movw, but that led to misleadingly results.
1068 // This is now disallowed in the the AsmParser in validateInstruction()
1069 // so this should never happen.
1070 llvm_unreachable("expression without :upper16: or :lower16:");
1073 uint32_t ARMMCCodeEmitter::
1074 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1075 SmallVectorImpl<MCFixup> &Fixups,
1076 const MCSubtargetInfo &STI) const {
1077 const MCOperand &MO = MI.getOperand(OpIdx);
1078 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1079 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1080 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1081 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1082 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1083 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1084 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1085 unsigned SBits = getShiftOp(ShOp);
1087 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1088 // amount. However, it would be an easy mistake to make so check here.
1089 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1098 uint32_t Binary = Rm;
1100 Binary |= SBits << 5;
1101 Binary |= ShImm << 7;
1107 uint32_t ARMMCCodeEmitter::
1108 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
1109 SmallVectorImpl<MCFixup> &Fixups,
1110 const MCSubtargetInfo &STI) const {
1112 // {13} 1 == imm12, 0 == Rm
1115 const MCOperand &MO = MI.getOperand(OpIdx);
1116 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1117 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups, STI);
1122 uint32_t ARMMCCodeEmitter::
1123 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1124 SmallVectorImpl<MCFixup> &Fixups,
1125 const MCSubtargetInfo &STI) const {
1126 // {13} 1 == imm12, 0 == Rm
1129 const MCOperand &MO = MI.getOperand(OpIdx);
1130 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1131 unsigned Imm = MO1.getImm();
1132 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1133 bool isReg = MO.getReg() != 0;
1134 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1135 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1137 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1138 Binary <<= 7; // Shift amount is bits [11:7]
1139 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1140 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1142 return Binary | (isAdd << 12) | (isReg << 13);
1145 uint32_t ARMMCCodeEmitter::
1146 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1147 SmallVectorImpl<MCFixup> &Fixups,
1148 const MCSubtargetInfo &STI) const {
1151 const MCOperand &MO = MI.getOperand(OpIdx);
1152 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1153 bool isAdd = MO1.getImm() != 0;
1154 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1157 uint32_t ARMMCCodeEmitter::
1158 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1159 SmallVectorImpl<MCFixup> &Fixups,
1160 const MCSubtargetInfo &STI) const {
1161 // {9} 1 == imm8, 0 == Rm
1163 // {7-4} imm7_4/zero
1165 const MCOperand &MO = MI.getOperand(OpIdx);
1166 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1167 unsigned Imm = MO1.getImm();
1168 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1169 bool isImm = MO.getReg() == 0;
1170 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1171 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1173 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1174 return Imm8 | (isAdd << 8) | (isImm << 9);
1177 uint32_t ARMMCCodeEmitter::
1178 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1179 SmallVectorImpl<MCFixup> &Fixups,
1180 const MCSubtargetInfo &STI) const {
1181 // {13} 1 == imm8, 0 == Rm
1184 // {7-4} imm7_4/zero
1186 const MCOperand &MO = MI.getOperand(OpIdx);
1187 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1188 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1190 // If The first operand isn't a register, we have a label reference.
1192 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1194 assert(MO.isExpr() && "Unexpected machine operand type!");
1195 const MCExpr *Expr = MO.getExpr();
1196 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1197 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1199 ++MCNumCPRelocations;
1200 return (Rn << 9) | (1 << 13);
1202 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1203 unsigned Imm = MO2.getImm();
1204 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1205 bool isImm = MO1.getReg() == 0;
1206 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1207 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1209 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1210 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1213 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1214 uint32_t ARMMCCodeEmitter::
1215 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1216 SmallVectorImpl<MCFixup> &Fixups,
1217 const MCSubtargetInfo &STI) const {
1220 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1221 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1222 "Unexpected base register!");
1224 // The immediate is already shifted for the implicit zeroes, so no change
1226 return MO1.getImm() & 0xff;
1229 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1230 uint32_t ARMMCCodeEmitter::
1231 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1232 SmallVectorImpl<MCFixup> &Fixups,
1233 const MCSubtargetInfo &STI) const {
1237 const MCOperand &MO = MI.getOperand(OpIdx);
1238 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1239 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1240 unsigned Imm5 = MO1.getImm();
1241 return ((Imm5 & 0x1f) << 3) | Rn;
1244 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1245 uint32_t ARMMCCodeEmitter::
1246 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1247 SmallVectorImpl<MCFixup> &Fixups,
1248 const MCSubtargetInfo &STI) const {
1249 const MCOperand MO = MI.getOperand(OpIdx);
1251 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
1252 return (MO.getImm() >> 2);
1255 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1256 uint32_t ARMMCCodeEmitter::
1257 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1258 SmallVectorImpl<MCFixup> &Fixups,
1259 const MCSubtargetInfo &STI) const {
1261 // {8} = (U)nsigned (add == '1', sub == '0')
1265 // If The first operand isn't a register, we have a label reference.
1266 const MCOperand &MO = MI.getOperand(OpIdx);
1268 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1270 isAdd = false; // 'U' bit is handled as part of the fixup.
1272 assert(MO.isExpr() && "Unexpected machine operand type!");
1273 const MCExpr *Expr = MO.getExpr();
1276 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1278 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1279 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1281 ++MCNumCPRelocations;
1283 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1284 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1287 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1288 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1291 Binary |= (Reg << 9);
1295 unsigned ARMMCCodeEmitter::
1296 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1297 SmallVectorImpl<MCFixup> &Fixups,
1298 const MCSubtargetInfo &STI) const {
1299 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1300 // shifted. The second is Rs, the amount to shift by, and the third specifies
1301 // the type of the shift.
1309 const MCOperand &MO = MI.getOperand(OpIdx);
1310 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1311 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1312 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1315 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1317 // Encode the shift opcode.
1319 unsigned Rs = MO1.getReg();
1321 // Set shift operand (bit[7:4]).
1327 default: llvm_unreachable("Unknown shift opc!");
1328 case ARM_AM::lsl: SBits = 0x1; break;
1329 case ARM_AM::lsr: SBits = 0x3; break;
1330 case ARM_AM::asr: SBits = 0x5; break;
1331 case ARM_AM::ror: SBits = 0x7; break;
1335 Binary |= SBits << 4;
1337 // Encode the shift operation Rs.
1338 // Encode Rs bit[11:8].
1339 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1340 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1343 unsigned ARMMCCodeEmitter::
1344 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1345 SmallVectorImpl<MCFixup> &Fixups,
1346 const MCSubtargetInfo &STI) const {
1347 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1348 // shifted. The second is the amount to shift by.
1355 const MCOperand &MO = MI.getOperand(OpIdx);
1356 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1357 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1360 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1362 // Encode the shift opcode.
1365 // Set shift operand (bit[6:4]).
1370 // RRX - 110 and bit[11:8] clear.
1372 default: llvm_unreachable("Unknown shift opc!");
1373 case ARM_AM::lsl: SBits = 0x0; break;
1374 case ARM_AM::lsr: SBits = 0x2; break;
1375 case ARM_AM::asr: SBits = 0x4; break;
1376 case ARM_AM::ror: SBits = 0x6; break;
1382 // Encode shift_imm bit[11:7].
1383 Binary |= SBits << 4;
1384 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1385 assert(Offset < 32 && "Offset must be in range 0-31!");
1386 return Binary | (Offset << 7);
1390 unsigned ARMMCCodeEmitter::
1391 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1392 SmallVectorImpl<MCFixup> &Fixups,
1393 const MCSubtargetInfo &STI) const {
1394 const MCOperand &MO1 = MI.getOperand(OpNum);
1395 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1396 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1398 // Encoded as [Rn, Rm, imm].
1399 // FIXME: Needs fixup support.
1400 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1402 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1404 Value |= MO3.getImm();
1409 unsigned ARMMCCodeEmitter::
1410 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1411 SmallVectorImpl<MCFixup> &Fixups,
1412 const MCSubtargetInfo &STI) const {
1413 const MCOperand &MO1 = MI.getOperand(OpNum);
1414 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1416 // FIXME: Needs fixup support.
1417 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1419 // Even though the immediate is 8 bits long, we need 9 bits in order
1420 // to represent the (inverse of the) sign bit.
1422 int32_t tmp = (int32_t)MO2.getImm();
1426 Value |= 256; // Set the ADD bit
1431 unsigned ARMMCCodeEmitter::
1432 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1433 SmallVectorImpl<MCFixup> &Fixups,
1434 const MCSubtargetInfo &STI) const {
1435 const MCOperand &MO1 = MI.getOperand(OpNum);
1437 // FIXME: Needs fixup support.
1439 int32_t tmp = (int32_t)MO1.getImm();
1443 Value |= 256; // Set the ADD bit
1448 unsigned ARMMCCodeEmitter::
1449 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1450 SmallVectorImpl<MCFixup> &Fixups,
1451 const MCSubtargetInfo &STI) const {
1452 const MCOperand &MO1 = MI.getOperand(OpNum);
1454 // FIXME: Needs fixup support.
1456 int32_t tmp = (int32_t)MO1.getImm();
1460 Value |= 4096; // Set the ADD bit
1461 Value |= tmp & 4095;
1465 unsigned ARMMCCodeEmitter::
1466 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1467 SmallVectorImpl<MCFixup> &Fixups,
1468 const MCSubtargetInfo &STI) const {
1469 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1470 // shifted. The second is the amount to shift by.
1477 const MCOperand &MO = MI.getOperand(OpIdx);
1478 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1479 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1482 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1484 // Encode the shift opcode.
1486 // Set shift operand (bit[6:4]).
1492 default: llvm_unreachable("Unknown shift opc!");
1493 case ARM_AM::lsl: SBits = 0x0; break;
1494 case ARM_AM::lsr: SBits = 0x2; break;
1495 case ARM_AM::asr: SBits = 0x4; break;
1496 case ARM_AM::rrx: // FALLTHROUGH
1497 case ARM_AM::ror: SBits = 0x6; break;
1500 Binary |= SBits << 4;
1501 if (SOpc == ARM_AM::rrx)
1504 // Encode shift_imm bit[11:7].
1505 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1508 unsigned ARMMCCodeEmitter::
1509 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1510 SmallVectorImpl<MCFixup> &Fixups,
1511 const MCSubtargetInfo &STI) const {
1512 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1514 const MCOperand &MO = MI.getOperand(Op);
1515 uint32_t v = ~MO.getImm();
1516 uint32_t lsb = countTrailingZeros(v);
1517 uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1518 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1519 return lsb | (msb << 5);
1522 unsigned ARMMCCodeEmitter::
1523 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1524 SmallVectorImpl<MCFixup> &Fixups,
1525 const MCSubtargetInfo &STI) const {
1528 // {7-0} = Number of registers
1531 // {15-0} = Bitfield of GPRs.
1532 unsigned Reg = MI.getOperand(Op).getReg();
1533 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1534 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1536 unsigned Binary = 0;
1538 if (SPRRegs || DPRRegs) {
1540 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1541 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1542 Binary |= (RegNo & 0x1f) << 8;
1546 Binary |= NumRegs * 2;
1548 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1549 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());
1550 Binary |= 1 << RegNo;
1557 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1558 /// with the alignment operand.
1559 unsigned ARMMCCodeEmitter::
1560 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1561 SmallVectorImpl<MCFixup> &Fixups,
1562 const MCSubtargetInfo &STI) const {
1563 const MCOperand &Reg = MI.getOperand(Op);
1564 const MCOperand &Imm = MI.getOperand(Op + 1);
1566 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1569 switch (Imm.getImm()) {
1573 case 8: Align = 0x01; break;
1574 case 16: Align = 0x02; break;
1575 case 32: Align = 0x03; break;
1578 return RegNo | (Align << 4);
1581 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1582 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1583 unsigned ARMMCCodeEmitter::
1584 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1585 SmallVectorImpl<MCFixup> &Fixups,
1586 const MCSubtargetInfo &STI) const {
1587 const MCOperand &Reg = MI.getOperand(Op);
1588 const MCOperand &Imm = MI.getOperand(Op + 1);
1590 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1593 switch (Imm.getImm()) {
1597 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1598 case 2: Align = 0x00; break;
1599 case 4: Align = 0x03; break;
1602 return RegNo | (Align << 4);
1606 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1607 /// alignment operand for use in VLD-dup instructions. This is the same as
1608 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1609 /// different for VLD4-dup.
1610 unsigned ARMMCCodeEmitter::
1611 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1612 SmallVectorImpl<MCFixup> &Fixups,
1613 const MCSubtargetInfo &STI) const {
1614 const MCOperand &Reg = MI.getOperand(Op);
1615 const MCOperand &Imm = MI.getOperand(Op + 1);
1617 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1620 switch (Imm.getImm()) {
1624 case 8: Align = 0x01; break;
1625 case 16: Align = 0x03; break;
1628 return RegNo | (Align << 4);
1631 unsigned ARMMCCodeEmitter::
1632 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1633 SmallVectorImpl<MCFixup> &Fixups,
1634 const MCSubtargetInfo &STI) const {
1635 const MCOperand &MO = MI.getOperand(Op);
1636 if (MO.getReg() == 0) return 0x0D;
1637 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1640 unsigned ARMMCCodeEmitter::
1641 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1642 SmallVectorImpl<MCFixup> &Fixups,
1643 const MCSubtargetInfo &STI) const {
1644 return 8 - MI.getOperand(Op).getImm();
1647 unsigned ARMMCCodeEmitter::
1648 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1649 SmallVectorImpl<MCFixup> &Fixups,
1650 const MCSubtargetInfo &STI) const {
1651 return 16 - MI.getOperand(Op).getImm();
1654 unsigned ARMMCCodeEmitter::
1655 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1656 SmallVectorImpl<MCFixup> &Fixups,
1657 const MCSubtargetInfo &STI) const {
1658 return 32 - MI.getOperand(Op).getImm();
1661 unsigned ARMMCCodeEmitter::
1662 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1663 SmallVectorImpl<MCFixup> &Fixups,
1664 const MCSubtargetInfo &STI) const {
1665 return 64 - MI.getOperand(Op).getImm();
1668 void ARMMCCodeEmitter::
1669 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1670 SmallVectorImpl<MCFixup> &Fixups,
1671 const MCSubtargetInfo &STI) const {
1672 // Pseudo instructions don't get encoded.
1673 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1674 uint64_t TSFlags = Desc.TSFlags;
1675 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1679 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1680 Size = Desc.getSize();
1682 llvm_unreachable("Unexpected instruction size!");
1684 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1685 // Thumb 32-bit wide instructions need to emit the high order halfword
1687 if (isThumb(STI) && Size == 4) {
1688 EmitConstant(Binary >> 16, 2, OS);
1689 EmitConstant(Binary & 0xffff, 2, OS);
1691 EmitConstant(Binary, Size, OS);
1692 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1695 #include "ARMGenMCCodeEmitter.inc"