1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/ARMMCTargetDesc.h"
16 #include "MCTargetDesc/ARMAddressingModes.h"
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "MCTargetDesc/ARMFixupKinds.h"
19 #include "MCTargetDesc/ARMMCExpr.h"
20 #include "llvm/ADT/APFloat.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
34 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
35 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
38 class ARMMCCodeEmitter : public MCCodeEmitter {
39 ARMMCCodeEmitter(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION;
40 void operator=(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION;
41 const MCInstrInfo &MCII;
42 const MCSubtargetInfo &STI;
46 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
48 : MCII(mcii), STI(sti), CTX(ctx) {
51 ~ARMMCCodeEmitter() {}
53 bool isThumb() const {
54 // FIXME: Can tablegen auto-generate this?
55 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
57 bool isThumb2() const {
58 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
60 bool isTargetMachO() const {
61 Triple TT(STI.getTargetTriple());
62 return TT.isOSBinFormatMachO();
65 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
67 // getBinaryCodeForInstr - TableGen'erated function for getting the
68 // binary encoding for an instruction.
69 uint64_t getBinaryCodeForInstr(const MCInst &MI,
70 SmallVectorImpl<MCFixup> &Fixups) const;
72 /// getMachineOpValue - Return binary encoding of operand. If the machine
73 /// operand requires relocation, record the relocation and return zero.
74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
75 SmallVectorImpl<MCFixup> &Fixups) const;
77 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
78 /// the specified operand. This is used for operands with :lower16: and
79 /// :upper16: prefixes.
80 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
81 SmallVectorImpl<MCFixup> &Fixups) const;
83 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
84 unsigned &Reg, unsigned &Imm,
85 SmallVectorImpl<MCFixup> &Fixups) const;
87 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
89 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
90 SmallVectorImpl<MCFixup> &Fixups) const;
92 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
93 /// BLX branch target.
94 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
95 SmallVectorImpl<MCFixup> &Fixups) const;
97 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
98 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
99 SmallVectorImpl<MCFixup> &Fixups) const;
101 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
102 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 SmallVectorImpl<MCFixup> &Fixups) const;
105 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
106 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
107 SmallVectorImpl<MCFixup> &Fixups) const;
109 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
111 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
112 SmallVectorImpl<MCFixup> &Fixups) const;
114 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
115 /// immediate Thumb2 direct branch target.
116 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
117 SmallVectorImpl<MCFixup> &Fixups) const;
119 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
121 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
122 SmallVectorImpl<MCFixup> &Fixups) const;
123 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
124 SmallVectorImpl<MCFixup> &Fixups) const;
125 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
126 SmallVectorImpl<MCFixup> &Fixups) const;
128 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
129 /// ADR label target.
130 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
131 SmallVectorImpl<MCFixup> &Fixups) const;
132 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
133 SmallVectorImpl<MCFixup> &Fixups) const;
134 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
135 SmallVectorImpl<MCFixup> &Fixups) const;
138 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
140 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
141 SmallVectorImpl<MCFixup> &Fixups) const;
143 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
144 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
145 SmallVectorImpl<MCFixup> &Fixups)const;
147 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
149 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
150 SmallVectorImpl<MCFixup> &Fixups) const;
152 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
154 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
155 SmallVectorImpl<MCFixup> &Fixups) const;
157 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
159 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
160 SmallVectorImpl<MCFixup> &Fixups) const;
163 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
164 /// operand as needed by load/store instructions.
165 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
166 SmallVectorImpl<MCFixup> &Fixups) const;
168 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
169 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
170 SmallVectorImpl<MCFixup> &Fixups) const {
171 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
173 default: llvm_unreachable("Unknown addressing sub-mode!");
174 case ARM_AM::da: return 0;
175 case ARM_AM::ia: return 1;
176 case ARM_AM::db: return 2;
177 case ARM_AM::ib: return 3;
180 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
182 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
184 case ARM_AM::no_shift:
185 case ARM_AM::lsl: return 0;
186 case ARM_AM::lsr: return 1;
187 case ARM_AM::asr: return 2;
189 case ARM_AM::rrx: return 3;
191 llvm_unreachable("Invalid ShiftOpc!");
194 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
195 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
196 SmallVectorImpl<MCFixup> &Fixups) const;
198 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
199 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
200 SmallVectorImpl<MCFixup> &Fixups) const;
202 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
203 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
204 SmallVectorImpl<MCFixup> &Fixups) const;
206 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
207 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
208 SmallVectorImpl<MCFixup> &Fixups) const;
210 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
211 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
212 SmallVectorImpl<MCFixup> &Fixups) const;
214 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
216 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
217 SmallVectorImpl<MCFixup> &Fixups) const;
219 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
220 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
221 SmallVectorImpl<MCFixup> &Fixups) const;
223 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
224 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
225 SmallVectorImpl<MCFixup> &Fixups) const;
227 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
228 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
229 SmallVectorImpl<MCFixup> &Fixups) const;
231 /// getCCOutOpValue - Return encoding of the 's' bit.
232 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
233 SmallVectorImpl<MCFixup> &Fixups) const {
234 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
236 return MI.getOperand(Op).getReg() == ARM::CPSR;
239 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
240 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
241 SmallVectorImpl<MCFixup> &Fixups) const {
242 unsigned SoImm = MI.getOperand(Op).getImm();
243 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
244 assert(SoImmVal != -1 && "Not a valid so_imm value!");
246 // Encode rotate_imm.
247 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
248 << ARMII::SoRotImmShift;
251 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
255 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
256 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
257 SmallVectorImpl<MCFixup> &Fixups) const {
258 unsigned SoImm = MI.getOperand(Op).getImm();
259 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
260 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
264 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
265 SmallVectorImpl<MCFixup> &Fixups) const;
266 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
267 SmallVectorImpl<MCFixup> &Fixups) const;
268 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
269 SmallVectorImpl<MCFixup> &Fixups) const;
270 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
271 SmallVectorImpl<MCFixup> &Fixups) const;
273 /// getSORegOpValue - Return an encoded so_reg shifted register value.
274 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
275 SmallVectorImpl<MCFixup> &Fixups) const;
276 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
277 SmallVectorImpl<MCFixup> &Fixups) const;
278 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
279 SmallVectorImpl<MCFixup> &Fixups) const;
281 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
282 SmallVectorImpl<MCFixup> &Fixups) const {
283 return 64 - MI.getOperand(Op).getImm();
286 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
287 SmallVectorImpl<MCFixup> &Fixups) const;
289 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
290 SmallVectorImpl<MCFixup> &Fixups) const;
291 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
292 SmallVectorImpl<MCFixup> &Fixups) const;
293 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
294 SmallVectorImpl<MCFixup> &Fixups) const;
295 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
296 SmallVectorImpl<MCFixup> &Fixups) const;
297 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
298 SmallVectorImpl<MCFixup> &Fixups) const;
300 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
301 SmallVectorImpl<MCFixup> &Fixups) const;
302 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
303 SmallVectorImpl<MCFixup> &Fixups) const;
304 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
305 SmallVectorImpl<MCFixup> &Fixups) const;
306 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
307 SmallVectorImpl<MCFixup> &Fixups) const;
309 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
310 SmallVectorImpl<MCFixup> &Fixups) const;
312 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
313 unsigned EncodedValue) const;
314 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
315 unsigned EncodedValue) const;
316 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
317 unsigned EncodedValue) const;
318 unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
319 unsigned EncodedValue) const;
321 unsigned VFPThumb2PostEncoder(const MCInst &MI,
322 unsigned EncodedValue) const;
324 void EmitByte(unsigned char C, raw_ostream &OS) const {
328 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
329 // Output the constant in little endian byte order.
330 for (unsigned i = 0; i != Size; ++i) {
331 EmitByte(Val & 255, OS);
336 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
337 SmallVectorImpl<MCFixup> &Fixups,
338 const MCSubtargetInfo &STI) const;
341 } // end anonymous namespace
343 MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
344 const MCRegisterInfo &MRI,
345 const MCSubtargetInfo &STI,
347 return new ARMMCCodeEmitter(MCII, STI, Ctx);
350 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
351 /// instructions, and rewrite them to their Thumb2 form if we are currently in
353 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
354 unsigned EncodedValue) const {
356 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
357 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
359 unsigned Bit24 = EncodedValue & 0x01000000;
360 unsigned Bit28 = Bit24 << 4;
361 EncodedValue &= 0xEFFFFFFF;
362 EncodedValue |= Bit28;
363 EncodedValue |= 0x0F000000;
369 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
370 /// instructions, and rewrite them to their Thumb2 form if we are currently in
372 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
373 unsigned EncodedValue) const {
375 EncodedValue &= 0xF0FFFFFF;
376 EncodedValue |= 0x09000000;
382 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
383 /// instructions, and rewrite them to their Thumb2 form if we are currently in
385 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
386 unsigned EncodedValue) const {
388 EncodedValue &= 0x00FFFFFF;
389 EncodedValue |= 0xEE000000;
395 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
396 /// if we are in Thumb2.
397 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
398 unsigned EncodedValue) const {
400 EncodedValue |= 0xC000000; // Set bits 27-26
406 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
407 /// them to their Thumb2 form if we are currently in Thumb2 mode.
408 unsigned ARMMCCodeEmitter::
409 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
411 EncodedValue &= 0x0FFFFFFF;
412 EncodedValue |= 0xE0000000;
417 /// getMachineOpValue - Return binary encoding of operand. If the machine
418 /// operand requires relocation, record the relocation and return zero.
419 unsigned ARMMCCodeEmitter::
420 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
421 SmallVectorImpl<MCFixup> &Fixups) const {
423 unsigned Reg = MO.getReg();
424 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
426 // Q registers are encoded as 2x their register number.
430 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
431 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
432 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
433 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
436 } else if (MO.isImm()) {
437 return static_cast<unsigned>(MO.getImm());
438 } else if (MO.isFPImm()) {
439 return static_cast<unsigned>(APFloat(MO.getFPImm())
440 .bitcastToAPInt().getHiBits(32).getLimitedValue());
443 llvm_unreachable("Unable to encode MCOperand!");
446 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
447 bool ARMMCCodeEmitter::
448 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
449 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
450 const MCOperand &MO = MI.getOperand(OpIdx);
451 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
453 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
455 int32_t SImm = MO1.getImm();
458 // Special value for #-0
459 if (SImm == INT32_MIN) {
464 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
474 /// getBranchTargetOpValue - Helper function to get the branch target operand,
475 /// which is either an immediate or requires a fixup.
476 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
478 SmallVectorImpl<MCFixup> &Fixups) {
479 const MCOperand &MO = MI.getOperand(OpIdx);
481 // If the destination is an immediate, we have nothing to do.
482 if (MO.isImm()) return MO.getImm();
483 assert(MO.isExpr() && "Unexpected branch target type!");
484 const MCExpr *Expr = MO.getExpr();
485 MCFixupKind Kind = MCFixupKind(FixupKind);
486 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
488 // All of the information is in the fixup.
492 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
493 // determined by negating them and XOR'ing them with bit 23.
494 static int32_t encodeThumbBLOffset(int32_t offset) {
496 uint32_t S = (offset & 0x800000) >> 23;
497 uint32_t J1 = (offset & 0x400000) >> 22;
498 uint32_t J2 = (offset & 0x200000) >> 21;
511 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
512 uint32_t ARMMCCodeEmitter::
513 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
514 SmallVectorImpl<MCFixup> &Fixups) const {
515 const MCOperand MO = MI.getOperand(OpIdx);
517 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
519 return encodeThumbBLOffset(MO.getImm());
522 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
523 /// BLX branch target.
524 uint32_t ARMMCCodeEmitter::
525 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
526 SmallVectorImpl<MCFixup> &Fixups) const {
527 const MCOperand MO = MI.getOperand(OpIdx);
529 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
531 return encodeThumbBLOffset(MO.getImm());
534 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
535 uint32_t ARMMCCodeEmitter::
536 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
537 SmallVectorImpl<MCFixup> &Fixups) const {
538 const MCOperand MO = MI.getOperand(OpIdx);
540 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
542 return (MO.getImm() >> 1);
545 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
546 uint32_t ARMMCCodeEmitter::
547 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
548 SmallVectorImpl<MCFixup> &Fixups) const {
549 const MCOperand MO = MI.getOperand(OpIdx);
551 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
553 return (MO.getImm() >> 1);
556 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
557 uint32_t ARMMCCodeEmitter::
558 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
559 SmallVectorImpl<MCFixup> &Fixups) const {
560 const MCOperand MO = MI.getOperand(OpIdx);
562 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
563 return (MO.getImm() >> 1);
566 /// Return true if this branch has a non-always predication
567 static bool HasConditionalBranch(const MCInst &MI) {
568 int NumOp = MI.getNumOperands();
570 for (int i = 0; i < NumOp-1; ++i) {
571 const MCOperand &MCOp1 = MI.getOperand(i);
572 const MCOperand &MCOp2 = MI.getOperand(i + 1);
573 if (MCOp1.isImm() && MCOp2.isReg() &&
574 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
575 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
583 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
585 uint32_t ARMMCCodeEmitter::
586 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
587 SmallVectorImpl<MCFixup> &Fixups) const {
588 // FIXME: This really, really shouldn't use TargetMachine. We don't want
589 // coupling between MC and TM anywhere we can help it.
592 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
593 return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
596 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
598 uint32_t ARMMCCodeEmitter::
599 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
600 SmallVectorImpl<MCFixup> &Fixups) const {
601 const MCOperand MO = MI.getOperand(OpIdx);
603 if (HasConditionalBranch(MI))
604 return ::getBranchTargetOpValue(MI, OpIdx,
605 ARM::fixup_arm_condbranch, Fixups);
606 return ::getBranchTargetOpValue(MI, OpIdx,
607 ARM::fixup_arm_uncondbranch, Fixups);
610 return MO.getImm() >> 2;
613 uint32_t ARMMCCodeEmitter::
614 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
615 SmallVectorImpl<MCFixup> &Fixups) const {
616 const MCOperand MO = MI.getOperand(OpIdx);
618 if (HasConditionalBranch(MI))
619 return ::getBranchTargetOpValue(MI, OpIdx,
620 ARM::fixup_arm_condbl, Fixups);
621 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups);
624 return MO.getImm() >> 2;
627 uint32_t ARMMCCodeEmitter::
628 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
629 SmallVectorImpl<MCFixup> &Fixups) const {
630 const MCOperand MO = MI.getOperand(OpIdx);
632 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups);
634 return MO.getImm() >> 1;
637 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
638 /// immediate branch target.
639 uint32_t ARMMCCodeEmitter::
640 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
641 SmallVectorImpl<MCFixup> &Fixups) const {
643 const MCOperand MO = MI.getOperand(OpIdx);
646 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
648 Val = MO.getImm() >> 1;
650 bool I = (Val & 0x800000);
651 bool J1 = (Val & 0x400000);
652 bool J2 = (Val & 0x200000);
666 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
667 /// ADR label target.
668 uint32_t ARMMCCodeEmitter::
669 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
670 SmallVectorImpl<MCFixup> &Fixups) const {
671 const MCOperand MO = MI.getOperand(OpIdx);
673 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
675 int64_t offset = MO.getImm();
676 uint32_t Val = 0x2000;
679 if (offset == INT32_MIN) {
682 } else if (offset < 0) {
685 SoImmVal = ARM_AM::getSOImmVal(offset);
689 SoImmVal = ARM_AM::getSOImmVal(offset);
692 SoImmVal = ARM_AM::getSOImmVal(offset);
696 SoImmVal = ARM_AM::getSOImmVal(offset);
700 assert(SoImmVal != -1 && "Not a valid so_imm value!");
706 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
708 uint32_t ARMMCCodeEmitter::
709 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
710 SmallVectorImpl<MCFixup> &Fixups) const {
711 const MCOperand MO = MI.getOperand(OpIdx);
713 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
715 int32_t Val = MO.getImm();
716 if (Val == INT32_MIN)
725 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
727 uint32_t ARMMCCodeEmitter::
728 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
729 SmallVectorImpl<MCFixup> &Fixups) const {
730 const MCOperand MO = MI.getOperand(OpIdx);
732 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
737 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
739 uint32_t ARMMCCodeEmitter::
740 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
741 SmallVectorImpl<MCFixup> &) const {
745 const MCOperand &MO1 = MI.getOperand(OpIdx);
746 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
747 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
748 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
749 return (Rm << 3) | Rn;
752 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
753 uint32_t ARMMCCodeEmitter::
754 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
755 SmallVectorImpl<MCFixup> &Fixups) const {
757 // {12} = (U)nsigned (add == '1', sub == '0')
761 // If The first operand isn't a register, we have a label reference.
762 const MCOperand &MO = MI.getOperand(OpIdx);
764 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
768 const MCExpr *Expr = MO.getExpr();
769 isAdd = false ; // 'U' bit is set as part of the fixup.
773 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
775 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
776 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
778 ++MCNumCPRelocations;
781 int32_t Offset = MO.getImm();
782 if (Offset == INT32_MIN) {
785 } else if (Offset < 0) {
792 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
794 uint32_t Binary = Imm12 & 0xfff;
795 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
798 Binary |= (Reg << 13);
802 /// getT2Imm8s4OpValue - Return encoding info for
803 /// '+/- imm8<<2' operand.
804 uint32_t ARMMCCodeEmitter::
805 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
806 SmallVectorImpl<MCFixup> &Fixups) const {
807 // FIXME: The immediate operand should have already been encoded like this
808 // before ever getting here. The encoder method should just need to combine
809 // the MI operands for the register and the offset into a single
810 // representation for the complex operand in the .td file. This isn't just
811 // style, unfortunately. As-is, we can't represent the distinct encoding
814 // {8} = (U)nsigned (add == '1', sub == '0')
816 int32_t Imm8 = MI.getOperand(OpIdx).getImm();
817 bool isAdd = Imm8 >= 0;
819 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
821 Imm8 = -(uint32_t)Imm8;
826 uint32_t Binary = Imm8 & 0xff;
827 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
833 /// getT2AddrModeImm8s4OpValue - Return encoding info for
834 /// 'reg +/- imm8<<2' operand.
835 uint32_t ARMMCCodeEmitter::
836 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
837 SmallVectorImpl<MCFixup> &Fixups) const {
839 // {8} = (U)nsigned (add == '1', sub == '0')
843 // If The first operand isn't a register, we have a label reference.
844 const MCOperand &MO = MI.getOperand(OpIdx);
846 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
848 isAdd = false ; // 'U' bit is set as part of the fixup.
850 assert(MO.isExpr() && "Unexpected machine operand type!");
851 const MCExpr *Expr = MO.getExpr();
852 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
853 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
855 ++MCNumCPRelocations;
857 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
859 // FIXME: The immediate operand should have already been encoded like this
860 // before ever getting here. The encoder method should just need to combine
861 // the MI operands for the register and the offset into a single
862 // representation for the complex operand in the .td file. This isn't just
863 // style, unfortunately. As-is, we can't represent the distinct encoding
865 uint32_t Binary = (Imm8 >> 2) & 0xff;
866 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
869 Binary |= (Reg << 9);
873 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
874 /// 'reg + imm8<<2' operand.
875 uint32_t ARMMCCodeEmitter::
876 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
877 SmallVectorImpl<MCFixup> &Fixups) const {
880 const MCOperand &MO = MI.getOperand(OpIdx);
881 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
882 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
883 unsigned Imm8 = MO1.getImm();
884 return (Reg << 8) | Imm8;
887 // FIXME: This routine assumes that a binary
888 // expression will always result in a PCRel expression
889 // In reality, its only true if one or more subexpressions
890 // is itself a PCRel (i.e. "." in asm or some other pcrel construct)
891 // but this is good enough for now.
892 static bool EvaluateAsPCRel(const MCExpr *Expr) {
893 switch (Expr->getKind()) {
894 default: llvm_unreachable("Unexpected expression type");
895 case MCExpr::SymbolRef: return false;
896 case MCExpr::Binary: return true;
901 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
902 SmallVectorImpl<MCFixup> &Fixups) const {
903 // {20-16} = imm{15-12}
904 // {11-0} = imm{11-0}
905 const MCOperand &MO = MI.getOperand(OpIdx);
907 // Hi / lo 16 bits already extracted during earlier passes.
908 return static_cast<unsigned>(MO.getImm());
910 // Handle :upper16: and :lower16: assembly prefixes.
911 const MCExpr *E = MO.getExpr();
913 if (E->getKind() == MCExpr::Target) {
914 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
915 E = ARM16Expr->getSubExpr();
917 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
918 const int64_t Value = MCE->getValue();
919 if (Value > UINT32_MAX)
920 report_fatal_error("constant value truncated (limited to 32-bit)");
922 switch (ARM16Expr->getKind()) {
923 case ARMMCExpr::VK_ARM_HI16:
924 return (int32_t(Value) & 0xffff0000) >> 16;
925 case ARMMCExpr::VK_ARM_LO16:
926 return (int32_t(Value) & 0x0000ffff);
927 default: llvm_unreachable("Unsupported ARMFixup");
931 switch (ARM16Expr->getKind()) {
932 default: llvm_unreachable("Unsupported ARMFixup");
933 case ARMMCExpr::VK_ARM_HI16:
934 if (!isTargetMachO() && EvaluateAsPCRel(E))
935 Kind = MCFixupKind(isThumb2()
936 ? ARM::fixup_t2_movt_hi16_pcrel
937 : ARM::fixup_arm_movt_hi16_pcrel);
939 Kind = MCFixupKind(isThumb2()
940 ? ARM::fixup_t2_movt_hi16
941 : ARM::fixup_arm_movt_hi16);
943 case ARMMCExpr::VK_ARM_LO16:
944 if (!isTargetMachO() && EvaluateAsPCRel(E))
945 Kind = MCFixupKind(isThumb2()
946 ? ARM::fixup_t2_movw_lo16_pcrel
947 : ARM::fixup_arm_movw_lo16_pcrel);
949 Kind = MCFixupKind(isThumb2()
950 ? ARM::fixup_t2_movw_lo16
951 : ARM::fixup_arm_movw_lo16);
954 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
957 // If the expression doesn't have :upper16: or :lower16: on it,
958 // it's just a plain immediate expression, and those evaluate to
959 // the lower 16 bits of the expression regardless of whether
960 // we have a movt or a movw.
961 if (!isTargetMachO() && EvaluateAsPCRel(E))
962 Kind = MCFixupKind(isThumb2()
963 ? ARM::fixup_t2_movw_lo16_pcrel
964 : ARM::fixup_arm_movw_lo16_pcrel);
966 Kind = MCFixupKind(isThumb2()
967 ? ARM::fixup_t2_movw_lo16
968 : ARM::fixup_arm_movw_lo16);
969 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
973 uint32_t ARMMCCodeEmitter::
974 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
975 SmallVectorImpl<MCFixup> &Fixups) const {
976 const MCOperand &MO = MI.getOperand(OpIdx);
977 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
978 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
979 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
980 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
981 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
982 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
983 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
984 unsigned SBits = getShiftOp(ShOp);
986 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
987 // amount. However, it would be an easy mistake to make so check here.
988 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
997 uint32_t Binary = Rm;
999 Binary |= SBits << 5;
1000 Binary |= ShImm << 7;
1006 uint32_t ARMMCCodeEmitter::
1007 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
1008 SmallVectorImpl<MCFixup> &Fixups) const {
1010 // {13} 1 == imm12, 0 == Rm
1013 const MCOperand &MO = MI.getOperand(OpIdx);
1014 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1015 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
1020 uint32_t ARMMCCodeEmitter::
1021 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1022 SmallVectorImpl<MCFixup> &Fixups) const {
1023 // {13} 1 == imm12, 0 == Rm
1026 const MCOperand &MO = MI.getOperand(OpIdx);
1027 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1028 unsigned Imm = MO1.getImm();
1029 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1030 bool isReg = MO.getReg() != 0;
1031 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1032 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1034 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1035 Binary <<= 7; // Shift amount is bits [11:7]
1036 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1037 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1039 return Binary | (isAdd << 12) | (isReg << 13);
1042 uint32_t ARMMCCodeEmitter::
1043 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1044 SmallVectorImpl<MCFixup> &Fixups) const {
1047 const MCOperand &MO = MI.getOperand(OpIdx);
1048 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1049 bool isAdd = MO1.getImm() != 0;
1050 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1053 uint32_t ARMMCCodeEmitter::
1054 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1055 SmallVectorImpl<MCFixup> &Fixups) const {
1056 // {9} 1 == imm8, 0 == Rm
1058 // {7-4} imm7_4/zero
1060 const MCOperand &MO = MI.getOperand(OpIdx);
1061 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1062 unsigned Imm = MO1.getImm();
1063 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1064 bool isImm = MO.getReg() == 0;
1065 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1066 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1068 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1069 return Imm8 | (isAdd << 8) | (isImm << 9);
1072 uint32_t ARMMCCodeEmitter::
1073 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1074 SmallVectorImpl<MCFixup> &Fixups) const {
1075 // {13} 1 == imm8, 0 == Rm
1078 // {7-4} imm7_4/zero
1080 const MCOperand &MO = MI.getOperand(OpIdx);
1081 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1082 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1084 // If The first operand isn't a register, we have a label reference.
1086 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1088 assert(MO.isExpr() && "Unexpected machine operand type!");
1089 const MCExpr *Expr = MO.getExpr();
1090 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1091 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1093 ++MCNumCPRelocations;
1094 return (Rn << 9) | (1 << 13);
1096 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1097 unsigned Imm = MO2.getImm();
1098 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1099 bool isImm = MO1.getReg() == 0;
1100 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1101 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1103 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1104 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1107 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1108 uint32_t ARMMCCodeEmitter::
1109 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1110 SmallVectorImpl<MCFixup> &Fixups) const {
1113 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1114 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1115 "Unexpected base register!");
1117 // The immediate is already shifted for the implicit zeroes, so no change
1119 return MO1.getImm() & 0xff;
1122 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1123 uint32_t ARMMCCodeEmitter::
1124 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1125 SmallVectorImpl<MCFixup> &Fixups) const {
1129 const MCOperand &MO = MI.getOperand(OpIdx);
1130 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1131 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1132 unsigned Imm5 = MO1.getImm();
1133 return ((Imm5 & 0x1f) << 3) | Rn;
1136 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1137 uint32_t ARMMCCodeEmitter::
1138 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1139 SmallVectorImpl<MCFixup> &Fixups) const {
1140 const MCOperand MO = MI.getOperand(OpIdx);
1142 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
1143 return (MO.getImm() >> 2);
1146 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1147 uint32_t ARMMCCodeEmitter::
1148 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1149 SmallVectorImpl<MCFixup> &Fixups) const {
1151 // {8} = (U)nsigned (add == '1', sub == '0')
1155 // If The first operand isn't a register, we have a label reference.
1156 const MCOperand &MO = MI.getOperand(OpIdx);
1158 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1160 isAdd = false; // 'U' bit is handled as part of the fixup.
1162 assert(MO.isExpr() && "Unexpected machine operand type!");
1163 const MCExpr *Expr = MO.getExpr();
1166 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1168 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1169 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1171 ++MCNumCPRelocations;
1173 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
1174 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1177 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1178 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1181 Binary |= (Reg << 9);
1185 unsigned ARMMCCodeEmitter::
1186 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1187 SmallVectorImpl<MCFixup> &Fixups) const {
1188 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1189 // shifted. The second is Rs, the amount to shift by, and the third specifies
1190 // the type of the shift.
1198 const MCOperand &MO = MI.getOperand(OpIdx);
1199 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1200 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1201 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1204 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1206 // Encode the shift opcode.
1208 unsigned Rs = MO1.getReg();
1210 // Set shift operand (bit[7:4]).
1216 default: llvm_unreachable("Unknown shift opc!");
1217 case ARM_AM::lsl: SBits = 0x1; break;
1218 case ARM_AM::lsr: SBits = 0x3; break;
1219 case ARM_AM::asr: SBits = 0x5; break;
1220 case ARM_AM::ror: SBits = 0x7; break;
1224 Binary |= SBits << 4;
1226 // Encode the shift operation Rs.
1227 // Encode Rs bit[11:8].
1228 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1229 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1232 unsigned ARMMCCodeEmitter::
1233 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1234 SmallVectorImpl<MCFixup> &Fixups) const {
1235 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1236 // shifted. The second is the amount to shift by.
1243 const MCOperand &MO = MI.getOperand(OpIdx);
1244 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1245 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1248 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1250 // Encode the shift opcode.
1253 // Set shift operand (bit[6:4]).
1258 // RRX - 110 and bit[11:8] clear.
1260 default: llvm_unreachable("Unknown shift opc!");
1261 case ARM_AM::lsl: SBits = 0x0; break;
1262 case ARM_AM::lsr: SBits = 0x2; break;
1263 case ARM_AM::asr: SBits = 0x4; break;
1264 case ARM_AM::ror: SBits = 0x6; break;
1270 // Encode shift_imm bit[11:7].
1271 Binary |= SBits << 4;
1272 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1273 assert(Offset < 32 && "Offset must be in range 0-31!");
1274 return Binary | (Offset << 7);
1278 unsigned ARMMCCodeEmitter::
1279 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1280 SmallVectorImpl<MCFixup> &Fixups) const {
1281 const MCOperand &MO1 = MI.getOperand(OpNum);
1282 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1283 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1285 // Encoded as [Rn, Rm, imm].
1286 // FIXME: Needs fixup support.
1287 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1289 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1291 Value |= MO3.getImm();
1296 unsigned ARMMCCodeEmitter::
1297 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1298 SmallVectorImpl<MCFixup> &Fixups) const {
1299 const MCOperand &MO1 = MI.getOperand(OpNum);
1300 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1302 // FIXME: Needs fixup support.
1303 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1305 // Even though the immediate is 8 bits long, we need 9 bits in order
1306 // to represent the (inverse of the) sign bit.
1308 int32_t tmp = (int32_t)MO2.getImm();
1312 Value |= 256; // Set the ADD bit
1317 unsigned ARMMCCodeEmitter::
1318 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1319 SmallVectorImpl<MCFixup> &Fixups) const {
1320 const MCOperand &MO1 = MI.getOperand(OpNum);
1322 // FIXME: Needs fixup support.
1324 int32_t tmp = (int32_t)MO1.getImm();
1328 Value |= 256; // Set the ADD bit
1333 unsigned ARMMCCodeEmitter::
1334 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1335 SmallVectorImpl<MCFixup> &Fixups) const {
1336 const MCOperand &MO1 = MI.getOperand(OpNum);
1338 // FIXME: Needs fixup support.
1340 int32_t tmp = (int32_t)MO1.getImm();
1344 Value |= 4096; // Set the ADD bit
1345 Value |= tmp & 4095;
1349 unsigned ARMMCCodeEmitter::
1350 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1351 SmallVectorImpl<MCFixup> &Fixups) const {
1352 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1353 // shifted. The second is the amount to shift by.
1360 const MCOperand &MO = MI.getOperand(OpIdx);
1361 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1362 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1365 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1367 // Encode the shift opcode.
1369 // Set shift operand (bit[6:4]).
1375 default: llvm_unreachable("Unknown shift opc!");
1376 case ARM_AM::lsl: SBits = 0x0; break;
1377 case ARM_AM::lsr: SBits = 0x2; break;
1378 case ARM_AM::asr: SBits = 0x4; break;
1379 case ARM_AM::rrx: // FALLTHROUGH
1380 case ARM_AM::ror: SBits = 0x6; break;
1383 Binary |= SBits << 4;
1384 if (SOpc == ARM_AM::rrx)
1387 // Encode shift_imm bit[11:7].
1388 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1391 unsigned ARMMCCodeEmitter::
1392 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1393 SmallVectorImpl<MCFixup> &Fixups) const {
1394 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1396 const MCOperand &MO = MI.getOperand(Op);
1397 uint32_t v = ~MO.getImm();
1398 uint32_t lsb = countTrailingZeros(v);
1399 uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1400 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1401 return lsb | (msb << 5);
1404 unsigned ARMMCCodeEmitter::
1405 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1406 SmallVectorImpl<MCFixup> &Fixups) const {
1409 // {7-0} = Number of registers
1412 // {15-0} = Bitfield of GPRs.
1413 unsigned Reg = MI.getOperand(Op).getReg();
1414 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1415 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1417 unsigned Binary = 0;
1419 if (SPRRegs || DPRRegs) {
1421 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1422 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1423 Binary |= (RegNo & 0x1f) << 8;
1427 Binary |= NumRegs * 2;
1429 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1430 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());
1431 Binary |= 1 << RegNo;
1438 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1439 /// with the alignment operand.
1440 unsigned ARMMCCodeEmitter::
1441 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1442 SmallVectorImpl<MCFixup> &Fixups) const {
1443 const MCOperand &Reg = MI.getOperand(Op);
1444 const MCOperand &Imm = MI.getOperand(Op + 1);
1446 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1449 switch (Imm.getImm()) {
1453 case 8: Align = 0x01; break;
1454 case 16: Align = 0x02; break;
1455 case 32: Align = 0x03; break;
1458 return RegNo | (Align << 4);
1461 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1462 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1463 unsigned ARMMCCodeEmitter::
1464 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1465 SmallVectorImpl<MCFixup> &Fixups) const {
1466 const MCOperand &Reg = MI.getOperand(Op);
1467 const MCOperand &Imm = MI.getOperand(Op + 1);
1469 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1472 switch (Imm.getImm()) {
1476 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1477 case 2: Align = 0x00; break;
1478 case 4: Align = 0x03; break;
1481 return RegNo | (Align << 4);
1485 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1486 /// alignment operand for use in VLD-dup instructions. This is the same as
1487 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1488 /// different for VLD4-dup.
1489 unsigned ARMMCCodeEmitter::
1490 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1491 SmallVectorImpl<MCFixup> &Fixups) const {
1492 const MCOperand &Reg = MI.getOperand(Op);
1493 const MCOperand &Imm = MI.getOperand(Op + 1);
1495 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1498 switch (Imm.getImm()) {
1502 case 8: Align = 0x01; break;
1503 case 16: Align = 0x03; break;
1506 return RegNo | (Align << 4);
1509 unsigned ARMMCCodeEmitter::
1510 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1511 SmallVectorImpl<MCFixup> &Fixups) const {
1512 const MCOperand &MO = MI.getOperand(Op);
1513 if (MO.getReg() == 0) return 0x0D;
1514 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1517 unsigned ARMMCCodeEmitter::
1518 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1519 SmallVectorImpl<MCFixup> &Fixups) const {
1520 return 8 - MI.getOperand(Op).getImm();
1523 unsigned ARMMCCodeEmitter::
1524 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1525 SmallVectorImpl<MCFixup> &Fixups) const {
1526 return 16 - MI.getOperand(Op).getImm();
1529 unsigned ARMMCCodeEmitter::
1530 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1531 SmallVectorImpl<MCFixup> &Fixups) const {
1532 return 32 - MI.getOperand(Op).getImm();
1535 unsigned ARMMCCodeEmitter::
1536 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1537 SmallVectorImpl<MCFixup> &Fixups) const {
1538 return 64 - MI.getOperand(Op).getImm();
1541 void ARMMCCodeEmitter::
1542 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1543 SmallVectorImpl<MCFixup> &Fixups,
1544 const MCSubtargetInfo &STI) const {
1545 // Pseudo instructions don't get encoded.
1546 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1547 uint64_t TSFlags = Desc.TSFlags;
1548 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1552 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1553 Size = Desc.getSize();
1555 llvm_unreachable("Unexpected instruction size!");
1557 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1558 // Thumb 32-bit wide instructions need to emit the high order halfword
1560 if (isThumb() && Size == 4) {
1561 EmitConstant(Binary >> 16, 2, OS);
1562 EmitConstant(Binary & 0xffff, 2, OS);
1564 EmitConstant(Binary, Size, OS);
1565 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1568 #include "ARMGenMCCodeEmitter.inc"