1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMFixupKinds.h"
18 #include "MCTargetDesc/ARMMCExpr.h"
19 #include "MCTargetDesc/ARMMCTargetDesc.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/raw_ostream.h"
32 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
33 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
36 class ARMMCCodeEmitter : public MCCodeEmitter {
37 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
38 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
39 const MCInstrInfo &MCII;
40 const MCSubtargetInfo &STI;
43 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
45 : MCII(mcii), STI(sti) {
48 ~ARMMCCodeEmitter() {}
50 bool isThumb() const {
51 // FIXME: Can tablegen auto-generate this?
52 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
54 bool isThumb2() const {
55 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
57 bool isTargetDarwin() const {
58 Triple TT(STI.getTargetTriple());
59 Triple::OSType OS = TT.getOS();
60 return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS;
63 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
65 // getBinaryCodeForInstr - TableGen'erated function for getting the
66 // binary encoding for an instruction.
67 uint64_t getBinaryCodeForInstr(const MCInst &MI,
68 SmallVectorImpl<MCFixup> &Fixups) const;
70 /// getMachineOpValue - Return binary encoding of operand. If the machine
71 /// operand requires relocation, record the relocation and return zero.
72 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
73 SmallVectorImpl<MCFixup> &Fixups) const;
75 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
76 /// the specified operand. This is used for operands with :lower16: and
77 /// :upper16: prefixes.
78 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
79 SmallVectorImpl<MCFixup> &Fixups) const;
81 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
82 unsigned &Reg, unsigned &Imm,
83 SmallVectorImpl<MCFixup> &Fixups) const;
85 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
87 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
88 SmallVectorImpl<MCFixup> &Fixups) const;
90 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
91 /// BLX branch target.
92 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
93 SmallVectorImpl<MCFixup> &Fixups) const;
95 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
96 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
97 SmallVectorImpl<MCFixup> &Fixups) const;
99 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
100 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
101 SmallVectorImpl<MCFixup> &Fixups) const;
103 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
104 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 SmallVectorImpl<MCFixup> &Fixups) const;
107 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
109 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
110 SmallVectorImpl<MCFixup> &Fixups) const;
112 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
113 /// immediate Thumb2 direct branch target.
114 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
115 SmallVectorImpl<MCFixup> &Fixups) const;
117 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
119 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120 SmallVectorImpl<MCFixup> &Fixups) const;
121 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
122 SmallVectorImpl<MCFixup> &Fixups) const;
123 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
124 SmallVectorImpl<MCFixup> &Fixups) const;
126 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
127 /// ADR label target.
128 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
129 SmallVectorImpl<MCFixup> &Fixups) const;
130 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
131 SmallVectorImpl<MCFixup> &Fixups) const;
132 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
133 SmallVectorImpl<MCFixup> &Fixups) const;
136 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
138 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
139 SmallVectorImpl<MCFixup> &Fixups) const;
141 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
142 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
143 SmallVectorImpl<MCFixup> &Fixups)const;
145 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
147 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
148 SmallVectorImpl<MCFixup> &Fixups) const;
150 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
152 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
153 SmallVectorImpl<MCFixup> &Fixups) const;
155 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
157 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
158 SmallVectorImpl<MCFixup> &Fixups) const;
161 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
162 /// operand as needed by load/store instructions.
163 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
164 SmallVectorImpl<MCFixup> &Fixups) const;
166 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
167 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
168 SmallVectorImpl<MCFixup> &Fixups) const {
169 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
171 default: llvm_unreachable("Unknown addressing sub-mode!");
172 case ARM_AM::da: return 0;
173 case ARM_AM::ia: return 1;
174 case ARM_AM::db: return 2;
175 case ARM_AM::ib: return 3;
178 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
180 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
182 case ARM_AM::no_shift:
183 case ARM_AM::lsl: return 0;
184 case ARM_AM::lsr: return 1;
185 case ARM_AM::asr: return 2;
187 case ARM_AM::rrx: return 3;
189 llvm_unreachable("Invalid ShiftOpc!");
192 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
193 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
194 SmallVectorImpl<MCFixup> &Fixups) const;
196 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
197 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
198 SmallVectorImpl<MCFixup> &Fixups) const;
200 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
201 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
202 SmallVectorImpl<MCFixup> &Fixups) const;
204 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
205 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
206 SmallVectorImpl<MCFixup> &Fixups) const;
208 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
209 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
210 SmallVectorImpl<MCFixup> &Fixups) const;
212 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
214 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
215 SmallVectorImpl<MCFixup> &Fixups) const;
217 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
218 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
219 SmallVectorImpl<MCFixup> &Fixups) const;
221 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
222 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
223 SmallVectorImpl<MCFixup> &Fixups) const;
225 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
226 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
227 SmallVectorImpl<MCFixup> &Fixups) const;
229 /// getCCOutOpValue - Return encoding of the 's' bit.
230 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
231 SmallVectorImpl<MCFixup> &Fixups) const {
232 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
234 return MI.getOperand(Op).getReg() == ARM::CPSR;
237 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
238 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
239 SmallVectorImpl<MCFixup> &Fixups) const {
240 unsigned SoImm = MI.getOperand(Op).getImm();
241 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
242 assert(SoImmVal != -1 && "Not a valid so_imm value!");
244 // Encode rotate_imm.
245 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
246 << ARMII::SoRotImmShift;
249 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
253 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
254 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
255 SmallVectorImpl<MCFixup> &Fixups) const {
256 unsigned SoImm = MI.getOperand(Op).getImm();
257 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
258 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
262 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
263 SmallVectorImpl<MCFixup> &Fixups) const;
264 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
265 SmallVectorImpl<MCFixup> &Fixups) const;
266 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
267 SmallVectorImpl<MCFixup> &Fixups) const;
268 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
269 SmallVectorImpl<MCFixup> &Fixups) const;
271 /// getSORegOpValue - Return an encoded so_reg shifted register value.
272 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
273 SmallVectorImpl<MCFixup> &Fixups) const;
274 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
275 SmallVectorImpl<MCFixup> &Fixups) const;
276 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
277 SmallVectorImpl<MCFixup> &Fixups) const;
279 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
280 SmallVectorImpl<MCFixup> &Fixups) const {
281 return 64 - MI.getOperand(Op).getImm();
284 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
285 SmallVectorImpl<MCFixup> &Fixups) const;
287 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
288 SmallVectorImpl<MCFixup> &Fixups) const;
289 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
290 SmallVectorImpl<MCFixup> &Fixups) const;
291 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
292 SmallVectorImpl<MCFixup> &Fixups) const;
293 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
294 SmallVectorImpl<MCFixup> &Fixups) const;
295 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
296 SmallVectorImpl<MCFixup> &Fixups) const;
298 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
299 SmallVectorImpl<MCFixup> &Fixups) const;
300 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
301 SmallVectorImpl<MCFixup> &Fixups) const;
302 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
303 SmallVectorImpl<MCFixup> &Fixups) const;
304 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
305 SmallVectorImpl<MCFixup> &Fixups) const;
307 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
308 SmallVectorImpl<MCFixup> &Fixups) const;
310 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
311 unsigned EncodedValue) const;
312 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
313 unsigned EncodedValue) const;
314 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
315 unsigned EncodedValue) const;
317 unsigned VFPThumb2PostEncoder(const MCInst &MI,
318 unsigned EncodedValue) const;
320 void EmitByte(unsigned char C, raw_ostream &OS) const {
324 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
325 // Output the constant in little endian byte order.
326 for (unsigned i = 0; i != Size; ++i) {
327 EmitByte(Val & 255, OS);
332 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
333 SmallVectorImpl<MCFixup> &Fixups) const;
336 } // end anonymous namespace
338 MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
339 const MCRegisterInfo &MRI,
340 const MCSubtargetInfo &STI,
342 return new ARMMCCodeEmitter(MCII, STI, Ctx);
345 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
346 /// instructions, and rewrite them to their Thumb2 form if we are currently in
348 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
349 unsigned EncodedValue) const {
351 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
352 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
354 unsigned Bit24 = EncodedValue & 0x01000000;
355 unsigned Bit28 = Bit24 << 4;
356 EncodedValue &= 0xEFFFFFFF;
357 EncodedValue |= Bit28;
358 EncodedValue |= 0x0F000000;
364 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
365 /// instructions, and rewrite them to their Thumb2 form if we are currently in
367 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
368 unsigned EncodedValue) const {
370 EncodedValue &= 0xF0FFFFFF;
371 EncodedValue |= 0x09000000;
377 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
378 /// instructions, and rewrite them to their Thumb2 form if we are currently in
380 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
381 unsigned EncodedValue) const {
383 EncodedValue &= 0x00FFFFFF;
384 EncodedValue |= 0xEE000000;
390 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
391 /// them to their Thumb2 form if we are currently in Thumb2 mode.
392 unsigned ARMMCCodeEmitter::
393 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
395 EncodedValue &= 0x0FFFFFFF;
396 EncodedValue |= 0xE0000000;
401 /// getMachineOpValue - Return binary encoding of operand. If the machine
402 /// operand requires relocation, record the relocation and return zero.
403 unsigned ARMMCCodeEmitter::
404 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
405 SmallVectorImpl<MCFixup> &Fixups) const {
407 unsigned Reg = MO.getReg();
408 unsigned RegNo = getARMRegisterNumbering(Reg);
410 // Q registers are encoded as 2x their register number.
414 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
415 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
416 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
417 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
420 } else if (MO.isImm()) {
421 return static_cast<unsigned>(MO.getImm());
422 } else if (MO.isFPImm()) {
423 return static_cast<unsigned>(APFloat(MO.getFPImm())
424 .bitcastToAPInt().getHiBits(32).getLimitedValue());
427 llvm_unreachable("Unable to encode MCOperand!");
430 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
431 bool ARMMCCodeEmitter::
432 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
433 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
434 const MCOperand &MO = MI.getOperand(OpIdx);
435 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
437 Reg = getARMRegisterNumbering(MO.getReg());
439 int32_t SImm = MO1.getImm();
442 // Special value for #-0
443 if (SImm == INT32_MIN) {
448 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
458 /// getBranchTargetOpValue - Helper function to get the branch target operand,
459 /// which is either an immediate or requires a fixup.
460 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
462 SmallVectorImpl<MCFixup> &Fixups) {
463 const MCOperand &MO = MI.getOperand(OpIdx);
465 // If the destination is an immediate, we have nothing to do.
466 if (MO.isImm()) return MO.getImm();
467 assert(MO.isExpr() && "Unexpected branch target type!");
468 const MCExpr *Expr = MO.getExpr();
469 MCFixupKind Kind = MCFixupKind(FixupKind);
470 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
472 // All of the information is in the fixup.
476 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
477 // determined by negating them and XOR'ing them with bit 23.
478 static int32_t encodeThumbBLOffset(int32_t offset) {
480 uint32_t S = (offset & 0x800000) >> 23;
481 uint32_t J1 = (offset & 0x400000) >> 22;
482 uint32_t J2 = (offset & 0x200000) >> 21;
495 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
496 uint32_t ARMMCCodeEmitter::
497 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
498 SmallVectorImpl<MCFixup> &Fixups) const {
499 const MCOperand MO = MI.getOperand(OpIdx);
501 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
503 return encodeThumbBLOffset(MO.getImm());
506 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
507 /// BLX branch target.
508 uint32_t ARMMCCodeEmitter::
509 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
510 SmallVectorImpl<MCFixup> &Fixups) const {
511 const MCOperand MO = MI.getOperand(OpIdx);
513 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
515 return encodeThumbBLOffset(MO.getImm());
518 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
519 uint32_t ARMMCCodeEmitter::
520 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
521 SmallVectorImpl<MCFixup> &Fixups) const {
522 const MCOperand MO = MI.getOperand(OpIdx);
524 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
526 return (MO.getImm() >> 1);
529 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
530 uint32_t ARMMCCodeEmitter::
531 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
532 SmallVectorImpl<MCFixup> &Fixups) const {
533 const MCOperand MO = MI.getOperand(OpIdx);
535 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
537 return (MO.getImm() >> 1);
540 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
541 uint32_t ARMMCCodeEmitter::
542 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
543 SmallVectorImpl<MCFixup> &Fixups) const {
544 const MCOperand MO = MI.getOperand(OpIdx);
546 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
547 return (MO.getImm() >> 1);
550 /// Return true if this branch has a non-always predication
551 static bool HasConditionalBranch(const MCInst &MI) {
552 int NumOp = MI.getNumOperands();
554 for (int i = 0; i < NumOp-1; ++i) {
555 const MCOperand &MCOp1 = MI.getOperand(i);
556 const MCOperand &MCOp2 = MI.getOperand(i + 1);
557 if (MCOp1.isImm() && MCOp2.isReg() &&
558 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
559 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
567 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
569 uint32_t ARMMCCodeEmitter::
570 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
571 SmallVectorImpl<MCFixup> &Fixups) const {
572 // FIXME: This really, really shouldn't use TargetMachine. We don't want
573 // coupling between MC and TM anywhere we can help it.
576 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
577 return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
580 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
582 uint32_t ARMMCCodeEmitter::
583 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
584 SmallVectorImpl<MCFixup> &Fixups) const {
585 const MCOperand MO = MI.getOperand(OpIdx);
587 if (HasConditionalBranch(MI))
588 return ::getBranchTargetOpValue(MI, OpIdx,
589 ARM::fixup_arm_condbranch, Fixups);
590 return ::getBranchTargetOpValue(MI, OpIdx,
591 ARM::fixup_arm_uncondbranch, Fixups);
594 return MO.getImm() >> 2;
597 uint32_t ARMMCCodeEmitter::
598 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
599 SmallVectorImpl<MCFixup> &Fixups) const {
600 const MCOperand MO = MI.getOperand(OpIdx);
602 if (HasConditionalBranch(MI))
603 return ::getBranchTargetOpValue(MI, OpIdx,
604 ARM::fixup_arm_condbl, Fixups);
605 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups);
608 return MO.getImm() >> 2;
611 uint32_t ARMMCCodeEmitter::
612 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
613 SmallVectorImpl<MCFixup> &Fixups) const {
614 const MCOperand MO = MI.getOperand(OpIdx);
616 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups);
618 return MO.getImm() >> 1;
621 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
622 /// immediate branch target.
623 uint32_t ARMMCCodeEmitter::
624 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
625 SmallVectorImpl<MCFixup> &Fixups) const {
627 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
628 bool I = (Val & 0x800000);
629 bool J1 = (Val & 0x400000);
630 bool J2 = (Val & 0x200000);
644 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
645 /// ADR label target.
646 uint32_t ARMMCCodeEmitter::
647 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
648 SmallVectorImpl<MCFixup> &Fixups) const {
649 const MCOperand MO = MI.getOperand(OpIdx);
651 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
653 int32_t offset = MO.getImm();
654 uint32_t Val = 0x2000;
656 if (offset == INT32_MIN) {
659 } else if (offset < 0) {
664 int SoImmVal = ARM_AM::getSOImmVal(offset);
665 assert(SoImmVal != -1 && "Not a valid so_imm value!");
671 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
673 uint32_t ARMMCCodeEmitter::
674 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
675 SmallVectorImpl<MCFixup> &Fixups) const {
676 const MCOperand MO = MI.getOperand(OpIdx);
678 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
680 int32_t Val = MO.getImm();
681 if (Val == INT32_MIN)
690 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
692 uint32_t ARMMCCodeEmitter::
693 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
694 SmallVectorImpl<MCFixup> &Fixups) const {
695 const MCOperand MO = MI.getOperand(OpIdx);
697 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
702 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
704 uint32_t ARMMCCodeEmitter::
705 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
706 SmallVectorImpl<MCFixup> &) const {
710 const MCOperand &MO1 = MI.getOperand(OpIdx);
711 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
712 unsigned Rn = getARMRegisterNumbering(MO1.getReg());
713 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
714 return (Rm << 3) | Rn;
717 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
718 uint32_t ARMMCCodeEmitter::
719 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
720 SmallVectorImpl<MCFixup> &Fixups) const {
722 // {12} = (U)nsigned (add == '1', sub == '0')
726 // If The first operand isn't a register, we have a label reference.
727 const MCOperand &MO = MI.getOperand(OpIdx);
729 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
731 isAdd = false ; // 'U' bit is set as part of the fixup.
734 const MCExpr *Expr = MO.getExpr();
738 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
740 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
741 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
743 ++MCNumCPRelocations;
746 int32_t Offset = MO.getImm();
747 // FIXME: Handle #-0.
755 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
757 uint32_t Binary = Imm12 & 0xfff;
758 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
761 Binary |= (Reg << 13);
765 /// getT2Imm8s4OpValue - Return encoding info for
766 /// '+/- imm8<<2' operand.
767 uint32_t ARMMCCodeEmitter::
768 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
769 SmallVectorImpl<MCFixup> &Fixups) const {
770 // FIXME: The immediate operand should have already been encoded like this
771 // before ever getting here. The encoder method should just need to combine
772 // the MI operands for the register and the offset into a single
773 // representation for the complex operand in the .td file. This isn't just
774 // style, unfortunately. As-is, we can't represent the distinct encoding
777 // {8} = (U)nsigned (add == '1', sub == '0')
779 int32_t Imm8 = MI.getOperand(OpIdx).getImm();
780 bool isAdd = Imm8 >= 0;
782 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
789 uint32_t Binary = Imm8 & 0xff;
790 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
796 /// getT2AddrModeImm8s4OpValue - Return encoding info for
797 /// 'reg +/- imm8<<2' operand.
798 uint32_t ARMMCCodeEmitter::
799 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
800 SmallVectorImpl<MCFixup> &Fixups) const {
802 // {8} = (U)nsigned (add == '1', sub == '0')
806 // If The first operand isn't a register, we have a label reference.
807 const MCOperand &MO = MI.getOperand(OpIdx);
809 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
811 isAdd = false ; // 'U' bit is set as part of the fixup.
813 assert(MO.isExpr() && "Unexpected machine operand type!");
814 const MCExpr *Expr = MO.getExpr();
815 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
816 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
818 ++MCNumCPRelocations;
820 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
822 // FIXME: The immediate operand should have already been encoded like this
823 // before ever getting here. The encoder method should just need to combine
824 // the MI operands for the register and the offset into a single
825 // representation for the complex operand in the .td file. This isn't just
826 // style, unfortunately. As-is, we can't represent the distinct encoding
828 uint32_t Binary = (Imm8 >> 2) & 0xff;
829 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
832 Binary |= (Reg << 9);
836 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
837 /// 'reg + imm8<<2' operand.
838 uint32_t ARMMCCodeEmitter::
839 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
840 SmallVectorImpl<MCFixup> &Fixups) const {
843 const MCOperand &MO = MI.getOperand(OpIdx);
844 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
845 unsigned Reg = getARMRegisterNumbering(MO.getReg());
846 unsigned Imm8 = MO1.getImm();
847 return (Reg << 8) | Imm8;
850 // FIXME: This routine assumes that a binary
851 // expression will always result in a PCRel expression
852 // In reality, its only true if one or more subexpressions
853 // is itself a PCRel (i.e. "." in asm or some other pcrel construct)
854 // but this is good enough for now.
855 static bool EvaluateAsPCRel(const MCExpr *Expr) {
856 switch (Expr->getKind()) {
857 default: llvm_unreachable("Unexpected expression type");
858 case MCExpr::SymbolRef: return false;
859 case MCExpr::Binary: return true;
864 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
865 SmallVectorImpl<MCFixup> &Fixups) const {
866 // {20-16} = imm{15-12}
867 // {11-0} = imm{11-0}
868 const MCOperand &MO = MI.getOperand(OpIdx);
870 // Hi / lo 16 bits already extracted during earlier passes.
871 return static_cast<unsigned>(MO.getImm());
873 // Handle :upper16: and :lower16: assembly prefixes.
874 const MCExpr *E = MO.getExpr();
876 if (E->getKind() == MCExpr::Target) {
877 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
878 E = ARM16Expr->getSubExpr();
880 switch (ARM16Expr->getKind()) {
881 default: llvm_unreachable("Unsupported ARMFixup");
882 case ARMMCExpr::VK_ARM_HI16:
883 if (!isTargetDarwin() && EvaluateAsPCRel(E))
884 Kind = MCFixupKind(isThumb2()
885 ? ARM::fixup_t2_movt_hi16_pcrel
886 : ARM::fixup_arm_movt_hi16_pcrel);
888 Kind = MCFixupKind(isThumb2()
889 ? ARM::fixup_t2_movt_hi16
890 : ARM::fixup_arm_movt_hi16);
892 case ARMMCExpr::VK_ARM_LO16:
893 if (!isTargetDarwin() && EvaluateAsPCRel(E))
894 Kind = MCFixupKind(isThumb2()
895 ? ARM::fixup_t2_movw_lo16_pcrel
896 : ARM::fixup_arm_movw_lo16_pcrel);
898 Kind = MCFixupKind(isThumb2()
899 ? ARM::fixup_t2_movw_lo16
900 : ARM::fixup_arm_movw_lo16);
903 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
906 // If the expression doesn't have :upper16: or :lower16: on it,
907 // it's just a plain immediate expression, and those evaluate to
908 // the lower 16 bits of the expression regardless of whether
909 // we have a movt or a movw.
910 if (!isTargetDarwin() && EvaluateAsPCRel(E))
911 Kind = MCFixupKind(isThumb2()
912 ? ARM::fixup_t2_movw_lo16_pcrel
913 : ARM::fixup_arm_movw_lo16_pcrel);
915 Kind = MCFixupKind(isThumb2()
916 ? ARM::fixup_t2_movw_lo16
917 : ARM::fixup_arm_movw_lo16);
918 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
922 uint32_t ARMMCCodeEmitter::
923 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
924 SmallVectorImpl<MCFixup> &Fixups) const {
925 const MCOperand &MO = MI.getOperand(OpIdx);
926 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
927 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
928 unsigned Rn = getARMRegisterNumbering(MO.getReg());
929 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
930 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
931 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
932 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
933 unsigned SBits = getShiftOp(ShOp);
942 uint32_t Binary = Rm;
944 Binary |= SBits << 5;
945 Binary |= ShImm << 7;
951 uint32_t ARMMCCodeEmitter::
952 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
953 SmallVectorImpl<MCFixup> &Fixups) const {
955 // {13} 1 == imm12, 0 == Rm
958 const MCOperand &MO = MI.getOperand(OpIdx);
959 unsigned Rn = getARMRegisterNumbering(MO.getReg());
960 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
965 uint32_t ARMMCCodeEmitter::
966 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
967 SmallVectorImpl<MCFixup> &Fixups) const {
968 // {13} 1 == imm12, 0 == Rm
971 const MCOperand &MO = MI.getOperand(OpIdx);
972 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
973 unsigned Imm = MO1.getImm();
974 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
975 bool isReg = MO.getReg() != 0;
976 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
977 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
979 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
980 Binary <<= 7; // Shift amount is bits [11:7]
981 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
982 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
984 return Binary | (isAdd << 12) | (isReg << 13);
987 uint32_t ARMMCCodeEmitter::
988 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
989 SmallVectorImpl<MCFixup> &Fixups) const {
992 const MCOperand &MO = MI.getOperand(OpIdx);
993 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
994 bool isAdd = MO1.getImm() != 0;
995 return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4);
998 uint32_t ARMMCCodeEmitter::
999 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1000 SmallVectorImpl<MCFixup> &Fixups) const {
1001 // {9} 1 == imm8, 0 == Rm
1003 // {7-4} imm7_4/zero
1005 const MCOperand &MO = MI.getOperand(OpIdx);
1006 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1007 unsigned Imm = MO1.getImm();
1008 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1009 bool isImm = MO.getReg() == 0;
1010 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1011 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1013 Imm8 = getARMRegisterNumbering(MO.getReg());
1014 return Imm8 | (isAdd << 8) | (isImm << 9);
1017 uint32_t ARMMCCodeEmitter::
1018 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1019 SmallVectorImpl<MCFixup> &Fixups) const {
1020 // {13} 1 == imm8, 0 == Rm
1023 // {7-4} imm7_4/zero
1025 const MCOperand &MO = MI.getOperand(OpIdx);
1026 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1027 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1029 // If The first operand isn't a register, we have a label reference.
1031 unsigned Rn = getARMRegisterNumbering(ARM::PC); // Rn is PC.
1033 assert(MO.isExpr() && "Unexpected machine operand type!");
1034 const MCExpr *Expr = MO.getExpr();
1035 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1036 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1038 ++MCNumCPRelocations;
1039 return (Rn << 9) | (1 << 13);
1041 unsigned Rn = getARMRegisterNumbering(MO.getReg());
1042 unsigned Imm = MO2.getImm();
1043 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1044 bool isImm = MO1.getReg() == 0;
1045 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1046 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1048 Imm8 = getARMRegisterNumbering(MO1.getReg());
1049 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1052 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1053 uint32_t ARMMCCodeEmitter::
1054 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1055 SmallVectorImpl<MCFixup> &Fixups) const {
1058 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1059 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1060 "Unexpected base register!");
1062 // The immediate is already shifted for the implicit zeroes, so no change
1064 return MO1.getImm() & 0xff;
1067 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1068 uint32_t ARMMCCodeEmitter::
1069 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1070 SmallVectorImpl<MCFixup> &Fixups) const {
1074 const MCOperand &MO = MI.getOperand(OpIdx);
1075 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1076 unsigned Rn = getARMRegisterNumbering(MO.getReg());
1077 unsigned Imm5 = MO1.getImm();
1078 return ((Imm5 & 0x1f) << 3) | Rn;
1081 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1082 uint32_t ARMMCCodeEmitter::
1083 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1084 SmallVectorImpl<MCFixup> &Fixups) const {
1085 const MCOperand MO = MI.getOperand(OpIdx);
1087 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
1088 return (MO.getImm() >> 2);
1091 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1092 uint32_t ARMMCCodeEmitter::
1093 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1094 SmallVectorImpl<MCFixup> &Fixups) const {
1096 // {8} = (U)nsigned (add == '1', sub == '0')
1100 // If The first operand isn't a register, we have a label reference.
1101 const MCOperand &MO = MI.getOperand(OpIdx);
1103 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
1105 isAdd = false; // 'U' bit is handled as part of the fixup.
1107 assert(MO.isExpr() && "Unexpected machine operand type!");
1108 const MCExpr *Expr = MO.getExpr();
1111 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1113 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1114 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1116 ++MCNumCPRelocations;
1118 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
1119 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1122 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1123 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1126 Binary |= (Reg << 9);
1130 unsigned ARMMCCodeEmitter::
1131 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1132 SmallVectorImpl<MCFixup> &Fixups) const {
1133 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1134 // shifted. The second is Rs, the amount to shift by, and the third specifies
1135 // the type of the shift.
1143 const MCOperand &MO = MI.getOperand(OpIdx);
1144 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1145 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1146 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1149 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1151 // Encode the shift opcode.
1153 unsigned Rs = MO1.getReg();
1155 // Set shift operand (bit[7:4]).
1161 default: llvm_unreachable("Unknown shift opc!");
1162 case ARM_AM::lsl: SBits = 0x1; break;
1163 case ARM_AM::lsr: SBits = 0x3; break;
1164 case ARM_AM::asr: SBits = 0x5; break;
1165 case ARM_AM::ror: SBits = 0x7; break;
1169 Binary |= SBits << 4;
1171 // Encode the shift operation Rs.
1172 // Encode Rs bit[11:8].
1173 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1174 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
1177 unsigned ARMMCCodeEmitter::
1178 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1179 SmallVectorImpl<MCFixup> &Fixups) const {
1180 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1181 // shifted. The second is the amount to shift by.
1188 const MCOperand &MO = MI.getOperand(OpIdx);
1189 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1190 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1193 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1195 // Encode the shift opcode.
1198 // Set shift operand (bit[6:4]).
1203 // RRX - 110 and bit[11:8] clear.
1205 default: llvm_unreachable("Unknown shift opc!");
1206 case ARM_AM::lsl: SBits = 0x0; break;
1207 case ARM_AM::lsr: SBits = 0x2; break;
1208 case ARM_AM::asr: SBits = 0x4; break;
1209 case ARM_AM::ror: SBits = 0x6; break;
1215 // Encode shift_imm bit[11:7].
1216 Binary |= SBits << 4;
1217 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1218 assert(Offset < 32 && "Offset must be in range 0-31!");
1219 return Binary | (Offset << 7);
1223 unsigned ARMMCCodeEmitter::
1224 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1225 SmallVectorImpl<MCFixup> &Fixups) const {
1226 const MCOperand &MO1 = MI.getOperand(OpNum);
1227 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1228 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1230 // Encoded as [Rn, Rm, imm].
1231 // FIXME: Needs fixup support.
1232 unsigned Value = getARMRegisterNumbering(MO1.getReg());
1234 Value |= getARMRegisterNumbering(MO2.getReg());
1236 Value |= MO3.getImm();
1241 unsigned ARMMCCodeEmitter::
1242 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1243 SmallVectorImpl<MCFixup> &Fixups) const {
1244 const MCOperand &MO1 = MI.getOperand(OpNum);
1245 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1247 // FIXME: Needs fixup support.
1248 unsigned Value = getARMRegisterNumbering(MO1.getReg());
1250 // Even though the immediate is 8 bits long, we need 9 bits in order
1251 // to represent the (inverse of the) sign bit.
1253 int32_t tmp = (int32_t)MO2.getImm();
1257 Value |= 256; // Set the ADD bit
1262 unsigned ARMMCCodeEmitter::
1263 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1264 SmallVectorImpl<MCFixup> &Fixups) const {
1265 const MCOperand &MO1 = MI.getOperand(OpNum);
1267 // FIXME: Needs fixup support.
1269 int32_t tmp = (int32_t)MO1.getImm();
1273 Value |= 256; // Set the ADD bit
1278 unsigned ARMMCCodeEmitter::
1279 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1280 SmallVectorImpl<MCFixup> &Fixups) const {
1281 const MCOperand &MO1 = MI.getOperand(OpNum);
1283 // FIXME: Needs fixup support.
1285 int32_t tmp = (int32_t)MO1.getImm();
1289 Value |= 4096; // Set the ADD bit
1290 Value |= tmp & 4095;
1294 unsigned ARMMCCodeEmitter::
1295 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1296 SmallVectorImpl<MCFixup> &Fixups) const {
1297 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1298 // shifted. The second is the amount to shift by.
1305 const MCOperand &MO = MI.getOperand(OpIdx);
1306 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1307 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1310 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1312 // Encode the shift opcode.
1314 // Set shift operand (bit[6:4]).
1320 default: llvm_unreachable("Unknown shift opc!");
1321 case ARM_AM::lsl: SBits = 0x0; break;
1322 case ARM_AM::lsr: SBits = 0x2; break;
1323 case ARM_AM::asr: SBits = 0x4; break;
1324 case ARM_AM::rrx: // FALLTHROUGH
1325 case ARM_AM::ror: SBits = 0x6; break;
1328 Binary |= SBits << 4;
1329 if (SOpc == ARM_AM::rrx)
1332 // Encode shift_imm bit[11:7].
1333 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1336 unsigned ARMMCCodeEmitter::
1337 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1338 SmallVectorImpl<MCFixup> &Fixups) const {
1339 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1341 const MCOperand &MO = MI.getOperand(Op);
1342 uint32_t v = ~MO.getImm();
1343 uint32_t lsb = CountTrailingZeros_32(v);
1344 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1345 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1346 return lsb | (msb << 5);
1349 unsigned ARMMCCodeEmitter::
1350 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1351 SmallVectorImpl<MCFixup> &Fixups) const {
1354 // {7-0} = Number of registers
1357 // {15-0} = Bitfield of GPRs.
1358 unsigned Reg = MI.getOperand(Op).getReg();
1359 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1360 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1362 unsigned Binary = 0;
1364 if (SPRRegs || DPRRegs) {
1366 unsigned RegNo = getARMRegisterNumbering(Reg);
1367 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1368 Binary |= (RegNo & 0x1f) << 8;
1372 Binary |= NumRegs * 2;
1374 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1375 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1376 Binary |= 1 << RegNo;
1383 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1384 /// with the alignment operand.
1385 unsigned ARMMCCodeEmitter::
1386 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1387 SmallVectorImpl<MCFixup> &Fixups) const {
1388 const MCOperand &Reg = MI.getOperand(Op);
1389 const MCOperand &Imm = MI.getOperand(Op + 1);
1391 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1394 switch (Imm.getImm()) {
1398 case 8: Align = 0x01; break;
1399 case 16: Align = 0x02; break;
1400 case 32: Align = 0x03; break;
1403 return RegNo | (Align << 4);
1406 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1407 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1408 unsigned ARMMCCodeEmitter::
1409 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1410 SmallVectorImpl<MCFixup> &Fixups) const {
1411 const MCOperand &Reg = MI.getOperand(Op);
1412 const MCOperand &Imm = MI.getOperand(Op + 1);
1414 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1417 switch (Imm.getImm()) {
1421 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1422 case 2: Align = 0x00; break;
1423 case 4: Align = 0x03; break;
1426 return RegNo | (Align << 4);
1430 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1431 /// alignment operand for use in VLD-dup instructions. This is the same as
1432 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1433 /// different for VLD4-dup.
1434 unsigned ARMMCCodeEmitter::
1435 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1436 SmallVectorImpl<MCFixup> &Fixups) const {
1437 const MCOperand &Reg = MI.getOperand(Op);
1438 const MCOperand &Imm = MI.getOperand(Op + 1);
1440 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1443 switch (Imm.getImm()) {
1447 case 8: Align = 0x01; break;
1448 case 16: Align = 0x03; break;
1451 return RegNo | (Align << 4);
1454 unsigned ARMMCCodeEmitter::
1455 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1456 SmallVectorImpl<MCFixup> &Fixups) const {
1457 const MCOperand &MO = MI.getOperand(Op);
1458 if (MO.getReg() == 0) return 0x0D;
1459 return getARMRegisterNumbering(MO.getReg());
1462 unsigned ARMMCCodeEmitter::
1463 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1464 SmallVectorImpl<MCFixup> &Fixups) const {
1465 return 8 - MI.getOperand(Op).getImm();
1468 unsigned ARMMCCodeEmitter::
1469 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1470 SmallVectorImpl<MCFixup> &Fixups) const {
1471 return 16 - MI.getOperand(Op).getImm();
1474 unsigned ARMMCCodeEmitter::
1475 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1476 SmallVectorImpl<MCFixup> &Fixups) const {
1477 return 32 - MI.getOperand(Op).getImm();
1480 unsigned ARMMCCodeEmitter::
1481 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1482 SmallVectorImpl<MCFixup> &Fixups) const {
1483 return 64 - MI.getOperand(Op).getImm();
1486 void ARMMCCodeEmitter::
1487 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1488 SmallVectorImpl<MCFixup> &Fixups) const {
1489 // Pseudo instructions don't get encoded.
1490 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1491 uint64_t TSFlags = Desc.TSFlags;
1492 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1496 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1497 Size = Desc.getSize();
1499 llvm_unreachable("Unexpected instruction size!");
1501 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1502 // Thumb 32-bit wide instructions need to emit the high order halfword
1504 if (isThumb() && Size == 4) {
1505 EmitConstant(Binary >> 16, 2, OS);
1506 EmitConstant(Binary & 0xffff, 2, OS);
1508 EmitConstant(Binary, Size, OS);
1509 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1512 #include "ARMGenMCCodeEmitter.inc"