1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/ARMMCTargetDesc.h"
16 #include "MCTargetDesc/ARMAddressingModes.h"
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "MCTargetDesc/ARMFixupKinds.h"
19 #include "MCTargetDesc/ARMMCExpr.h"
20 #include "llvm/ADT/APFloat.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/Support/raw_ostream.h"
33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
34 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
37 class ARMMCCodeEmitter : public MCCodeEmitter {
38 ARMMCCodeEmitter(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION;
39 void operator=(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION;
40 const MCInstrInfo &MCII;
41 const MCSubtargetInfo &STI;
45 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
47 : MCII(mcii), STI(sti), CTX(ctx) {
50 ~ARMMCCodeEmitter() {}
52 bool isThumb() const {
53 // FIXME: Can tablegen auto-generate this?
54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
56 bool isThumb2() const {
57 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
59 bool isTargetDarwin() const {
60 Triple TT(STI.getTargetTriple());
61 Triple::OSType OS = TT.getOS();
62 return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS;
65 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
67 // getBinaryCodeForInstr - TableGen'erated function for getting the
68 // binary encoding for an instruction.
69 uint64_t getBinaryCodeForInstr(const MCInst &MI,
70 SmallVectorImpl<MCFixup> &Fixups) const;
72 /// getMachineOpValue - Return binary encoding of operand. If the machine
73 /// operand requires relocation, record the relocation and return zero.
74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
75 SmallVectorImpl<MCFixup> &Fixups) const;
77 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
78 /// the specified operand. This is used for operands with :lower16: and
79 /// :upper16: prefixes.
80 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
81 SmallVectorImpl<MCFixup> &Fixups) const;
83 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
84 unsigned &Reg, unsigned &Imm,
85 SmallVectorImpl<MCFixup> &Fixups) const;
87 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
89 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
90 SmallVectorImpl<MCFixup> &Fixups) const;
92 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
93 /// BLX branch target.
94 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
95 SmallVectorImpl<MCFixup> &Fixups) const;
97 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
98 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
99 SmallVectorImpl<MCFixup> &Fixups) const;
101 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
102 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 SmallVectorImpl<MCFixup> &Fixups) const;
105 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
106 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
107 SmallVectorImpl<MCFixup> &Fixups) const;
109 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
111 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
112 SmallVectorImpl<MCFixup> &Fixups) const;
114 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
115 /// immediate Thumb2 direct branch target.
116 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
117 SmallVectorImpl<MCFixup> &Fixups) const;
119 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
121 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
122 SmallVectorImpl<MCFixup> &Fixups) const;
123 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
124 SmallVectorImpl<MCFixup> &Fixups) const;
125 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
126 SmallVectorImpl<MCFixup> &Fixups) const;
128 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
129 /// ADR label target.
130 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
131 SmallVectorImpl<MCFixup> &Fixups) const;
132 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
133 SmallVectorImpl<MCFixup> &Fixups) const;
134 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
135 SmallVectorImpl<MCFixup> &Fixups) const;
138 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
140 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
141 SmallVectorImpl<MCFixup> &Fixups) const;
143 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
144 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
145 SmallVectorImpl<MCFixup> &Fixups)const;
147 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
149 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
150 SmallVectorImpl<MCFixup> &Fixups) const;
152 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
154 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
155 SmallVectorImpl<MCFixup> &Fixups) const;
157 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
159 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
160 SmallVectorImpl<MCFixup> &Fixups) const;
163 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
164 /// operand as needed by load/store instructions.
165 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
166 SmallVectorImpl<MCFixup> &Fixups) const;
168 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
169 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
170 SmallVectorImpl<MCFixup> &Fixups) const {
171 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
173 default: llvm_unreachable("Unknown addressing sub-mode!");
174 case ARM_AM::da: return 0;
175 case ARM_AM::ia: return 1;
176 case ARM_AM::db: return 2;
177 case ARM_AM::ib: return 3;
180 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
182 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
184 case ARM_AM::no_shift:
185 case ARM_AM::lsl: return 0;
186 case ARM_AM::lsr: return 1;
187 case ARM_AM::asr: return 2;
189 case ARM_AM::rrx: return 3;
191 llvm_unreachable("Invalid ShiftOpc!");
194 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
195 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
196 SmallVectorImpl<MCFixup> &Fixups) const;
198 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
199 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
200 SmallVectorImpl<MCFixup> &Fixups) const;
202 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
203 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
204 SmallVectorImpl<MCFixup> &Fixups) const;
206 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
207 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
208 SmallVectorImpl<MCFixup> &Fixups) const;
210 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
211 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
212 SmallVectorImpl<MCFixup> &Fixups) const;
214 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
216 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
217 SmallVectorImpl<MCFixup> &Fixups) const;
219 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
220 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
221 SmallVectorImpl<MCFixup> &Fixups) const;
223 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
224 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
225 SmallVectorImpl<MCFixup> &Fixups) const;
227 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
228 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
229 SmallVectorImpl<MCFixup> &Fixups) const;
231 /// getCCOutOpValue - Return encoding of the 's' bit.
232 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
233 SmallVectorImpl<MCFixup> &Fixups) const {
234 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
236 return MI.getOperand(Op).getReg() == ARM::CPSR;
239 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
240 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
241 SmallVectorImpl<MCFixup> &Fixups) const {
242 unsigned SoImm = MI.getOperand(Op).getImm();
243 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
244 assert(SoImmVal != -1 && "Not a valid so_imm value!");
246 // Encode rotate_imm.
247 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
248 << ARMII::SoRotImmShift;
251 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
255 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
256 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
257 SmallVectorImpl<MCFixup> &Fixups) const {
258 unsigned SoImm = MI.getOperand(Op).getImm();
259 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
260 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
264 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
265 SmallVectorImpl<MCFixup> &Fixups) const;
266 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
267 SmallVectorImpl<MCFixup> &Fixups) const;
268 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
269 SmallVectorImpl<MCFixup> &Fixups) const;
270 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
271 SmallVectorImpl<MCFixup> &Fixups) const;
273 /// getSORegOpValue - Return an encoded so_reg shifted register value.
274 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
275 SmallVectorImpl<MCFixup> &Fixups) const;
276 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
277 SmallVectorImpl<MCFixup> &Fixups) const;
278 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
279 SmallVectorImpl<MCFixup> &Fixups) const;
281 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
282 SmallVectorImpl<MCFixup> &Fixups) const {
283 return 64 - MI.getOperand(Op).getImm();
286 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
287 SmallVectorImpl<MCFixup> &Fixups) const;
289 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
290 SmallVectorImpl<MCFixup> &Fixups) const;
291 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
292 SmallVectorImpl<MCFixup> &Fixups) const;
293 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
294 SmallVectorImpl<MCFixup> &Fixups) const;
295 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
296 SmallVectorImpl<MCFixup> &Fixups) const;
297 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
298 SmallVectorImpl<MCFixup> &Fixups) const;
300 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
301 SmallVectorImpl<MCFixup> &Fixups) const;
302 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
303 SmallVectorImpl<MCFixup> &Fixups) const;
304 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
305 SmallVectorImpl<MCFixup> &Fixups) const;
306 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
307 SmallVectorImpl<MCFixup> &Fixups) const;
309 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
310 SmallVectorImpl<MCFixup> &Fixups) const;
312 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
313 unsigned EncodedValue) const;
314 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
315 unsigned EncodedValue) const;
316 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
317 unsigned EncodedValue) const;
319 unsigned VFPThumb2PostEncoder(const MCInst &MI,
320 unsigned EncodedValue) const;
322 void EmitByte(unsigned char C, raw_ostream &OS) const {
326 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
327 // Output the constant in little endian byte order.
328 for (unsigned i = 0; i != Size; ++i) {
329 EmitByte(Val & 255, OS);
334 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
335 SmallVectorImpl<MCFixup> &Fixups) const;
338 } // end anonymous namespace
340 MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
341 const MCRegisterInfo &MRI,
342 const MCSubtargetInfo &STI,
344 return new ARMMCCodeEmitter(MCII, STI, Ctx);
347 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
348 /// instructions, and rewrite them to their Thumb2 form if we are currently in
350 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
351 unsigned EncodedValue) const {
353 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
354 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
356 unsigned Bit24 = EncodedValue & 0x01000000;
357 unsigned Bit28 = Bit24 << 4;
358 EncodedValue &= 0xEFFFFFFF;
359 EncodedValue |= Bit28;
360 EncodedValue |= 0x0F000000;
366 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
367 /// instructions, and rewrite them to their Thumb2 form if we are currently in
369 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
370 unsigned EncodedValue) const {
372 EncodedValue &= 0xF0FFFFFF;
373 EncodedValue |= 0x09000000;
379 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
380 /// instructions, and rewrite them to their Thumb2 form if we are currently in
382 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
383 unsigned EncodedValue) const {
385 EncodedValue &= 0x00FFFFFF;
386 EncodedValue |= 0xEE000000;
392 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
393 /// them to their Thumb2 form if we are currently in Thumb2 mode.
394 unsigned ARMMCCodeEmitter::
395 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
397 EncodedValue &= 0x0FFFFFFF;
398 EncodedValue |= 0xE0000000;
403 /// getMachineOpValue - Return binary encoding of operand. If the machine
404 /// operand requires relocation, record the relocation and return zero.
405 unsigned ARMMCCodeEmitter::
406 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
407 SmallVectorImpl<MCFixup> &Fixups) const {
409 unsigned Reg = MO.getReg();
410 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg);
412 // Q registers are encoded as 2x their register number.
416 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
417 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
418 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
419 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
422 } else if (MO.isImm()) {
423 return static_cast<unsigned>(MO.getImm());
424 } else if (MO.isFPImm()) {
425 return static_cast<unsigned>(APFloat(MO.getFPImm())
426 .bitcastToAPInt().getHiBits(32).getLimitedValue());
429 llvm_unreachable("Unable to encode MCOperand!");
432 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
433 bool ARMMCCodeEmitter::
434 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
435 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
436 const MCOperand &MO = MI.getOperand(OpIdx);
437 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
439 Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
441 int32_t SImm = MO1.getImm();
444 // Special value for #-0
445 if (SImm == INT32_MIN) {
450 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
460 /// getBranchTargetOpValue - Helper function to get the branch target operand,
461 /// which is either an immediate or requires a fixup.
462 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
464 SmallVectorImpl<MCFixup> &Fixups) {
465 const MCOperand &MO = MI.getOperand(OpIdx);
467 // If the destination is an immediate, we have nothing to do.
468 if (MO.isImm()) return MO.getImm();
469 assert(MO.isExpr() && "Unexpected branch target type!");
470 const MCExpr *Expr = MO.getExpr();
471 MCFixupKind Kind = MCFixupKind(FixupKind);
472 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
474 // All of the information is in the fixup.
478 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
479 // determined by negating them and XOR'ing them with bit 23.
480 static int32_t encodeThumbBLOffset(int32_t offset) {
482 uint32_t S = (offset & 0x800000) >> 23;
483 uint32_t J1 = (offset & 0x400000) >> 22;
484 uint32_t J2 = (offset & 0x200000) >> 21;
497 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
498 uint32_t ARMMCCodeEmitter::
499 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
500 SmallVectorImpl<MCFixup> &Fixups) const {
501 const MCOperand MO = MI.getOperand(OpIdx);
503 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
505 return encodeThumbBLOffset(MO.getImm());
508 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
509 /// BLX branch target.
510 uint32_t ARMMCCodeEmitter::
511 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
512 SmallVectorImpl<MCFixup> &Fixups) const {
513 const MCOperand MO = MI.getOperand(OpIdx);
515 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
517 return encodeThumbBLOffset(MO.getImm());
520 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
521 uint32_t ARMMCCodeEmitter::
522 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
523 SmallVectorImpl<MCFixup> &Fixups) const {
524 const MCOperand MO = MI.getOperand(OpIdx);
526 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
528 return (MO.getImm() >> 1);
531 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
532 uint32_t ARMMCCodeEmitter::
533 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
534 SmallVectorImpl<MCFixup> &Fixups) const {
535 const MCOperand MO = MI.getOperand(OpIdx);
537 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
539 return (MO.getImm() >> 1);
542 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
543 uint32_t ARMMCCodeEmitter::
544 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
545 SmallVectorImpl<MCFixup> &Fixups) const {
546 const MCOperand MO = MI.getOperand(OpIdx);
548 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
549 return (MO.getImm() >> 1);
552 /// Return true if this branch has a non-always predication
553 static bool HasConditionalBranch(const MCInst &MI) {
554 int NumOp = MI.getNumOperands();
556 for (int i = 0; i < NumOp-1; ++i) {
557 const MCOperand &MCOp1 = MI.getOperand(i);
558 const MCOperand &MCOp2 = MI.getOperand(i + 1);
559 if (MCOp1.isImm() && MCOp2.isReg() &&
560 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
561 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
569 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
571 uint32_t ARMMCCodeEmitter::
572 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
573 SmallVectorImpl<MCFixup> &Fixups) const {
574 // FIXME: This really, really shouldn't use TargetMachine. We don't want
575 // coupling between MC and TM anywhere we can help it.
578 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
579 return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
582 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
584 uint32_t ARMMCCodeEmitter::
585 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
586 SmallVectorImpl<MCFixup> &Fixups) const {
587 const MCOperand MO = MI.getOperand(OpIdx);
589 if (HasConditionalBranch(MI))
590 return ::getBranchTargetOpValue(MI, OpIdx,
591 ARM::fixup_arm_condbranch, Fixups);
592 return ::getBranchTargetOpValue(MI, OpIdx,
593 ARM::fixup_arm_uncondbranch, Fixups);
596 return MO.getImm() >> 2;
599 uint32_t ARMMCCodeEmitter::
600 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
601 SmallVectorImpl<MCFixup> &Fixups) const {
602 const MCOperand MO = MI.getOperand(OpIdx);
604 if (HasConditionalBranch(MI))
605 return ::getBranchTargetOpValue(MI, OpIdx,
606 ARM::fixup_arm_condbl, Fixups);
607 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups);
610 return MO.getImm() >> 2;
613 uint32_t ARMMCCodeEmitter::
614 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
615 SmallVectorImpl<MCFixup> &Fixups) const {
616 const MCOperand MO = MI.getOperand(OpIdx);
618 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups);
620 return MO.getImm() >> 1;
623 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
624 /// immediate branch target.
625 uint32_t ARMMCCodeEmitter::
626 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
627 SmallVectorImpl<MCFixup> &Fixups) const {
629 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
630 bool I = (Val & 0x800000);
631 bool J1 = (Val & 0x400000);
632 bool J2 = (Val & 0x200000);
646 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
647 /// ADR label target.
648 uint32_t ARMMCCodeEmitter::
649 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
650 SmallVectorImpl<MCFixup> &Fixups) const {
651 const MCOperand MO = MI.getOperand(OpIdx);
653 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
655 int32_t offset = MO.getImm();
656 uint32_t Val = 0x2000;
659 if (offset == INT32_MIN) {
662 } else if (offset < 0) {
665 SoImmVal = ARM_AM::getSOImmVal(offset);
669 SoImmVal = ARM_AM::getSOImmVal(offset);
672 SoImmVal = ARM_AM::getSOImmVal(offset);
676 SoImmVal = ARM_AM::getSOImmVal(offset);
680 assert(SoImmVal != -1 && "Not a valid so_imm value!");
686 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
688 uint32_t ARMMCCodeEmitter::
689 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
690 SmallVectorImpl<MCFixup> &Fixups) const {
691 const MCOperand MO = MI.getOperand(OpIdx);
693 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
695 int32_t Val = MO.getImm();
696 if (Val == INT32_MIN)
705 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
707 uint32_t ARMMCCodeEmitter::
708 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
709 SmallVectorImpl<MCFixup> &Fixups) const {
710 const MCOperand MO = MI.getOperand(OpIdx);
712 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
717 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
719 uint32_t ARMMCCodeEmitter::
720 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
721 SmallVectorImpl<MCFixup> &) const {
725 const MCOperand &MO1 = MI.getOperand(OpIdx);
726 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
727 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
728 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO2.getReg());
729 return (Rm << 3) | Rn;
732 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
733 uint32_t ARMMCCodeEmitter::
734 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
735 SmallVectorImpl<MCFixup> &Fixups) const {
737 // {12} = (U)nsigned (add == '1', sub == '0')
741 // If The first operand isn't a register, we have a label reference.
742 const MCOperand &MO = MI.getOperand(OpIdx);
744 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
746 isAdd = false ; // 'U' bit is set as part of the fixup.
749 const MCExpr *Expr = MO.getExpr();
753 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
755 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
756 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
758 ++MCNumCPRelocations;
761 int32_t Offset = MO.getImm();
762 // FIXME: Handle #-0.
770 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
772 uint32_t Binary = Imm12 & 0xfff;
773 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
776 Binary |= (Reg << 13);
780 /// getT2Imm8s4OpValue - Return encoding info for
781 /// '+/- imm8<<2' operand.
782 uint32_t ARMMCCodeEmitter::
783 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
784 SmallVectorImpl<MCFixup> &Fixups) const {
785 // FIXME: The immediate operand should have already been encoded like this
786 // before ever getting here. The encoder method should just need to combine
787 // the MI operands for the register and the offset into a single
788 // representation for the complex operand in the .td file. This isn't just
789 // style, unfortunately. As-is, we can't represent the distinct encoding
792 // {8} = (U)nsigned (add == '1', sub == '0')
794 int32_t Imm8 = MI.getOperand(OpIdx).getImm();
795 bool isAdd = Imm8 >= 0;
797 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
799 Imm8 = -(uint32_t)Imm8;
804 uint32_t Binary = Imm8 & 0xff;
805 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
811 /// getT2AddrModeImm8s4OpValue - Return encoding info for
812 /// 'reg +/- imm8<<2' operand.
813 uint32_t ARMMCCodeEmitter::
814 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
815 SmallVectorImpl<MCFixup> &Fixups) const {
817 // {8} = (U)nsigned (add == '1', sub == '0')
821 // If The first operand isn't a register, we have a label reference.
822 const MCOperand &MO = MI.getOperand(OpIdx);
824 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
826 isAdd = false ; // 'U' bit is set as part of the fixup.
828 assert(MO.isExpr() && "Unexpected machine operand type!");
829 const MCExpr *Expr = MO.getExpr();
830 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
831 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
833 ++MCNumCPRelocations;
835 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
837 // FIXME: The immediate operand should have already been encoded like this
838 // before ever getting here. The encoder method should just need to combine
839 // the MI operands for the register and the offset into a single
840 // representation for the complex operand in the .td file. This isn't just
841 // style, unfortunately. As-is, we can't represent the distinct encoding
843 uint32_t Binary = (Imm8 >> 2) & 0xff;
844 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
847 Binary |= (Reg << 9);
851 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
852 /// 'reg + imm8<<2' operand.
853 uint32_t ARMMCCodeEmitter::
854 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
855 SmallVectorImpl<MCFixup> &Fixups) const {
858 const MCOperand &MO = MI.getOperand(OpIdx);
859 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
860 unsigned Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
861 unsigned Imm8 = MO1.getImm();
862 return (Reg << 8) | Imm8;
865 // FIXME: This routine assumes that a binary
866 // expression will always result in a PCRel expression
867 // In reality, its only true if one or more subexpressions
868 // is itself a PCRel (i.e. "." in asm or some other pcrel construct)
869 // but this is good enough for now.
870 static bool EvaluateAsPCRel(const MCExpr *Expr) {
871 switch (Expr->getKind()) {
872 default: llvm_unreachable("Unexpected expression type");
873 case MCExpr::SymbolRef: return false;
874 case MCExpr::Binary: return true;
879 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
880 SmallVectorImpl<MCFixup> &Fixups) const {
881 // {20-16} = imm{15-12}
882 // {11-0} = imm{11-0}
883 const MCOperand &MO = MI.getOperand(OpIdx);
885 // Hi / lo 16 bits already extracted during earlier passes.
886 return static_cast<unsigned>(MO.getImm());
888 // Handle :upper16: and :lower16: assembly prefixes.
889 const MCExpr *E = MO.getExpr();
891 if (E->getKind() == MCExpr::Target) {
892 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
893 E = ARM16Expr->getSubExpr();
895 switch (ARM16Expr->getKind()) {
896 default: llvm_unreachable("Unsupported ARMFixup");
897 case ARMMCExpr::VK_ARM_HI16:
898 if (!isTargetDarwin() && EvaluateAsPCRel(E))
899 Kind = MCFixupKind(isThumb2()
900 ? ARM::fixup_t2_movt_hi16_pcrel
901 : ARM::fixup_arm_movt_hi16_pcrel);
903 Kind = MCFixupKind(isThumb2()
904 ? ARM::fixup_t2_movt_hi16
905 : ARM::fixup_arm_movt_hi16);
907 case ARMMCExpr::VK_ARM_LO16:
908 if (!isTargetDarwin() && EvaluateAsPCRel(E))
909 Kind = MCFixupKind(isThumb2()
910 ? ARM::fixup_t2_movw_lo16_pcrel
911 : ARM::fixup_arm_movw_lo16_pcrel);
913 Kind = MCFixupKind(isThumb2()
914 ? ARM::fixup_t2_movw_lo16
915 : ARM::fixup_arm_movw_lo16);
918 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
921 // If the expression doesn't have :upper16: or :lower16: on it,
922 // it's just a plain immediate expression, and those evaluate to
923 // the lower 16 bits of the expression regardless of whether
924 // we have a movt or a movw.
925 if (!isTargetDarwin() && EvaluateAsPCRel(E))
926 Kind = MCFixupKind(isThumb2()
927 ? ARM::fixup_t2_movw_lo16_pcrel
928 : ARM::fixup_arm_movw_lo16_pcrel);
930 Kind = MCFixupKind(isThumb2()
931 ? ARM::fixup_t2_movw_lo16
932 : ARM::fixup_arm_movw_lo16);
933 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
937 uint32_t ARMMCCodeEmitter::
938 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
939 SmallVectorImpl<MCFixup> &Fixups) const {
940 const MCOperand &MO = MI.getOperand(OpIdx);
941 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
942 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
943 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
944 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
945 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
946 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
947 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
948 unsigned SBits = getShiftOp(ShOp);
950 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
951 // amount. However, it would be an easy mistake to make so check here.
952 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
961 uint32_t Binary = Rm;
963 Binary |= SBits << 5;
964 Binary |= ShImm << 7;
970 uint32_t ARMMCCodeEmitter::
971 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
972 SmallVectorImpl<MCFixup> &Fixups) const {
974 // {13} 1 == imm12, 0 == Rm
977 const MCOperand &MO = MI.getOperand(OpIdx);
978 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
979 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
984 uint32_t ARMMCCodeEmitter::
985 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
986 SmallVectorImpl<MCFixup> &Fixups) const {
987 // {13} 1 == imm12, 0 == Rm
990 const MCOperand &MO = MI.getOperand(OpIdx);
991 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
992 unsigned Imm = MO1.getImm();
993 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
994 bool isReg = MO.getReg() != 0;
995 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
996 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
998 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
999 Binary <<= 7; // Shift amount is bits [11:7]
1000 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1001 Binary |= CTX.getRegisterInfo().getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1003 return Binary | (isAdd << 12) | (isReg << 13);
1006 uint32_t ARMMCCodeEmitter::
1007 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1008 SmallVectorImpl<MCFixup> &Fixups) const {
1011 const MCOperand &MO = MI.getOperand(OpIdx);
1012 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1013 bool isAdd = MO1.getImm() != 0;
1014 return CTX.getRegisterInfo().getEncodingValue(MO.getReg()) | (isAdd << 4);
1017 uint32_t ARMMCCodeEmitter::
1018 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1019 SmallVectorImpl<MCFixup> &Fixups) const {
1020 // {9} 1 == imm8, 0 == Rm
1022 // {7-4} imm7_4/zero
1024 const MCOperand &MO = MI.getOperand(OpIdx);
1025 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1026 unsigned Imm = MO1.getImm();
1027 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1028 bool isImm = MO.getReg() == 0;
1029 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1030 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1032 Imm8 = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1033 return Imm8 | (isAdd << 8) | (isImm << 9);
1036 uint32_t ARMMCCodeEmitter::
1037 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1038 SmallVectorImpl<MCFixup> &Fixups) const {
1039 // {13} 1 == imm8, 0 == Rm
1042 // {7-4} imm7_4/zero
1044 const MCOperand &MO = MI.getOperand(OpIdx);
1045 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1046 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1048 // If The first operand isn't a register, we have a label reference.
1050 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
1052 assert(MO.isExpr() && "Unexpected machine operand type!");
1053 const MCExpr *Expr = MO.getExpr();
1054 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1055 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1057 ++MCNumCPRelocations;
1058 return (Rn << 9) | (1 << 13);
1060 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1061 unsigned Imm = MO2.getImm();
1062 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1063 bool isImm = MO1.getReg() == 0;
1064 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1065 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1067 Imm8 = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
1068 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1071 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1072 uint32_t ARMMCCodeEmitter::
1073 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1074 SmallVectorImpl<MCFixup> &Fixups) const {
1077 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1078 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1079 "Unexpected base register!");
1081 // The immediate is already shifted for the implicit zeroes, so no change
1083 return MO1.getImm() & 0xff;
1086 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1087 uint32_t ARMMCCodeEmitter::
1088 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1089 SmallVectorImpl<MCFixup> &Fixups) const {
1093 const MCOperand &MO = MI.getOperand(OpIdx);
1094 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1095 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1096 unsigned Imm5 = MO1.getImm();
1097 return ((Imm5 & 0x1f) << 3) | Rn;
1100 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1101 uint32_t ARMMCCodeEmitter::
1102 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1103 SmallVectorImpl<MCFixup> &Fixups) const {
1104 const MCOperand MO = MI.getOperand(OpIdx);
1106 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
1107 return (MO.getImm() >> 2);
1110 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1111 uint32_t ARMMCCodeEmitter::
1112 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1113 SmallVectorImpl<MCFixup> &Fixups) const {
1115 // {8} = (U)nsigned (add == '1', sub == '0')
1119 // If The first operand isn't a register, we have a label reference.
1120 const MCOperand &MO = MI.getOperand(OpIdx);
1122 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
1124 isAdd = false; // 'U' bit is handled as part of the fixup.
1126 assert(MO.isExpr() && "Unexpected machine operand type!");
1127 const MCExpr *Expr = MO.getExpr();
1130 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1132 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1133 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1135 ++MCNumCPRelocations;
1137 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
1138 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1141 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1142 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1145 Binary |= (Reg << 9);
1149 unsigned ARMMCCodeEmitter::
1150 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1151 SmallVectorImpl<MCFixup> &Fixups) const {
1152 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1153 // shifted. The second is Rs, the amount to shift by, and the third specifies
1154 // the type of the shift.
1162 const MCOperand &MO = MI.getOperand(OpIdx);
1163 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1164 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1165 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1168 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1170 // Encode the shift opcode.
1172 unsigned Rs = MO1.getReg();
1174 // Set shift operand (bit[7:4]).
1180 default: llvm_unreachable("Unknown shift opc!");
1181 case ARM_AM::lsl: SBits = 0x1; break;
1182 case ARM_AM::lsr: SBits = 0x3; break;
1183 case ARM_AM::asr: SBits = 0x5; break;
1184 case ARM_AM::ror: SBits = 0x7; break;
1188 Binary |= SBits << 4;
1190 // Encode the shift operation Rs.
1191 // Encode Rs bit[11:8].
1192 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1193 return Binary | (CTX.getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift);
1196 unsigned ARMMCCodeEmitter::
1197 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1198 SmallVectorImpl<MCFixup> &Fixups) const {
1199 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1200 // shifted. The second is the amount to shift by.
1207 const MCOperand &MO = MI.getOperand(OpIdx);
1208 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1209 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1212 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1214 // Encode the shift opcode.
1217 // Set shift operand (bit[6:4]).
1222 // RRX - 110 and bit[11:8] clear.
1224 default: llvm_unreachable("Unknown shift opc!");
1225 case ARM_AM::lsl: SBits = 0x0; break;
1226 case ARM_AM::lsr: SBits = 0x2; break;
1227 case ARM_AM::asr: SBits = 0x4; break;
1228 case ARM_AM::ror: SBits = 0x6; break;
1234 // Encode shift_imm bit[11:7].
1235 Binary |= SBits << 4;
1236 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1237 assert(Offset < 32 && "Offset must be in range 0-31!");
1238 return Binary | (Offset << 7);
1242 unsigned ARMMCCodeEmitter::
1243 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1244 SmallVectorImpl<MCFixup> &Fixups) const {
1245 const MCOperand &MO1 = MI.getOperand(OpNum);
1246 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1247 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1249 // Encoded as [Rn, Rm, imm].
1250 // FIXME: Needs fixup support.
1251 unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
1253 Value |= CTX.getRegisterInfo().getEncodingValue(MO2.getReg());
1255 Value |= MO3.getImm();
1260 unsigned ARMMCCodeEmitter::
1261 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1262 SmallVectorImpl<MCFixup> &Fixups) const {
1263 const MCOperand &MO1 = MI.getOperand(OpNum);
1264 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1266 // FIXME: Needs fixup support.
1267 unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
1269 // Even though the immediate is 8 bits long, we need 9 bits in order
1270 // to represent the (inverse of the) sign bit.
1272 int32_t tmp = (int32_t)MO2.getImm();
1276 Value |= 256; // Set the ADD bit
1281 unsigned ARMMCCodeEmitter::
1282 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1283 SmallVectorImpl<MCFixup> &Fixups) const {
1284 const MCOperand &MO1 = MI.getOperand(OpNum);
1286 // FIXME: Needs fixup support.
1288 int32_t tmp = (int32_t)MO1.getImm();
1292 Value |= 256; // Set the ADD bit
1297 unsigned ARMMCCodeEmitter::
1298 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1299 SmallVectorImpl<MCFixup> &Fixups) const {
1300 const MCOperand &MO1 = MI.getOperand(OpNum);
1302 // FIXME: Needs fixup support.
1304 int32_t tmp = (int32_t)MO1.getImm();
1308 Value |= 4096; // Set the ADD bit
1309 Value |= tmp & 4095;
1313 unsigned ARMMCCodeEmitter::
1314 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1315 SmallVectorImpl<MCFixup> &Fixups) const {
1316 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1317 // shifted. The second is the amount to shift by.
1324 const MCOperand &MO = MI.getOperand(OpIdx);
1325 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1326 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1329 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1331 // Encode the shift opcode.
1333 // Set shift operand (bit[6:4]).
1339 default: llvm_unreachable("Unknown shift opc!");
1340 case ARM_AM::lsl: SBits = 0x0; break;
1341 case ARM_AM::lsr: SBits = 0x2; break;
1342 case ARM_AM::asr: SBits = 0x4; break;
1343 case ARM_AM::rrx: // FALLTHROUGH
1344 case ARM_AM::ror: SBits = 0x6; break;
1347 Binary |= SBits << 4;
1348 if (SOpc == ARM_AM::rrx)
1351 // Encode shift_imm bit[11:7].
1352 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1355 unsigned ARMMCCodeEmitter::
1356 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1357 SmallVectorImpl<MCFixup> &Fixups) const {
1358 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1360 const MCOperand &MO = MI.getOperand(Op);
1361 uint32_t v = ~MO.getImm();
1362 uint32_t lsb = countTrailingZeros(v);
1363 uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1364 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1365 return lsb | (msb << 5);
1368 unsigned ARMMCCodeEmitter::
1369 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1370 SmallVectorImpl<MCFixup> &Fixups) const {
1373 // {7-0} = Number of registers
1376 // {15-0} = Bitfield of GPRs.
1377 unsigned Reg = MI.getOperand(Op).getReg();
1378 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1379 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1381 unsigned Binary = 0;
1383 if (SPRRegs || DPRRegs) {
1385 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg);
1386 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1387 Binary |= (RegNo & 0x1f) << 8;
1391 Binary |= NumRegs * 2;
1393 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1394 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(MI.getOperand(I).getReg());
1395 Binary |= 1 << RegNo;
1402 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1403 /// with the alignment operand.
1404 unsigned ARMMCCodeEmitter::
1405 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1406 SmallVectorImpl<MCFixup> &Fixups) const {
1407 const MCOperand &Reg = MI.getOperand(Op);
1408 const MCOperand &Imm = MI.getOperand(Op + 1);
1410 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
1413 switch (Imm.getImm()) {
1417 case 8: Align = 0x01; break;
1418 case 16: Align = 0x02; break;
1419 case 32: Align = 0x03; break;
1422 return RegNo | (Align << 4);
1425 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1426 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1427 unsigned ARMMCCodeEmitter::
1428 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1429 SmallVectorImpl<MCFixup> &Fixups) const {
1430 const MCOperand &Reg = MI.getOperand(Op);
1431 const MCOperand &Imm = MI.getOperand(Op + 1);
1433 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
1436 switch (Imm.getImm()) {
1440 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1441 case 2: Align = 0x00; break;
1442 case 4: Align = 0x03; break;
1445 return RegNo | (Align << 4);
1449 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1450 /// alignment operand for use in VLD-dup instructions. This is the same as
1451 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1452 /// different for VLD4-dup.
1453 unsigned ARMMCCodeEmitter::
1454 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1455 SmallVectorImpl<MCFixup> &Fixups) const {
1456 const MCOperand &Reg = MI.getOperand(Op);
1457 const MCOperand &Imm = MI.getOperand(Op + 1);
1459 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
1462 switch (Imm.getImm()) {
1466 case 8: Align = 0x01; break;
1467 case 16: Align = 0x03; break;
1470 return RegNo | (Align << 4);
1473 unsigned ARMMCCodeEmitter::
1474 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1475 SmallVectorImpl<MCFixup> &Fixups) const {
1476 const MCOperand &MO = MI.getOperand(Op);
1477 if (MO.getReg() == 0) return 0x0D;
1478 return CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1481 unsigned ARMMCCodeEmitter::
1482 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1483 SmallVectorImpl<MCFixup> &Fixups) const {
1484 return 8 - MI.getOperand(Op).getImm();
1487 unsigned ARMMCCodeEmitter::
1488 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1489 SmallVectorImpl<MCFixup> &Fixups) const {
1490 return 16 - MI.getOperand(Op).getImm();
1493 unsigned ARMMCCodeEmitter::
1494 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1495 SmallVectorImpl<MCFixup> &Fixups) const {
1496 return 32 - MI.getOperand(Op).getImm();
1499 unsigned ARMMCCodeEmitter::
1500 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1501 SmallVectorImpl<MCFixup> &Fixups) const {
1502 return 64 - MI.getOperand(Op).getImm();
1505 void ARMMCCodeEmitter::
1506 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1507 SmallVectorImpl<MCFixup> &Fixups) const {
1508 // Pseudo instructions don't get encoded.
1509 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1510 uint64_t TSFlags = Desc.TSFlags;
1511 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1515 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1516 Size = Desc.getSize();
1518 llvm_unreachable("Unexpected instruction size!");
1520 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1521 // Thumb 32-bit wide instructions need to emit the high order halfword
1523 if (isThumb() && Size == 4) {
1524 EmitConstant(Binary >> 16, 2, OS);
1525 EmitConstant(Binary & 0xffff, 2, OS);
1527 EmitConstant(Binary, Size, OS);
1528 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1531 #include "ARMGenMCCodeEmitter.inc"