1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMMCTargetDesc.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMFixupKinds.h"
14 #include "llvm/ADT/StringSwitch.h"
15 #include "llvm/MC/MCAsmBackend.h"
16 #include "llvm/MC/MCAssembler.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDirectives.h"
19 #include "llvm/MC/MCELFObjectWriter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCFixupKindInfo.h"
22 #include "llvm/MC/MCMachObjectWriter.h"
23 #include "llvm/MC/MCObjectWriter.h"
24 #include "llvm/MC/MCSectionELF.h"
25 #include "llvm/MC/MCSectionMachO.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCValue.h"
28 #include "llvm/Support/ELF.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MachO.h"
31 #include "llvm/Support/raw_ostream.h"
35 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
37 ARMELFObjectWriter(uint8_t OSABI)
38 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
39 /*HasRelocationAddend*/ false) {}
42 class ARMAsmBackend : public MCAsmBackend {
43 const MCSubtargetInfo* STI;
44 bool isThumbMode; // Currently emitting Thumb code.
46 ARMAsmBackend(const Target &T, const StringRef TT)
47 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
48 isThumbMode(TT.startswith("thumb")) {}
54 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
57 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
60 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
61 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
62 // This table *must* be in the order that the fixup_* kinds are defined in
65 // Name Offset (bits) Size (bits) Flags
66 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
67 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
68 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
69 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
70 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
71 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
72 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
73 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
74 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
75 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
76 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
77 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
78 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
79 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
80 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
81 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
82 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
83 { "fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
84 { "fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
85 { "fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
86 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
87 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
88 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
89 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel |
90 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
91 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
92 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
93 { "fixup_arm_movt_hi16", 0, 20, 0 },
94 { "fixup_arm_movw_lo16", 0, 20, 0 },
95 { "fixup_t2_movt_hi16", 0, 20, 0 },
96 { "fixup_t2_movw_lo16", 0, 20, 0 },
97 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
98 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
99 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
100 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
103 if (Kind < FirstTargetFixupKind)
104 return MCAsmBackend::getFixupKindInfo(Kind);
106 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
108 return Infos[Kind - FirstTargetFixupKind];
111 /// processFixupValue - Target hook to process the literal value of a fixup
113 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
114 const MCFixup &Fixup, const MCFragment *DF,
115 MCValue &Target, uint64_t &Value,
119 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
120 uint64_t Value) const;
122 bool mayNeedRelaxation(const MCInst &Inst) const;
124 bool fixupNeedsRelaxation(const MCFixup &Fixup,
126 const MCRelaxableFragment *DF,
127 const MCAsmLayout &Layout) const;
129 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
131 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
133 void handleAssemblerFlag(MCAssemblerFlag Flag) {
145 unsigned getPointerSize() const { return 4; }
146 bool isThumb() const { return isThumbMode; }
147 void setIsThumb(bool it) { isThumbMode = it; }
149 } // end anonymous namespace
151 static unsigned getRelaxedOpcode(unsigned Op) {
154 case ARM::tBcc: return ARM::t2Bcc;
155 case ARM::tLDRpci: return ARM::t2LDRpci;
156 case ARM::tADR: return ARM::t2ADR;
157 case ARM::tB: return ARM::t2B;
158 case ARM::tCBZ: return ARM::tHINT;
159 case ARM::tCBNZ: return ARM::tHINT;
163 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
164 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
169 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
171 const MCRelaxableFragment *DF,
172 const MCAsmLayout &Layout) const {
173 switch ((unsigned)Fixup.getKind()) {
174 case ARM::fixup_arm_thumb_br: {
175 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
176 // low bit being an implied zero. There's an implied +4 offset for the
177 // branch, so we adjust the other way here to determine what's
180 // Relax if the value is too big for a (signed) i8.
181 int64_t Offset = int64_t(Value) - 4;
182 return Offset > 2046 || Offset < -2048;
184 case ARM::fixup_arm_thumb_bcc: {
185 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
186 // low bit being an implied zero. There's an implied +4 offset for the
187 // branch, so we adjust the other way here to determine what's
190 // Relax if the value is too big for a (signed) i8.
191 int64_t Offset = int64_t(Value) - 4;
192 return Offset > 254 || Offset < -256;
194 case ARM::fixup_thumb_adr_pcrel_10:
195 case ARM::fixup_arm_thumb_cp: {
196 // If the immediate is negative, greater than 1020, or not a multiple
197 // of four, the wide version of the instruction must be used.
198 int64_t Offset = int64_t(Value) - 4;
199 return Offset > 1020 || Offset < 0 || Offset & 3;
201 case ARM::fixup_arm_thumb_cb:
202 // If we have a Thumb CBZ or CBNZ instruction and its target is the next
203 // instruction it is is actually out of range for the instruction.
204 // It will be changed to a NOP.
205 int64_t Offset = (Value & ~1);
208 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!");
211 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
212 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
214 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
215 if (RelaxedOp == Inst.getOpcode()) {
216 SmallString<256> Tmp;
217 raw_svector_ostream OS(Tmp);
218 Inst.dump_pretty(OS);
220 report_fatal_error("unexpected instruction to relax: " + OS.str());
223 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we
224 // have to change the operands too.
225 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
226 RelaxedOp == ARM::tHINT) {
227 Res.setOpcode(RelaxedOp);
228 Res.addOperand(MCOperand::CreateImm(0));
229 Res.addOperand(MCOperand::CreateImm(14));
230 Res.addOperand(MCOperand::CreateReg(0));
234 // The rest of instructions we're relaxing have the same operands.
235 // We just need to update to the proper opcode.
237 Res.setOpcode(RelaxedOp);
240 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
241 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
242 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
243 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0
244 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
246 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
247 : Thumb1_16bitNopEncoding;
248 uint64_t NumNops = Count / 2;
249 for (uint64_t i = 0; i != NumNops; ++i)
250 OW->Write16(nopEncoding);
256 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding
258 uint64_t NumNops = Count / 4;
259 for (uint64_t i = 0; i != NumNops; ++i)
260 OW->Write32(nopEncoding);
261 // FIXME: should this function return false when unable to write exactly
262 // 'Count' bytes with NOP encodings?
264 default: break; // No leftover bytes to write
265 case 1: OW->Write8(0); break;
266 case 2: OW->Write16(0); break;
267 case 3: OW->Write16(0); OW->Write8(0xa0); break;
273 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
274 MCContext *Ctx = NULL) {
275 unsigned Kind = Fixup.getKind();
278 llvm_unreachable("Unknown fixup kind!");
283 case ARM::fixup_arm_movt_hi16:
286 case ARM::fixup_arm_movw_lo16:
287 case ARM::fixup_arm_movt_hi16_pcrel:
288 case ARM::fixup_arm_movw_lo16_pcrel: {
289 unsigned Hi4 = (Value & 0xF000) >> 12;
290 unsigned Lo12 = Value & 0x0FFF;
291 // inst{19-16} = Hi4;
292 // inst{11-0} = Lo12;
293 Value = (Hi4 << 16) | (Lo12);
296 case ARM::fixup_t2_movt_hi16:
299 case ARM::fixup_t2_movw_lo16:
300 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
301 // the other hi16 fixup?
302 case ARM::fixup_t2_movw_lo16_pcrel: {
303 unsigned Hi4 = (Value & 0xF000) >> 12;
304 unsigned i = (Value & 0x800) >> 11;
305 unsigned Mid3 = (Value & 0x700) >> 8;
306 unsigned Lo8 = Value & 0x0FF;
307 // inst{19-16} = Hi4;
309 // inst{14-12} = Mid3;
311 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
312 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
313 swapped |= (Value & 0x0000FFFF) << 16;
316 case ARM::fixup_arm_ldst_pcrel_12:
317 // ARM PC-relative values are offset by 8.
320 case ARM::fixup_t2_ldst_pcrel_12: {
321 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
324 if ((int64_t)Value < 0) {
328 if (Ctx && Value >= 4096)
329 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
330 Value |= isAdd << 23;
332 // Same addressing mode as fixup_arm_pcrel_10,
333 // but with 16-bit halfwords swapped.
334 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
335 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
336 swapped |= (Value & 0x0000FFFF) << 16;
342 case ARM::fixup_thumb_adr_pcrel_10:
343 return ((Value - 4) >> 2) & 0xff;
344 case ARM::fixup_arm_adr_pcrel_12: {
345 // ARM PC-relative values are offset by 8.
347 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
348 if ((int64_t)Value < 0) {
352 if (Ctx && ARM_AM::getSOImmVal(Value) == -1)
353 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
354 // Encode the immediate and shift the opcode into place.
355 return ARM_AM::getSOImmVal(Value) | (opc << 21);
358 case ARM::fixup_t2_adr_pcrel_12: {
361 if ((int64_t)Value < 0) {
366 uint32_t out = (opc << 21);
367 out |= (Value & 0x800) << 15;
368 out |= (Value & 0x700) << 4;
369 out |= (Value & 0x0FF);
371 uint64_t swapped = (out & 0xFFFF0000) >> 16;
372 swapped |= (out & 0x0000FFFF) << 16;
376 case ARM::fixup_arm_condbranch:
377 case ARM::fixup_arm_uncondbranch:
378 case ARM::fixup_arm_uncondbl:
379 case ARM::fixup_arm_condbl:
380 case ARM::fixup_arm_blx:
381 // These values don't encode the low two bits since they're always zero.
382 // Offset by 8 just as above.
383 return 0xffffff & ((Value - 8) >> 2);
384 case ARM::fixup_t2_uncondbranch: {
386 Value >>= 1; // Low bit is not encoded.
389 bool I = Value & 0x800000;
390 bool J1 = Value & 0x400000;
391 bool J2 = Value & 0x200000;
395 out |= I << 26; // S bit
396 out |= !J1 << 13; // J1 bit
397 out |= !J2 << 11; // J2 bit
398 out |= (Value & 0x1FF800) << 5; // imm6 field
399 out |= (Value & 0x0007FF); // imm11 field
401 uint64_t swapped = (out & 0xFFFF0000) >> 16;
402 swapped |= (out & 0x0000FFFF) << 16;
405 case ARM::fixup_t2_condbranch: {
407 Value >>= 1; // Low bit is not encoded.
410 out |= (Value & 0x80000) << 7; // S bit
411 out |= (Value & 0x40000) >> 7; // J2 bit
412 out |= (Value & 0x20000) >> 4; // J1 bit
413 out |= (Value & 0x1F800) << 5; // imm6 field
414 out |= (Value & 0x007FF); // imm11 field
416 uint32_t swapped = (out & 0xFFFF0000) >> 16;
417 swapped |= (out & 0x0000FFFF) << 16;
420 case ARM::fixup_arm_thumb_bl: {
421 // The value doesn't encode the low bit (always zero) and is offset by
422 // four. The 32-bit immediate value is encoded as
423 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
424 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
425 // The value is encoded into disjoint bit positions in the destination
426 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
427 // J = either J1 or J2 bit
429 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
431 // Note that the halfwords are stored high first, low second; so we need
432 // to transpose the fixup value here to map properly.
433 uint32_t offset = (Value - 4) >> 1;
434 uint32_t signBit = (offset & 0x800000) >> 23;
435 uint32_t I1Bit = (offset & 0x400000) >> 22;
436 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
437 uint32_t I2Bit = (offset & 0x200000) >> 21;
438 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
439 uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
440 uint32_t imm11Bits = (offset & 0x000007FF);
443 uint32_t firstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
444 uint32_t secondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
445 (uint16_t)imm11Bits);
446 Binary |= secondHalf << 16;
451 case ARM::fixup_arm_thumb_blx: {
452 // The value doesn't encode the low two bits (always zero) and is offset by
453 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
454 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
455 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
456 // The value is encoded into disjoint bit positions in the destination
457 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
458 // J = either J1 or J2 bit, 0 = zero.
460 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
462 // Note that the halfwords are stored high first, low second; so we need
463 // to transpose the fixup value here to map properly.
464 uint32_t offset = (Value - 2) >> 2;
465 uint32_t signBit = (offset & 0x400000) >> 22;
466 uint32_t I1Bit = (offset & 0x200000) >> 21;
467 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
468 uint32_t I2Bit = (offset & 0x100000) >> 20;
469 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
470 uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
471 uint32_t imm10LBits = (offset & 0x3FF);
474 uint32_t firstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
475 uint32_t secondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
476 ((uint16_t)imm10LBits) << 1);
477 Binary |= secondHalf << 16;
481 case ARM::fixup_arm_thumb_cp:
482 // Offset by 4, and don't encode the low two bits. Two bytes of that
483 // 'off by 4' is implicitly handled by the half-word ordering of the
484 // Thumb encoding, so we only need to adjust by 2 here.
485 return ((Value - 2) >> 2) & 0xff;
486 case ARM::fixup_arm_thumb_cb: {
487 // Offset by 4 and don't encode the lower bit, which is always 0.
488 uint32_t Binary = (Value - 4) >> 1;
489 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
491 case ARM::fixup_arm_thumb_br:
492 // Offset by 4 and don't encode the lower bit, which is always 0.
493 return ((Value - 4) >> 1) & 0x7ff;
494 case ARM::fixup_arm_thumb_bcc:
495 // Offset by 4 and don't encode the lower bit, which is always 0.
496 return ((Value - 4) >> 1) & 0xff;
497 case ARM::fixup_arm_pcrel_10_unscaled: {
498 Value = Value - 8; // ARM fixups offset by an additional word and don't
499 // need to adjust for the half-word ordering.
501 if ((int64_t)Value < 0) {
505 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
506 if (Ctx && Value >= 256)
507 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
508 Value = (Value & 0xf) | ((Value & 0xf0) << 4);
509 return Value | (isAdd << 23);
511 case ARM::fixup_arm_pcrel_10:
512 Value = Value - 4; // ARM fixups offset by an additional word and don't
513 // need to adjust for the half-word ordering.
515 case ARM::fixup_t2_pcrel_10: {
516 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
519 if ((int64_t)Value < 0) {
523 // These values don't encode the low two bits since they're always zero.
525 if (Ctx && Value >= 256)
526 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
527 Value |= isAdd << 23;
529 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
531 if (Kind == ARM::fixup_t2_pcrel_10) {
532 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
533 swapped |= (Value & 0x0000FFFF) << 16;
542 void ARMAsmBackend::processFixupValue(const MCAssembler &Asm,
543 const MCAsmLayout &Layout,
544 const MCFixup &Fixup,
545 const MCFragment *DF,
546 MCValue &Target, uint64_t &Value,
548 const MCSymbolRefExpr *A = Target.getSymA();
549 // Some fixups to thumb function symbols need the low bit (thumb bit)
551 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
552 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
553 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 &&
554 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 &&
555 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 &&
556 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
558 const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
559 if (Asm.isThumbFunc(&Sym))
563 // We must always generate a relocation for BL/BLX instructions if we have
564 // a symbol to reference, as the linker relies on knowing the destination
565 // symbol's thumb-ness to get interworking right.
566 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx ||
567 (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl ||
568 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx ||
569 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl ||
570 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl))
573 // Try to get the encoded value for the fixup as-if we're mapping it into
574 // the instruction. This allows adjustFixupValue() to issue a diagnostic
575 // if the value aren't invalid.
576 (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
579 /// getFixupKindNumBytes - The number of bytes the fixup may change.
580 static unsigned getFixupKindNumBytes(unsigned Kind) {
583 llvm_unreachable("Unknown fixup kind!");
586 case ARM::fixup_arm_thumb_bcc:
587 case ARM::fixup_arm_thumb_cp:
588 case ARM::fixup_thumb_adr_pcrel_10:
592 case ARM::fixup_arm_thumb_br:
593 case ARM::fixup_arm_thumb_cb:
596 case ARM::fixup_arm_pcrel_10_unscaled:
597 case ARM::fixup_arm_ldst_pcrel_12:
598 case ARM::fixup_arm_pcrel_10:
599 case ARM::fixup_arm_adr_pcrel_12:
600 case ARM::fixup_arm_uncondbl:
601 case ARM::fixup_arm_condbl:
602 case ARM::fixup_arm_blx:
603 case ARM::fixup_arm_condbranch:
604 case ARM::fixup_arm_uncondbranch:
608 case ARM::fixup_t2_ldst_pcrel_12:
609 case ARM::fixup_t2_condbranch:
610 case ARM::fixup_t2_uncondbranch:
611 case ARM::fixup_t2_pcrel_10:
612 case ARM::fixup_t2_adr_pcrel_12:
613 case ARM::fixup_arm_thumb_bl:
614 case ARM::fixup_arm_thumb_blx:
615 case ARM::fixup_arm_movt_hi16:
616 case ARM::fixup_arm_movw_lo16:
617 case ARM::fixup_arm_movt_hi16_pcrel:
618 case ARM::fixup_arm_movw_lo16_pcrel:
619 case ARM::fixup_t2_movt_hi16:
620 case ARM::fixup_t2_movw_lo16:
621 case ARM::fixup_t2_movt_hi16_pcrel:
622 case ARM::fixup_t2_movw_lo16_pcrel:
627 void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
628 unsigned DataSize, uint64_t Value) const {
629 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
630 Value = adjustFixupValue(Fixup, Value);
631 if (!Value) return; // Doesn't change encoding.
633 unsigned Offset = Fixup.getOffset();
634 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
636 // For each byte of the fragment that the fixup touches, mask in the bits from
637 // the fixup value. The Value has been "split up" into the appropriate
639 for (unsigned i = 0; i != NumBytes; ++i)
640 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
645 // FIXME: This should be in a separate file.
646 // ELF is an ELF of course...
647 class ELFARMAsmBackend : public ARMAsmBackend {
650 ELFARMAsmBackend(const Target &T, const StringRef TT,
652 : ARMAsmBackend(T, TT), OSABI(_OSABI) { }
654 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
655 return createARMELFObjectWriter(OS, OSABI);
659 // FIXME: This should be in a separate file.
660 class DarwinARMAsmBackend : public ARMAsmBackend {
662 const MachO::CPUSubTypeARM Subtype;
663 DarwinARMAsmBackend(const Target &T, const StringRef TT,
664 MachO::CPUSubTypeARM st)
665 : ARMAsmBackend(T, TT), Subtype(st) {
666 HasDataInCodeSupport = true;
669 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
670 return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
675 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
680 } // end anonymous namespace
682 MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
683 const MCRegisterInfo &MRI,
684 StringRef TT, StringRef CPU) {
685 Triple TheTriple(TT);
687 if (TheTriple.isOSBinFormatMachO()) {
688 MachO::CPUSubTypeARM CS =
689 StringSwitch<MachO::CPUSubTypeARM>(TheTriple.getArchName())
690 .Cases("armv4t", "thumbv4t", MachO::CPU_SUBTYPE_ARM_V4T)
691 .Cases("armv5e", "thumbv5e", MachO::CPU_SUBTYPE_ARM_V5TEJ)
692 .Cases("armv6", "thumbv6", MachO::CPU_SUBTYPE_ARM_V6)
693 .Cases("armv6m", "thumbv6m", MachO::CPU_SUBTYPE_ARM_V6M)
694 .Cases("armv7em", "thumbv7em", MachO::CPU_SUBTYPE_ARM_V7EM)
695 .Cases("armv7k", "thumbv7k", MachO::CPU_SUBTYPE_ARM_V7K)
696 .Cases("armv7m", "thumbv7m", MachO::CPU_SUBTYPE_ARM_V7M)
697 .Cases("armv7s", "thumbv7s", MachO::CPU_SUBTYPE_ARM_V7S)
698 .Default(MachO::CPU_SUBTYPE_ARM_V7);
700 return new DarwinARMAsmBackend(T, TT, CS);
704 // FIXME: Introduce yet another checker but assert(0).
705 if (TheTriple.isOSBinFormatCOFF())
706 assert(0 && "Windows not supported on ARM");
709 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
710 return new ELFARMAsmBackend(T, TT, OSABI);