1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMMCTargetDesc.h"
11 #include "MCTargetDesc/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMFixupKinds.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/MC/MCAssembler.h"
16 #include "llvm/MC/MCDirectives.h"
17 #include "llvm/MC/MCELFObjectWriter.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCMachObjectWriter.h"
20 #include "llvm/MC/MCObjectWriter.h"
21 #include "llvm/MC/MCSectionELF.h"
22 #include "llvm/MC/MCSectionMachO.h"
23 #include "llvm/MC/MCAsmBackend.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Object/MachOFormat.h"
26 #include "llvm/Support/ELF.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
32 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
34 ARMELFObjectWriter(Triple::OSType OSType)
35 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSType, ELF::EM_ARM,
36 /*HasRelocationAddend*/ false) {}
39 class ARMAsmBackend : public MCAsmBackend {
40 const MCSubtargetInfo* STI;
41 bool isThumbMode; // Currently emitting Thumb code.
43 ARMAsmBackend(const Target &T, const StringRef TT)
44 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
45 isThumbMode(TT.startswith("thumb")) {}
51 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
54 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
57 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
58 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
59 // This table *must* be in the order that the fixup_* kinds are defined in
62 // Name Offset (bits) Size (bits) Flags
63 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
64 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
65 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
66 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
67 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
68 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
69 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
70 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
71 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
72 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
73 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
74 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
75 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
76 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
77 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
78 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
79 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
80 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
81 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
82 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
83 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
84 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
85 { "fixup_arm_movt_hi16", 0, 20, 0 },
86 { "fixup_arm_movw_lo16", 0, 20, 0 },
87 { "fixup_t2_movt_hi16", 0, 20, 0 },
88 { "fixup_t2_movw_lo16", 0, 20, 0 },
89 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
90 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
91 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
92 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
95 if (Kind < FirstTargetFixupKind)
96 return MCAsmBackend::getFixupKindInfo(Kind);
98 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
100 return Infos[Kind - FirstTargetFixupKind];
103 bool MayNeedRelaxation(const MCInst &Inst) const;
105 bool fixupNeedsRelaxation(const MCFixup &Fixup,
107 const MCInstFragment *DF,
108 const MCAsmLayout &Layout) const;
110 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
112 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
114 void HandleAssemblerFlag(MCAssemblerFlag Flag) {
126 unsigned getPointerSize() const { return 4; }
127 bool isThumb() const { return isThumbMode; }
128 void setIsThumb(bool it) { isThumbMode = it; }
130 } // end anonymous namespace
132 static unsigned getRelaxedOpcode(unsigned Op) {
135 case ARM::tBcc: return ARM::t2Bcc;
139 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
140 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
145 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
147 const MCInstFragment *DF,
148 const MCAsmLayout &Layout) const {
149 // FIXME: This isn't correct for ARM. Just moving the "generic" logic
150 // into the targets for now.
152 // Relax if the value is too big for a (signed) i8.
153 return int64_t(Value) != int64_t(int8_t(Value));
156 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
157 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
159 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
160 if (RelaxedOp == Inst.getOpcode()) {
161 SmallString<256> Tmp;
162 raw_svector_ostream OS(Tmp);
163 Inst.dump_pretty(OS);
165 report_fatal_error("unexpected instruction to relax: " + OS.str());
168 // The instructions we're relaxing have (so far) the same operands.
169 // We just need to update to the proper opcode.
171 Res.setOpcode(RelaxedOp);
174 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
175 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
176 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
177 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0
178 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
180 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
181 : Thumb1_16bitNopEncoding;
182 uint64_t NumNops = Count / 2;
183 for (uint64_t i = 0; i != NumNops; ++i)
184 OW->Write16(nopEncoding);
190 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding
192 uint64_t NumNops = Count / 4;
193 for (uint64_t i = 0; i != NumNops; ++i)
194 OW->Write32(nopEncoding);
195 // FIXME: should this function return false when unable to write exactly
196 // 'Count' bytes with NOP encodings?
198 default: break; // No leftover bytes to write
199 case 1: OW->Write8(0); break;
200 case 2: OW->Write16(0); break;
201 case 3: OW->Write16(0); OW->Write8(0xa0); break;
207 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
210 llvm_unreachable("Unknown fixup kind!");
215 case ARM::fixup_arm_movt_hi16:
218 case ARM::fixup_arm_movw_lo16:
219 case ARM::fixup_arm_movt_hi16_pcrel:
220 case ARM::fixup_arm_movw_lo16_pcrel: {
221 unsigned Hi4 = (Value & 0xF000) >> 12;
222 unsigned Lo12 = Value & 0x0FFF;
223 // inst{19-16} = Hi4;
224 // inst{11-0} = Lo12;
225 Value = (Hi4 << 16) | (Lo12);
228 case ARM::fixup_t2_movt_hi16:
231 case ARM::fixup_t2_movw_lo16:
232 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
233 // the other hi16 fixup?
234 case ARM::fixup_t2_movw_lo16_pcrel: {
235 unsigned Hi4 = (Value & 0xF000) >> 12;
236 unsigned i = (Value & 0x800) >> 11;
237 unsigned Mid3 = (Value & 0x700) >> 8;
238 unsigned Lo8 = Value & 0x0FF;
239 // inst{19-16} = Hi4;
241 // inst{14-12} = Mid3;
243 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
244 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
245 swapped |= (Value & 0x0000FFFF) << 16;
248 case ARM::fixup_arm_ldst_pcrel_12:
249 // ARM PC-relative values are offset by 8.
252 case ARM::fixup_t2_ldst_pcrel_12: {
253 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
256 if ((int64_t)Value < 0) {
260 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
261 Value |= isAdd << 23;
263 // Same addressing mode as fixup_arm_pcrel_10,
264 // but with 16-bit halfwords swapped.
265 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
266 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
267 swapped |= (Value & 0x0000FFFF) << 16;
273 case ARM::fixup_thumb_adr_pcrel_10:
274 return ((Value - 4) >> 2) & 0xff;
275 case ARM::fixup_arm_adr_pcrel_12: {
276 // ARM PC-relative values are offset by 8.
278 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
279 if ((int64_t)Value < 0) {
283 assert(ARM_AM::getSOImmVal(Value) != -1 &&
284 "Out of range pc-relative fixup value!");
285 // Encode the immediate and shift the opcode into place.
286 return ARM_AM::getSOImmVal(Value) | (opc << 21);
289 case ARM::fixup_t2_adr_pcrel_12: {
292 if ((int64_t)Value < 0) {
297 uint32_t out = (opc << 21);
298 out |= (Value & 0x800) << 15;
299 out |= (Value & 0x700) << 4;
300 out |= (Value & 0x0FF);
302 uint64_t swapped = (out & 0xFFFF0000) >> 16;
303 swapped |= (out & 0x0000FFFF) << 16;
307 case ARM::fixup_arm_condbranch:
308 case ARM::fixup_arm_uncondbranch:
309 // These values don't encode the low two bits since they're always zero.
310 // Offset by 8 just as above.
311 return 0xffffff & ((Value - 8) >> 2);
312 case ARM::fixup_t2_uncondbranch: {
314 Value >>= 1; // Low bit is not encoded.
317 bool I = Value & 0x800000;
318 bool J1 = Value & 0x400000;
319 bool J2 = Value & 0x200000;
323 out |= I << 26; // S bit
324 out |= !J1 << 13; // J1 bit
325 out |= !J2 << 11; // J2 bit
326 out |= (Value & 0x1FF800) << 5; // imm6 field
327 out |= (Value & 0x0007FF); // imm11 field
329 uint64_t swapped = (out & 0xFFFF0000) >> 16;
330 swapped |= (out & 0x0000FFFF) << 16;
333 case ARM::fixup_t2_condbranch: {
335 Value >>= 1; // Low bit is not encoded.
338 out |= (Value & 0x80000) << 7; // S bit
339 out |= (Value & 0x40000) >> 7; // J2 bit
340 out |= (Value & 0x20000) >> 4; // J1 bit
341 out |= (Value & 0x1F800) << 5; // imm6 field
342 out |= (Value & 0x007FF); // imm11 field
344 uint32_t swapped = (out & 0xFFFF0000) >> 16;
345 swapped |= (out & 0x0000FFFF) << 16;
348 case ARM::fixup_arm_thumb_bl: {
349 // The value doesn't encode the low bit (always zero) and is offset by
350 // four. The value is encoded into disjoint bit positions in the destination
351 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
353 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
355 // Note that the halfwords are stored high first, low second; so we need
356 // to transpose the fixup value here to map properly.
357 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0;
359 Value = 0x3fffff & ((Value - 4) >> 1);
360 Binary = (Value & 0x7ff) << 16; // Low imm11 value.
361 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
362 Binary |= isNeg << 10; // Sign bit.
365 case ARM::fixup_arm_thumb_blx: {
366 // The value doesn't encode the low two bits (always zero) and is offset by
367 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
368 // positions in the destination opcode. x = unchanged, I = immediate value
369 // bit, S = sign extension bit, 0 = zero.
371 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
373 // Note that the halfwords are stored high first, low second; so we need
374 // to transpose the fixup value here to map properly.
375 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0;
377 Value = 0xfffff & ((Value - 2) >> 2);
378 Binary = (Value & 0x3ff) << 17; // Low imm10L value.
379 Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
380 Binary |= isNeg << 10; // Sign bit.
383 case ARM::fixup_arm_thumb_cp:
384 // Offset by 4, and don't encode the low two bits. Two bytes of that
385 // 'off by 4' is implicitly handled by the half-word ordering of the
386 // Thumb encoding, so we only need to adjust by 2 here.
387 return ((Value - 2) >> 2) & 0xff;
388 case ARM::fixup_arm_thumb_cb: {
389 // Offset by 4 and don't encode the lower bit, which is always 0.
390 uint32_t Binary = (Value - 4) >> 1;
391 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
393 case ARM::fixup_arm_thumb_br:
394 // Offset by 4 and don't encode the lower bit, which is always 0.
395 return ((Value - 4) >> 1) & 0x7ff;
396 case ARM::fixup_arm_thumb_bcc:
397 // Offset by 4 and don't encode the lower bit, which is always 0.
398 return ((Value - 4) >> 1) & 0xff;
399 case ARM::fixup_arm_pcrel_10:
400 Value = Value - 4; // ARM fixups offset by an additional word and don't
401 // need to adjust for the half-word ordering.
403 case ARM::fixup_t2_pcrel_10: {
404 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
407 if ((int64_t)Value < 0) {
411 // These values don't encode the low two bits since they're always zero.
413 assert ((Value < 256) && "Out of range pc-relative fixup value!");
414 Value |= isAdd << 23;
416 // Same addressing mode as fixup_arm_pcrel_10,
417 // but with 16-bit halfwords swapped.
418 if (Kind == ARM::fixup_t2_pcrel_10) {
419 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
420 swapped |= (Value & 0x0000FFFF) << 16;
431 // FIXME: This should be in a separate file.
432 // ELF is an ELF of course...
433 class ELFARMAsmBackend : public ARMAsmBackend {
435 Triple::OSType OSType;
436 ELFARMAsmBackend(const Target &T, const StringRef TT,
437 Triple::OSType _OSType)
438 : ARMAsmBackend(T, TT), OSType(_OSType) { }
440 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
441 uint64_t Value) const;
443 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
444 return createELFObjectWriter(new ARMELFObjectWriter(OSType), OS,
445 /*IsLittleEndian*/ true);
449 // FIXME: Raise this to share code between Darwin and ELF.
450 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
451 unsigned DataSize, uint64_t Value) const {
452 unsigned NumBytes = 4; // FIXME: 2 for Thumb
453 Value = adjustFixupValue(Fixup.getKind(), Value);
454 if (!Value) return; // Doesn't change encoding.
456 unsigned Offset = Fixup.getOffset();
458 // For each byte of the fragment that the fixup touches, mask in the bits from
459 // the fixup value. The Value has been "split up" into the appropriate
461 for (unsigned i = 0; i != NumBytes; ++i)
462 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
465 // FIXME: This should be in a separate file.
466 class DarwinARMAsmBackend : public ARMAsmBackend {
468 const object::mach::CPUSubtypeARM Subtype;
469 DarwinARMAsmBackend(const Target &T, const StringRef TT,
470 object::mach::CPUSubtypeARM st)
471 : ARMAsmBackend(T, TT), Subtype(st) { }
473 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
474 return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
475 object::mach::CTM_ARM,
479 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
480 uint64_t Value) const;
482 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
487 /// getFixupKindNumBytes - The number of bytes the fixup may change.
488 static unsigned getFixupKindNumBytes(unsigned Kind) {
491 llvm_unreachable("Unknown fixup kind!");
494 case ARM::fixup_arm_thumb_bcc:
495 case ARM::fixup_arm_thumb_cp:
496 case ARM::fixup_thumb_adr_pcrel_10:
500 case ARM::fixup_arm_thumb_br:
501 case ARM::fixup_arm_thumb_cb:
504 case ARM::fixup_arm_ldst_pcrel_12:
505 case ARM::fixup_arm_pcrel_10:
506 case ARM::fixup_arm_adr_pcrel_12:
507 case ARM::fixup_arm_condbranch:
508 case ARM::fixup_arm_uncondbranch:
512 case ARM::fixup_t2_ldst_pcrel_12:
513 case ARM::fixup_t2_condbranch:
514 case ARM::fixup_t2_uncondbranch:
515 case ARM::fixup_t2_pcrel_10:
516 case ARM::fixup_t2_adr_pcrel_12:
517 case ARM::fixup_arm_thumb_bl:
518 case ARM::fixup_arm_thumb_blx:
519 case ARM::fixup_arm_movt_hi16:
520 case ARM::fixup_arm_movw_lo16:
521 case ARM::fixup_arm_movt_hi16_pcrel:
522 case ARM::fixup_arm_movw_lo16_pcrel:
523 case ARM::fixup_t2_movt_hi16:
524 case ARM::fixup_t2_movw_lo16:
525 case ARM::fixup_t2_movt_hi16_pcrel:
526 case ARM::fixup_t2_movw_lo16_pcrel:
531 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
532 unsigned DataSize, uint64_t Value) const {
533 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
534 Value = adjustFixupValue(Fixup.getKind(), Value);
535 if (!Value) return; // Doesn't change encoding.
537 unsigned Offset = Fixup.getOffset();
538 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
540 // For each byte of the fragment that the fixup touches, mask in the
541 // bits from the fixup value.
542 for (unsigned i = 0; i != NumBytes; ++i)
543 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
546 } // end anonymous namespace
548 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) {
549 Triple TheTriple(TT);
551 if (TheTriple.isOSDarwin()) {
552 if (TheTriple.getArchName() == "armv4t" ||
553 TheTriple.getArchName() == "thumbv4t")
554 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T);
555 else if (TheTriple.getArchName() == "armv5e" ||
556 TheTriple.getArchName() == "thumbv5e")
557 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ);
558 else if (TheTriple.getArchName() == "armv6" ||
559 TheTriple.getArchName() == "thumbv6")
560 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6);
561 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7);
564 if (TheTriple.isOSWindows())
565 assert(0 && "Windows not supported on ARM");
567 return new ELFARMAsmBackend(T, TT, Triple(TT).getOS());